The present invention relates to two terminal resistive memory and more particularly to a memory array employing a two terminal resistive memory element driven by a vertical selector channel formed by selective epitaxial semiconductor growth.
The ever-increasing demand for data storage has led a push for the development of new and improved memory structures. Traditionally data has been stored in an array of transistors which can be employed as switches to store data as a one (1) and zero (0) memory states. Ideally, data storage systems can operate quickly, at low energy consumption and can maintain stored data over a long period of time without compromise of data integrity. Recently, researchers have looked to memory storage employing memory cells other than pure transistor storage, such as through the use of two terminal resistive switches.
Various types of two terminal resistive switches can be used to store data. One type of two terminal resistive switching technology that can be used to store data is Magnetic Random-Access Memory (MRAM). Magnetic Random-Access Memory (MRAM) is a non-volatile data memory technology that stores data using magnetoresistive cells such as Magnetoresistive Tunnel Junction (MTJ) cells. At their most basic level, such MTJ elements include first and second magnetic layers that are separated by a thin, non-magnetic layer such as a tunnel barrier layer, which can be constructed of a material such as Mg—O. The first magnetic layer, which can be referred to as a reference layer, has a magnetization that is fixed in a direction that is perpendicular to that plane of the layer. The second magnetic layer, which can be referred to as a magnetic free layer, has a magnetization that is free to move so that it can be oriented in either of two directions that are both generally perpendicular to the plane of the magnetic free layer. Therefore, the magnetization of the free layer can be either parallel with the magnetization of the reference layer or anti-parallel with the direction of the reference layer (i.e. opposite to the direction of the reference layer).
The electrical resistance through the MTJ element in a direction perpendicular to the planes of the layers changes with the relative orientations of the magnetizations of the magnetic reference layer and magnetic free layer. When the magnetization of the magnetic free layer is oriented in the same direction as the magnetization of the magnetic reference layer, the electrical resistance through the MTJ element is at its lowest electrical resistance state. Conversely, when the magnetization of the magnetic free layer is in a direction that is opposite to that of the magnetic reference layer, the electrical resistance across the MTJ element is at its highest electrical resistance state.
The switching of the MTJ element between high and low resistance states results from electron spin transfer. An electron has a spin orientation. Generally, electrons flowing through a conductive material have random spin orientations with no net spin orientation. However, when electrons flow through a magnetized layer, the spin orientations of the electrons become aligned so that there is a net aligned orientation of electrons flowing through the magnetic layer, and the orientation of this alignment is dependent on the orientation of the magnetization of the magnetic layer through which they travel. When the orientations of the magnetizations of the free and reference layer are oriented in the same direction, the majority spin of the electrons in the free layer is in the same direction as the orientation of the majority spin of the electrons in the reference layer. Because these electron spins are in generally the same direction, the electrons can pass relatively easily through the tunnel barrier layer. However, if the orientations of the magnetizations of the free and reference layers are opposite to one another, the spin of majority electrons in the free layer will be generally opposite to the majority spin of electrons in the reference layer. In this case, electrons cannot easily pass through the barrier layer, resulting in a higher electrical resistance through the MTJ stack.
Because the MTJ element can be switched between low and high electrical resistance states, it can be used as a memory element to store a bit of data. For example, the low resistance state can be read as a “0”, whereas the high resistance state can be read as a “1”. In addition, because the magnetic orientation of the magnetic free layer remains in its switched orientation without any electrical power to the element, it provides a robust, non-volatile data memory bit.
To write a bit of data to the MTJ cell, the magnetic orientation of the magnetic free layer can be switched from a first direction to a second direction that is 180 degrees from the first direction. This can be accomplished, for example, by applying a current through the MTJ element in a direction that is perpendicular to the planes of the layers of the MTJ element. An electrical current applied in one direction will switch the magnetization of the free layer to a first orientation, whereas switching the direction of the current such that it is applied in a second direction will switch the magnetization of the free layer to a second, opposite orientation. Once the magnetization of the free layer has been switched by the current, the state of the MTJ element can be read by reading a voltage across the MTJ element, thereby determining whether the MTJ element is in a “1” or “0” bit state. Advantageously, once the switching electrical current has been removed, the magnetic state of the free layer will remain in the switched orientation until such time as another electrical current is applied to again switch the MTJ element. Therefore, the recorded data bit is non-volatile in that it remains intact in the absence of any electrical power.
The magnetic memory elements can be arranged in an array of memory elements that are connected with word lines and bit lines. A source-line can provide read and write currents to the memory elements, with the individual memory elements being selected by the word line and bit line. In addition to MRAM memory systems, other types of two terminal resistive switching elements can be used in a similar manner being connected with word and bit lines to both switch the memory state of the element and to read a memory state of the element.
The present invention provides a memory array that includes a semiconductor substrate having a recess formed in its surface. A selector transistor is formed on the substrate, the selector transistor including a semiconductor column extending from the recess formed in the surface of the substrate, a gate dielectric surrounding at least a portion of the semiconductor column, and an electrically conductive gate structure arranged such that the gate dielectric is between the electrically conductive gate structure and the semiconductor column. A two terminal resistive memory element is electrically connected with the semiconductor column of the selector transistor.
The semiconductor column can be formed by selective epitaxial growth on a semiconductor substrate. The selective epitaxial growth of the semiconductor column advantageously allows the semiconductor column to have a very low electrical resistance when in an “on” state so that a large amount of electrical current can be delivered to the two terminal resistive memory element. This allows for reliable switching of the memory element during data writing.
The selective epitaxial growth of the semiconductor column can be performed by first etching a notched region into the surface of a semiconductor substrate. The semiconductor substrate is etched sufficiently to remove any oxide in the region where the semiconductor column is to be formed. The etching can be performed in such a manner as to form a beveled surface in the notched region. This has been found to result in a good mono-crystalline structure in the semiconductor channel grown thereon.
These and other features and advantages of the invention will be apparent upon reading of the following detailed description of the embodiments taken in conjunction with the figures in which like reference numeral indicate like elements throughout.
For a fuller understanding of the nature and advantages of this invention, as well as the preferred mode of use, reference should be made to the following detailed description read in conjunction with the accompanying drawings which are not to scale.
The following description is of the best embodiments presently contemplated for carrying out this invention. This description is made for the purpose of illustrating the general principles of this invention and is not meant to limit the inventive concepts claimed herein.
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The magnetic reference layer 102 can be part of an anti-parallel magnetic pinning structure such as a Synthetic Anti-Ferromagnet (SAF) 112 that can include a magnetic balancing bottom layer 114, and a non-magnetic, antiparallel coupling layer (such as Ru) 116 located between the bottom SAF layer 114 and reference layer 102. The antiparallel coupling layer 116, which will be described in greater detail herein below, can be constructed to have a composition and thickness such that it will couple the layers 114, 102 in an antiparallel configuration. The antiparallel coupling between the layers 114, 102 ensures that the magnetization 108 of the reference layer 102 is fixed in a direction opposite to the direction of magnetization 118 of the bottom SAF layer 114.
A seed layer 120 may be provided near the bottom of the memory element 100 to initiate a desired crystalline structure in the above deposited layers. A capping layer 121 may be provided near the top of the memory element 100 to protect the underlying layers during manufacture, such as during high temperature annealing and from exposure to ambient atmosphere. The capping layer 121 can be constructed of, for example, Ta.
In addition, electrodes 124, 126 may be provided at the bottom and top of the memory element 100. The electrodes 124, 126 may be constructed of a non-magnetic, electrically conductive material such as one or more of Ta, W, Cu and Al and can provide electrical connection a bit line 128 and a word line 130 for reading and writing data to the memory element 100.
The magnetic free layer 104 has a perpendicular magnetic anisotropy that causes the magnetization 110 of the free layer 104 to remain stable in one of two directions perpendicular to the plane of the free layer 104. In a write mode, the orientation of the magnetization 110 of the free layer 104 can be switched between these two directions by applying an electrical current through the memory element 100 from the circuitry 128. A current in one direction will cause the memory element to flip to a first orientation, and a current in an opposite direction will cause the magnetization to flip to a second, opposite direction. For example, if the magnetization 110 is initially oriented in a downward direction in
On the other hand, if the magnetization 110 of the free layer 104 is initially in an upward direction in
The magnetic memory element 100 can be electrically connected with a bit line 128 at one end and a word line 130 at the opposite end. An electrical current from the word and bit lines 128, 130 can be used to switch the memory state of the memory element 100 as described above, and can also be used to read an electrical resistance of the memory element during a read operation to determine whether the memory element 100 is in a high resistance state or a low resistance state (i.e. 0 or 1).
The two terminal resistive memory element can be connected at one end to an electrically conductive bit line 204. The other end of the two terminal resistive memory element 202 can be connected with a selector 206. The selector 206 can be in the form of a vertical semiconductor transistor structure which will be described in greater detail herein below. The selector 206 is connected with a source line 210, which provides a source-line voltage to the selector 206. A word-line 208 is electrically connected with the selector 206 in such a manner as to supply a gate voltage to the selector 206. When the word-line 208 applies a voltage to the selector 206, the selector becomes conductive, allowing a current to flow from the source-line 210 to the memory element 202. When voltage at the word-line 208 is removed, the selector 206 becomes insulating, thereby preventing the flow of current between the source-line 210 and the memory element 202.
Memory systems employing two terminal resistive memory elements such as MTJ memory elements exhibit fundamentally different performance characteristics from more traditional memory systems that employ transistors as memory elements, such as in NAND architectures. In such more traditional transistor-based memory systems, the storage of electrical charge in a location between the transistor's gate and its channel changes the transistor's threshold voltage. The difference between a programmed and erased cell is sensed by measuring the transistor's source-drain current. Programming is done with high voltages but small currents. To get a large window between programmed and erased states, more charge can be stored but this is usually at the expense of other factors such as endurance and retention.
Memory systems based on two terminal memory elements such as MTJ elements, however, function in a fundamentally different manner. The memory element is either in a high resistance state or low resistance state, and the electrical resistance of the memory element is dictated by the magnetic orientations of the magnetizations of the magnetic layers in the memory element. As described above, this memory state is switched (written) by supplying an electrical current through the memory element 202 (e.g. between the source-line 210 and the bit line 204. The higher the current through the memory element 202 the higher the probability is that the memory state of the memory element 202 will be switched as desired. Therefore, increasing this current increases the accuracy of writing by increasing the number of memory elements that will be correctly switched. Ideally, 100% of the memory elements will be switched as desired, and to reach or come close to this performance, ideal an increased electrical current between the source-line 210 and bit-line 204 is desired.
Accurately switching the memory state of the memory element 202 requires that a large electrical current be able to flow through the selector 206 to the memory element 202 when the selector is in an “on” state. This requirement for high current at low voltage shows a fundamental difference between such a system and the more traditional transistor-based systems such as NAND Flash where high voltages and low currents are used to store electrical charge. In a memory system such as that described above, the selector 206 requires high current flow in an “on” state to reliably switch the memory state 202 when desired. This need for increased current flow through the selector 206, therefore, requires a fundamentally different design and structure than with transistor based memory systems. As a result, the formation of such a high current selector transistor fabricated in a manufacturable process has not been previously contemplated by those skilled in the art of memory arrays.
The semiconductor column 302 has a diameter DS and the gate dielectric 304 has a thickness TGD. Increasing the diameter DS of the semiconductor column effectively increases the amount of current that can flow through the semiconductor column in an “on” state. Therefore, to provide an effective conduction of current through the selector 202 to drive the memory element 202 (
Another way to increase current flow through the semiconductor column 302 in an “on” state is by carefully controlling the material of which the semiconductor column 302 is constructed. Pure monocrystalline semiconductor has a much higher effective conduction as compared with other structures such as amorphous or polycrystalline semiconductor. To that end, the semiconductor column preferably has a structure that is as close to monocrystalline as possible, although some inclusions or disruptions in the crystalline structure may inevitably occur in the semiconductor column 320. While forming the semiconductor column 302 as a 100% pure monocrystalline structure may not be practical, it is desirable that the semiconductor 302 be as close to pure monocrystalline as possible. For example, the semiconductor column is preferably at least 80 percent monocrystalline by volume, or more preferably at least 90 percent monocrystalline by volume. A novel process for forming such a highly monocrystalline semiconductor column 302 is described herein below.
The memory element 202 can be formed over the selector structure 206, and can be electrically connected with an end of the semiconductor column 302 by a bottom electrode 418. A top electrode 420 can be formed at the opposite (top) end of the memory element 202 to connect the memory element 202 with the bit line 204. The area surrounding the sides of the memory element can be filled with a dielectric isolation layer 422, which can be an oxide such as silicon oxide or some other suitable material.
The semiconductor pillar structure 302 can be formed on a substrate 408. The substrate 408 can include a substrate base 410 formed of a semiconductor material such as Si or silicon on insulator. A doped region 412 can be formed at the top of the substrate base. The doped region 412 can provide a source line connected with source-line circuitry 210, which will be described in greater detail herein below. It should be pointed out that the doped portion 412, which forms a portion of the source-line, can be formed as a line in the substrate, or could be formed as a source-plane in two dimensions for providing a source line voltage to multiple rows and columns of memory cells.
As discussed above it is desirable that the selector structure 206 be configured to provide a high current flow to the memory element when in a low resistance “on” mode (e.g. when a gate voltage is applied by the gate line 404). Therefore, the dimensions and material composition of the semiconductor column and gate dielectric are preferably configured to maximize this current flow. To this end, the semiconductor column 302 such as shown in
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The two terminal resistive memory element 1902 can be electrically connected with the semiconductor column 1602 by an electrically conductive bottom electrode 1904. The electrically conductive bottom electrode 1904 can be constructed of a material such as Ta or some other electrically conductive metal. Other electrically conductive structures such as electrically conductive vias (not shown) may also be included to provide electrical connection between the two terminal memory element 1902 and the semiconductor column 1602, such as between the bottom electrode 1904 and the semiconductor column 1602. An upper electrode 1908 can be electrically connected with the two terminal resistive memory element 1902 at the end opposite the bottom electrode 1904. The upper electrode 1908 can provide electrical connection between the two terminal resistive memory element 1902 and the bit line 128 previously described.
While various embodiments have been described above, it should be understood that they have been presented by way of example only and not limitation. Other embodiments falling within the scope of the invention may also become apparent to those skilled in the art. Thus, the breadth and scope of the inventions should not be limited by any of the above-described exemplary embodiments but should be defined only in accordance with the following claims and their equivalents.
The present invention is a Continuation in part of commonly assigned U.S. patent application Ser. No. 16/237,143 entitled “METHODS OF FORMING PERPENDICULAR MAGNETIC TUNNEL JUNCTION MEMORY CELLS HAVING VERTICAL CHANNELS,” filed Dec. 31, 2018, which in turn is a Continuation in part of, and claims priority to, U.S. patent application Ser. No. 15/857,387, filed Dec. 28, 2018, entitled “METHODS OF FORMING PERPENDICULAR MAGNETIC TUNNEL JUNCTION MEMORY CELLS HAVING VERTICAL CHANNELS,” now U.S. Pat. No. 10,468,293.
Number | Date | Country | |
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Parent | 16237143 | Dec 2018 | US |
Child | 16719790 | US | |
Parent | 15857387 | Dec 2017 | US |
Child | 16237143 | US |