MEMORY INTERFACE TO BRIDGE MEMORY BUSES

Abstract

A memory interface to bridge a parallel memory bus and a serial memory bus. One embodiment includes a printed circuit board, comprising: at least one memory interface buffer chip to connect an advanced memory buffer (AMB) interface and one or more non-fully buffered memory modules.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements.

FIG. 1 shows a computer using a memory system according to one embodiment of the invention.

FIG. 2 shows a block diagram of a memory interface buffer according to one embodiment of the invention.

FIG. 3 shows a memory system architecture according to one embodiment of the invention.

FIG. 4 shows a converter which can be used in a memory interface buffer according to one embodiment of the invention.

FIG. 5 shows a block diagram example of a transceiver which can be used in a memory interface buffer according to one embodiment of the invention.

FIGS. 6-9 illustrate examples of a pseudo differential digital logic circuit which can be used in transceivers of memory interface buffers according to embodiments of the invention.

FIGS. 10-11 illustrate examples of printed circuit boards according to embodiments of the invention.

FIG. 12 shows a computer using a memory system according to another embodiment of the invention.

FIGS. 13-14 show block diagrams of memory interface buffers according to embodiments of the invention.

FIG. 15 shows a memory system architecture according to another embodiment of the invention.

FIG. 16 illustrates an example of a printed circuit board according to one embodiment of the invention.

FIG. 17 shows a memory system architecture according to further embodiment of the invention.

Claims

1. A printed circuit board, comprising: at least one memory interface buffer chip to connect an advanced memory buffer (AMB) interface and one or more non-fully buffered memory modules.

2. The printed circuit board of claim 1, further comprising: a plurality of memory sockets configured to accept the one or more non-fully buffered memory modules;a chipset comprising a memory controller with the advanced memory buffer (AMB) interface; anda central processing unit (CPU) socket coupled to the chipset to accept a microprocessor chip.

3. The printed circuit board of claim 1, further comprising: a memory bus to connect the plurality of memory sockets.

4. The printed circuit board of claim 1, wherein the memory bus comprises a Double Date Rate (DDR) memory bus.

5. A computer system, comprising: a microprocessor chip;a core logic chip coupled to the microprocessor chip, the core logic chip comprising a memory controller with an advanced memory buffer (AMB) interface;one or more non-fully buffered dual in-line memory modules; anda memory interface buffer chip coupled between the advanced memory buffer (AMB) interface and the one or more non-fully buffered dual in-line memory modules.

6. The computer system of claim 5, wherein the one or more non-fully buffered memory modules are accessed via a parallel memory bus.

7. The computer system of claim 6, further comprising: one or more fully buffered dual in-line memory modules coupled to the memory interface buffer chip.

8. The computer system of claim 7, wherein the one or more fully buffered dual in-line memory modules is coupled between the memory interface buffer chip and the advanced memory buffer (AMB) interface.

9. A circuit, comprising: a transceiver to bridge a parallel memory bus and a serial memory bus; anda protocol converter coupled to the transceiver to translate control signals received from a memory controller of the serial memory bus to control signals for the parallel memory bus.

10. The circuit of claim 9, wherein the serial memory bus is in accordance with a Joint Electron Device Engineering Council (JEDEC) Advanced Memory Buffer (AMB) specification.

11. The circuit of claim 9, wherein the circuit is implemented on a single integrated circuit chip.

12. The circuit of claim 9, wherein the serial memory bus is connected to an Advanced Memory Buffer (AMB) interface of a memory controller.

13. The circuit of claim 12, wherein the parallel memory bus is a double data rate (DDR) memory bus on a motherboard.

14. The circuit of claim 9, wherein the serial memory bus is connected to an Advanced Memory Buffer (AMB) of a fully buffered memory module.

15. The circuit of claim 9, wherein the transceiver comprises: a pseudo differential digital logic circuit to convert an input to the transceiver into a differential digital output.

16. The circuit of claim 15, wherein the pseudo differential digital logic circuit is implemented using Complementary Metal-Oxide Semiconductor (CMOS).

17. The circuit of claim 16, further comprising: an adaptive power-supply regulator coupled with the pseudo differential digital logic circuit to adaptively adjust a power supply of the pseudo differential digital logic circuit.

18. The circuit of claim 16, wherein the pseudo differential digital logic circuit comprises: two logic units each of which is one of: a buffer and an inverter; anda common mode feedback (CMFB) circuit coupled to the two logic units, the CMFB circuit to receive outputs of the two logic units and adjust the two logic units according to a common mode detected from the outputs of the two logic units to suppress command mode.

19. The circuit of claim 16, wherein the pseudo differential digital logic circuit comprises: two logic units each of which is one of: a buffer and an inverter; anda cross couple circuit coupled to the two logic units, the cross couple circuit to cross couple outputs of the two logic units to suppress command mode in the outputs of the two logic units.

20. The circuit of claim 16, wherein the pseudo differential digital logic circuit comprises: two logic units each of which is one of: a buffer and an inverter; anda clock synchronization circuit coupled to the two logic units to synchronize timing of outputs of the two logic units.