Patent Application
20210328077
The present invention relates to a power diode structure, and more particularly to a merged PiN junction Schottky (MPS) diode with enhanced reliability under a surge current.
Power devices include power diodes and power switching transistors. Power diodes have two modes of operation in circuit applications, which are conduction mode and blocking mode. For the conduction mode, in addition to nominal current conditions, there is an occasional surge current condition. Under the abnormal conditions with surge current, the diode may have instant energy overshoot and chip temperature rise, resulting in device failure.
Power devices are expected to endure high current stresses under surges caused by circuit failure or lightening. Usually a great amount of energy, caused by high current multiplied by high voltage drop, flows into the device in quite a short time, leading to rapidly raised temperature and possibly a device failure. Surge capability is a key performance index which describes the robustness of power devices under extreme operating conditions. Devices with preeminent surge capability can dissipate such energy efficiently without a failure, thus offering a higher safety margin to the power system.
Silicon carbide semiconductor has two times larger bandgap compared with Silicon semiconductor. With a higher critical electric field, higher thermal conductivity, lower intrinsic carrier concentration, and higher saturation drift velocity, silicon carbide semiconductor has become an ideal candidate for high voltage, high temperature and high-power devices.
There are two technical routes for commercial devices based on silicon carbide power diodes, namely junction barrier Schottky (JBS) diode structure and merged PiN Schottky (MPS) diode structure.
For silicon carbide (SiC) materials, the Junction Barrier Schottky (JBS) diode is widely used. Armed with excellent characteristics of SiC material and characterized by alternatively arranged small P+ regions in N-drift layer, it has received large attention for its low forward voltage drop and low reverse leakage current. Merged PiN Schottky (MPS) diode was proposed based on the JBS diode structure, with merged large P+ regions into the active region. PN junctions formed by these large P+ regions will turn on under high current flows. Large amount of minority carriers will be injected into the drift layer, providing a lower resistivity and a higher current conduction capability. Thus, it offers higher surge capability compared to traditional JBS diode, as well as preserving a low forward voltage drop and reverse leakage current at the same time.
In one aspect, a merged PiN Schottky (MPS) diode may include a silicon carbide substrate having a first conductivity type, an epitaxial layer with the first conductivity type formed on the substrate, In one embodiment, the doping concentration in the epitaxial layer is lower than that in the substrate. The merged PiN Schottky (MPS) diode may further include a plurality of regions having a second conductivity type different from the first conductivity type, and formed under a top surface of the epitaxial layer.
A first Ohmic contact metal is formed on top of each of the regions of the second conductivity type, and a Schottky contact metal is placed on top of the entire epitaxial layer to form a Schottky junction. A second Ohmic contact is formed by a cathode electrode on the back side of the substrate.
In one embodiment, the first conductivity is N type, and the second conductivity type is P type. It is noted that in the merged PiN Schottky (MPS) diode structure, a PN junction can be formed by a P+ region, and a N-type drift region can be turned on under surge current condition, forming a parallel operation mode between the PN junction and the Schottky junction, providing device with better surge current capability.
In a merged PiN Schottky (MPS) diode, the PN junction formed by the P+ region and the N-type drift region can be turned on under surge current condition, forming a parallel operation mode between the PN junction and the Schottky junction, providing device with better surge current capability. The shape, size and arrangement of the P+ region largely affect the electrical characteristics of the merged PiN Schottky (MPS) diode in the event of a high current surge. Therefore, it is important to study the relationship between the structure parameter design of the P+ region and the device surge current capability. With the reasonable design of the width and spacing of P+ region, the turn-on voltage of the PN junction can be reduced, resulting in the lower power loss and temperature rise under the current surge, therefore improving the device surge current capability.
The design of the P+ region not only affects the surge current capability of the device, but also affects the forward voltage drop of the device under the nominal current operation, thereby influencing the conducting performance of the device. Under a nominal current condition, in which current is less than the value of the maximum steady-state operating current given in the product data sheet, because the Schottky barrier height is much lower than the PN junction built-in potential, only the Schottky junction is turned on. If the P+ region is designed with larger size and takes up too much active area, the remaining Schottky junction area will be reduced, the forward voltage drop under the nominal current conduction will increase, resulting in less competitive conducting performance. On the other hand, when the device is subjected to an abnormal surge current shock, the wider P+ region (larger P+ region area) can lower the turn-on voltage of the PN junction. Once the PN junction begins to conduct current, a large amount of minority carriers will be injected into the drift layer to reduce the electrical resistance and device voltage drop. As a result, the capability of device withstanding surge current can be enhanced.
The present invention proceeds from the method of device structure design, aiming to find the optimal solution between the normal current conduction performance and the surge current capability of merged PiN Schottky (MPS) diode.
In another aspect, a method for manufacturing a merged PiN Schottky (MPS) diode may include steps of providing a substrate having a first conductivity type; forming an epitaxial layer with the first conductivity type on top of the substrate; forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer; forming a plasma spreading layer in each region; depositing and patterning an Ohmic contact metal on the regions with the second conductivity type; depositing a Schottky contact metal on top of the entire epitaxial layer; and forming an Ohmic contact metal on a backside of the substrate.
In one embodiment, the epitaxial layer is made of N-type silicon carbide. In another embodiment, the step of forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer may include steps of depositing and patterning a mask layer on the epitaxial layer, implanting P-type dopant into the epitaxial layer, and removing the mask layer. It is noted that the dopant can be aluminum or boron.
In a further embodiment, the step of depositing and patterning an Ohmic contact metal on the regions may include a step of annealing the Ohmic metal to enable the metal to be in direct contact with the epitaxial layer. In still a further embodiment, the step of depositing a Schottky contact metal on top of the entire epitaxial layer may include a step of conducting a low temperature annealing of the Schottky contact metal.
The detailed description set forth below is intended as a description of the presently exemplary device provided in accordance with aspects of the present invention and is not intended to represent the only forms in which the present invention may be prepared or utilized. It is to be understood, rather, that the same or equivalent functions and components may be accomplished by different embodiments that are also intended to be encompassed within the spirit and scope of the invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood to one of ordinary skill in the art to which this invention belongs. Although any methods, devices and materials similar or equivalent to those described can be used in the practice or testing of the invention, the exemplary methods, devices and materials are now described.
All publications mentioned are incorporated by reference for the purpose of describing and disclosing, for example, the designs and methodologies that are described in the publications that might be used in connection with the presently described invention. The publications listed or discussed above, below and throughout the text are provided solely for their disclosure prior to the filing date of the present application. Nothing herein is to be construed as an admission that the inventors are not entitled to antedate such disclosure by virtue of prior invention.
As used in the description herein and throughout the claims that follow, the meaning of “a”, “an”, and “the” includes reference to the plural unless the context clearly dictates otherwise. Also, as used in the description herein and throughout the claims that follow, the terms “comprise or comprising”, “include or including”, “have or having”, “contain or containing” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. As used in the description herein and throughout the claims that follow, the meaning of “in” includes “in” and “on” unless the context clearly dictates otherwise.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
In one aspect as shown in
A first Ohmic contact metal 18 is formed on top of each of the regions of the second conductivity type, and a Schottky contact metal 19 is placed on top of the entire epitaxial layer 13 to form a Schottky junction 16. A second Ohmic contact 17 is formed by a cathode electrode 11 on the back side of the substrate 12.
In one embodiment, the first conductivity is N type, and the second conductivity type is P type. It is noted that in the merged PiN Schottky (MPS) diode structure, a PN junction can be formed by a P+ region 14, and a N-type drift region 15 can be turned on under surge current condition, forming a parallel operation mode between the PN junction and the Schottky junction 16, providing device with better surge current capability.
It is noted that the layout design of the merged PiN Schottky (MPS) diode 10 can be strip cell structure, circle cell structure or polygon cell structure. The one-dimensional strip structure has the drawback that the P+ region occupies too much active area, resulting in insufficient Schottky area for normal current operation, leading to a large forward voltage drop of the device. However, two-dimensional circles will also leads to a large P+ percentage because circular cells cannot form a close-packed layout. Therefore, compared with regular polygon cell structure, the device will also have larger forward voltage drop due to inadequate Schottky area under normal current operation.
When the MPS diode is under forward bias, the current flows from the anode of the diode through the Schottky junction 16 into the drift region 15, then through the substrate layer 12 and flows out of the cathode electrode 11. Before the current enters the drift region 15, it first passes through the channel region formed between the second conductivity type regions. Meanwhile, the current will form a potential difference on the PN junction, which is formed between the region 14 with second conductivity type and the drift region 15 with first conductivity type. When this potential difference exceeds the built-in potential of the PN junction, the PN junction will be turned on. Changing the width of the second conductivity type region 14 will affect the threshold that triggers the turn-on of the PN junction. Once the PN junction is turned on, the voltage drop between the anode and cathode 11 of the diode is referred to as the PN junction turn-on voltage. The larger the width of the region of the second conductivity type 14, the lower the PN junction turn-on voltage. This is because, as shown in
It can be clearly seen from
As such, based on the layout design shown in
The layout designs of
Through calculation, it is found that compared with regular polygons, P+ regions in circle cell design takes too much active area during the arrangement so the Schottky area ratio is only 50.49%. Thus, an octagon cell structure is proposed here for efficient layout design. It is important to note that in order to achieve close-packed arrangement, a square cell is used to fill the gap between the octagonal cells which is shown in
On the basis of the device design shown in
Through different arrangements of the octagonal cells in shown
In another aspect, as shown in
In one embodiment, the epitaxial layer is made of N-type silicon carbide. In another embodiment, the step of forming a plurality of regions with a second conductivity type under a top surface of the epitaxial layer 230 may include steps of depositing and patterning a mask layer 20 on the epitaxial layer 2301, implanting P-type dopant into the epitaxial layer 2302, and removing the mask layer 2303. It is noted that the dopant can be aluminum or boron.
In a further embodiment, the step of depositing and patterning an Ohmic contact metal on the regions 240 may include a step of annealing the Ohmic metal to enable the metal to be in direct contact with the epitaxial layer. In still a further embodiment, the step of depositing a Schottky contact metal on top of the entire epitaxial layer 250 may include a step of conducting a low temperature annealing of the Schottky contact metal.
Having described the invention by the description and illustrations above, it should be understood that these are exemplary of the invention and are not to be considered as limiting. Accordingly, the invention is not to be considered as limited by the foregoing description, but includes any equivalent.
This application claims priority under 35 U.S.C. § 119 (e) to U.S. Provisional Patent Application Ser. No. 63/012,893, filed on Apr. 20, 2020, the entire contents of which are hereby incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| 63012893 | Apr 2020 | US |
