Patent Application
20070241427
Prior to description of specific embodiments, advantageous effects of various elements of the present invention are outlined below using
Acceptor density distribution in a depth direction of the base layer 3 is shown in
In
In the meantime, since increasing L2 becomes disadvantageous for miniaturizing the transistor, L2 has its upper limit set to 9 μm, three times the diffusion length, as a distance at which the number of electrons in the base layer 3 becomes almost zero. Thus, miniaturizing a bipolar transistor and obtaining a current gain high enough for practical use can both be achieved at the same time, even for the bipolar transistor having the first and second mesa structures.
Next, another embodiment of the present invention is described as an example below using
In the present example, a base layer region is made of the first p-type base layer 14 having an acceptor of uniform density, and the second p-type base layer 15 having an acceptor whose density is higher than the uniform acceptor density of the first p-type base layer and whose density has a gradient in a depth direction of the second p-type base layer. Thus, the concise construction shown as an example in
Next, specific examples of mesa-type bipolar transistors of the present invention, together with respective manufacturing processes, will be described with reference to the accompanying drawings.
An npn-type SiC bipolar transistor according to a first embodiment of the present invention, and an associated manufacturing process are described below using
In this transistor construction, Al acceptor density in the base layer 3 is as mentioned below. That is to say, the Al acceptor density at an edge of the emitter layer 4 is 3×1018 cm−3, and the Al acceptor density at an edge of the collector layer 2 is 8×1016 cm−3. In terms of acceptor density distribution in a depth direction of the base layer 3, as shown in
Application of the built-in field in the base layer 4 can be continued for complete suppression of lateral electron diffusion. However, the acceptor density at the edge of the collector layer 2, in the base layer 4, is reduced to the same level as or below the donor density in the collector layer 2, and thus a base-collector breakdown voltage is reduced since this voltage is determined by the punch-through due to a deletion layer extending within the base layer. In the present embodiment, therefore, since the gradient of the acceptor density in the baser layer 4 is changed, the acceptor density at the edge of the collector layer 2, in the base layer 4, is maintained at a high level to prevent the breakdown voltage from deteriorating due to the punch-through of the base layer, even when an inverse bias is applied to the base-collector junction.
Hereunder, examples of manufacturing process steps for the npn-type SiC bipolar transistor shown in
First, as shown in
Next, an SiO2 film 9 is deposited, then after photolithography and SiO2 dry etching, a photoresist is removed to form an SiO2 pattern, and first mesa processing is executed for portions of both the n-type SiC emitter layer 4 and the p-type SiC base layer 3 by dry etching via the SiO2 pattern. The transistor construction in up to this phase is shown in
The above is followed by, as shown in
After that, the SiO2 pattern is removed using hydrofluoric acid, and then annealing is performed at a temperature of 1,500° C. to activate the acceptor within the base contact region 13. After this, a SiO2 film 9 is deposited and after photolithography and SiO2 dry etching, a photoresist is removed to form a SiO2 pattern. Second mesa processing is next executed for both a remainder of the base layer 3 and portions of the collector layer 2 by dry etching. The SiO2 pattern is removed using hydrofluoric acid, and after a SiO2 film 9 has been deposited once again, a collector electrode 8 is deposited on the reverse side of the SiC substrate 1. The transistor construction in up to this phase is shown in
The SiC substrate 1 (sample) is unloaded from the electrode metal evaporator and then is subjected to photolithography and SiO2 dry etching to hole the SiO2 section on the surface of the emitter layer 4. After this, an emitter electrode 6 is formed by deposition and lift-off. The transistor construction in up to this phase is shown in
Next, a SiO2 film 9 is deposited, then after photolithography and SiO2 dry etching, a base electrode 7 is formed on the base contact region 13 by deposition and lift-off, and the emitter electrode 6, the base electrode 7, and the collector electrode 8 are each alloyed at 1,000° C. simultaneously. The transistor construction in up to this phase is shown in
Finally, a SiO2 film 9 is deposited and then photolithography and SiO2 dry etching are used to remove a photoresist from necessary sections. After this, Al electrical interconnections 10, 10′, 10″ are deposited and then photolithography and Al dry etching are conducted to complete wiring. In this way, the mesa-type bipolar transistor shown in
The present embodiment yields an advantageous effect in that a high-temperature adaptable SiC mesa-type npn bipolar transistor capable of achieving miniaturization and a current gain high enough for practical use can be realized using the built-in field that the acceptor density gradient is created in the base layer 3.
Another npn-type SiC bipolar transistor according to a second embodiment of the present invention, and an associated manufacturing process are described below using
A longitudinal sectional structural view of the npn-type SiC bipolar transistor according to the second embodiment of the present invention, is essentially the same as in
In this transistor construction, Al acceptor density in the base layer 3 is essentially the same as in the first embodiment. That is to say, the Al acceptor density at an edge of the emitter layer 4 is 3×1018 cm−3, and the Al acceptor density at an edge of the collector layer 2 is 8×1016 cm−3. In terms of acceptor density distribution in a depth direction of the base layer 3, as shown in
Application of the built-in field in the base layer 3 can be continued for complete suppression of lateral electron diffusion. However, the acceptor density at the edge of the collector layer 2, in the base layer 3, is reduced to the same level as or below the donor density in the collector layer 2, and thus a base-collector breakdown voltage is reduced since this voltage is determined by punch-through due to a deletion layer extending within the base layer. In the present embodiment, therefore, since the gradient of the acceptor density in the baser layer 3 is changed, the acceptor density at the edge of the collector layer 2, in the base layer 3, is maintained at a high level to prevent the breakdown voltage from deteriorating due to the punch-through of the base layer, even when an inverse bias is applied to the base-collector junction.
Additionally, even when the above acceptor density distribution is adopted, increasing the shortest distance L2 between lateral sides of the first mesa structure 11 and the second mesa structure 12 to at least 3 μm is effective for avoiding the problem that electrons become diffused in a lateral-side direction of the second mesa structure 12 and then recombine to reduce a current gain of the transistor. The advantageous effect that increasing the shortest distance L2 prevents the occurrence of the above problem also applies, even if the electrons that have been injected from the emitter layer 4 into the base layer 3 and accelerated by the built-in field move close to the collector layer 2 in which the built-in field decreases in strength. Provided that L2 is at least 3 μm, the above effect can be sufficiently obtained, but there is a trade-off between this effect and the transistor size. In consideration of a maximum permissible saturation level of this effect, therefore, it is appropriate to limit L2 to a maximum of 9 μm.
Description of the manufacturing process for the npn-type SiC bipolar transistor of the present embodiment is omitted since the process is the same as for the first embodiment.
The present embodiment yields an advantageous effect in that a high-temperature adaptable SiC mesa-type npn bipolar transistor capable of achieving miniaturization and a current gain high enough for practical use can be realized using the built-in field that the acceptor density gradient is created in the base layer 3.
An npn-type GaN bipolar transistor according to a third embodiment of the present invention, and an associated manufacturing process are described below using
A longitudinal sectional structural view of this npn-type GaN bipolar transistor according to the third embodiment of the present invention is essentially the same as in
In this transistor construction, Mg acceptor density in the base layer 3 is as mentioned below. That is to say, the Mg acceptor density at an edge of the emitter layer 4 is 3×1018 cm−3, and the Mg acceptor density at an edge of the collector layer 2 is 8×1016 cm−3. In terms of acceptor density distribution in a depth direction of the base layer 3, as shown in
Application of the built-in field in the base layer 3 can be continued for complete suppression of lateral electron diffusion. However, the acceptor density at the edge of the collector layer 2, in the base layer 3, is reduced to the same level as or below the donor density in the collector layer 2, and thus a base-collector breakdown voltage is reduced since this voltage is determined by punch-through due to a deletion layer extending within the base layer. In the present embodiment, therefore, since the gradient of the acceptor density in the baser layer 3 is changed, the acceptor density at the edge of the collector layer 2, in the base layer 3, is maintained at a high level to prevent the breakdown voltage from deteriorating due to the punch-through of the base layer, even when an inverse bias is applied to the base-collector junction.
Hereunder, examples of manufacturing process steps for the npn-type GaN bipolar transistor shown in
First, as shown in
Next, an SiO2 film 9 is deposited, then after photolithography and SiO2 dry etching, a photoresist is removed to form an SiO2 pattern, and first mesa processing is executed for portions of both the n-type GaN emitter layer 4 and the p-type GaN base layer 3 by dry etching via the SiO2 pattern. The transistor construction in up to this phase is shown in
The above is followed by, as shown in
After that, the SiO2 pattern is removed using hydrofluoric acid, and then annealing is performed at a temperature of 1,500° C. to activate the acceptor within the base contact region 13. After this, a SiO2 film 9 is deposited and after photolithography and SiO2 dry etching, a photoresist is removed to form a SiO2 pattern. Second mesa processing is next executed for both a remainder of the base layer 3 and portions of the collector layer 2 by dry etching. The SiO2 pattern is removed using hydrofluoric acid, and after a SiO2 film 9 has been deposited once again, a collector electrode is deposited on the reverse side of the GaN substrate 1. The transistor construction in up to this phase is shown in
The GaN substrate 1 (sample) is unloaded from the electrode metal evaporator and then is subjected to photolithography and SiO2 dry etching to hole the SiO2 section on the surface of the emitter layer 4. After this, an emitter electrode 6 is formed by deposition and lift-off. The transistor construction in up to this phase is shown in
Next, a SiO2 film 9 is deposited, then after photolithography and SiO2 dry etching, a base electrode 7 is formed on the base contact region 13 by deposition and lift-off, and the emitter electrode 6, the base electrode 7, and the collector electrode 8 are each alloyed at 1,000° C. simultaneously. The transistor construction in up to this phase is shown in
Finally, a SiO2 film 9 is deposited and then photolithography and SiO2 dry etching are used to remove a photoresist from necessary sections. After this, Al electrical interconnections are deposited and then photolithography and Al dry etching are conducted. In this way, the mesa-type bipolar transistor shown in
The present embodiment yields an advantageous effect in that a high-temperature adaptable GaN mesa-type npn bipolar transistor capable of achieving miniaturization and a current gain high enough for practical use can be realized using the built-in field that the acceptor density gradient is created in the base layer 3.
Another npn-type GaN bipolar transistor according to a fourth embodiment of the present invention, and an associated manufacturing process are described below using
A longitudinal sectional structural view of this npn-type GaN bipolar transistor according to the third embodiment of the present invention, is essentially the same as in
Application of the built-in field in the base layer 4 can be continued for complete suppression of lateral electron diffusion. However, the acceptor density at the edge of the collector layer 2, in the base layer 3, is reduced to the same level as or below the donor density in the collector layer 2, and thus a base-collector breakdown voltage is reduced since this voltage is determined by punch-through due to a deletion layer extending within the base layer. In the present embodiment, therefore, since the gradient of the acceptor density in the baser layer 4 is changed, the acceptor density at the edge of the collector layer 2, in the base layer 3, is maintained at a high level to prevent the breakdown voltage from deteriorating due to the punch-through of the base layer, even when an inverse bias is applied to the base-collector section.
Additionally, even when the above acceptor density distribution is adopted, increasing the shortest distance L2 between lateral sides of the first mesa structure 11 and the second mesa structure 12 to at least 3 μm is effective for avoiding the problem that electrons become diffused in a lateral-side direction of the second mesa structure 12 and then recombine to reduce a current gain of the transistor. The advantageous effect that increasing the shortest distance L2 prevents the occurrence of the above problem also applies, even if the electrons that have been injected from the emitter layer 4 into the base layer 3 and accelerated by the built-in field move close to the collector layer 2 in which the built-in field decreases in strength. Provided that L2 is at least 3 μm, the above effect can be sufficiently obtained, but there is a trade-off between this effect and the transistor size. In consideration of a maximum permissible saturation level of this effect, therefore, it is appropriate to limit L2 to a maximum of 9 μm.
Description of the manufacturing process for the npn-type bipolar transistor of the present embodiment is omitted since the process is the same as for the first embodiment.
The present embodiment yields an advantageous effect in that a high-temperature adaptable GaN mesa-type npn bipolar transistor capable of achieving miniaturization and a current gain high enough for practical use can be realized using the built-in field that the acceptor density gradient is created in the base layer 3.
Yet another npn-type SiC bipolar transistor that is a fifth embodiment of the present invention, and an associated manufacturing process are described below using
In this transistor construction, Al acceptor density in the first base layer 14 and that of the second base layer 15 are as shown in
Electrons that have been injected from the emitter layer 4 into the second base layer 15 are accelerated vertically towards the edge of the first base layer 14 by a strong built-in field where the acceptor density distribution is formed in the second base layer 15. Diffusion of the injected electrons in a direction of the base contact region 13 is thus reduced to an ignorable level. Consequently, all electrons injected from the emitter layer 4 into the second base layer 15 can reach the collector layer 2, with the exception of the electrons that recombine in the first base layer 14 and in the second base layer 15 existing in a transistor intrinsic region directly under the emitter layer 4. A current gain of 35 or more can there be obtained, even if L1 that has traditionally needed to be at least 3 μm is reduced below 2 μm.
Hereunder, examples of manufacturing process steps for the npn-type SiC bipolar transistor shown in
First, as shown in
Next, a SiO2 film 9 is deposited, then after photolithography and SiO2 dry etching, a photoresist is removed to form a SiO2 pattern, and first mesa processing is executed for portions of both the n-type SiC emitter layer 4 and the p-type SiC second base layer 15 by dry etching via the SiO2 pattern. The transistor construction in up to this phase is shown in
The above is followed by, as shown in
After that, the SiO2 pattern is removed using hydrofluoric acid, and then annealing is performed at a temperature of 1,500° C. to activate the acceptor within the base contact region 13. After this, a SiO2 film 9 is deposited and after photolithography and SiO2 dry etching, a photoresist is removed to form a SiO2 pattern. Second mesa processing is next executed for both a remainder of the second base layer 15 and portions of the first base layer 14 and the collector layer 2 by dry etching. The SiO2 pattern is removed using hydrofluoric acid, and after a SiO2 film 9 has been deposited once again, a collector electrode 8 is deposited on the reverse side of the SiC substrate 1. The transistor construction in up to this phase is shown in
The SiC substrate 1 (sample) is unloaded from the electrode metal evaporator and then provided with photolithography and SiO2 dry etching to hole the SiO2 section on the surface of the emitter layer 4. After this, an emitter electrode 6 is formed by deposition and lift-off. The transistor construction in up to this phase is shown in
Next, a SiO2 film 9 is deposited, then after photolithography and SiO2 dry etching, a base electrode 7 is formed on the base contact region 13 by deposition and lift-off, and the emitter electrode 6, the base electrode 7, and the collector electrode 8 are each alloyed at 1,000° C. simultaneously. The transistor construction in up to this phase is shown in
Finally, a SiO2 film 9 is deposited and then photolithography and SiO2 dry etching are conducted to remove a photoresist. After this, Al electrical interconnections are deposited and then photolithography and Al dry etching are conducted. In this way, the mesa-type bipolar transistor shown in
The present embodiment yields an advantageous effect in that a high-breakdown-voltage, high-temperature adaptable SiC mesa-type npn bipolar transistor capable of achieving miniaturization and a current gain high enough for practical use can be realized by combining the first base layer that is a high-voltage blocking layer, and then second base layer that is a built-in field layer.
Yet another npn-type GaN bipolar transistor according to a sixth embodiment of the present invention, and an associated manufacturing process are described below using
A longitudinal sectional structural view of this npn-type GaN bipolar transistor according to the sixth embodiment of the present invention, is essentially the same as in
In this transistor construction, Al acceptor density in the first base layer 14 and that of the second base layer 15 are as shown in
Electrons that have been injected from the emitter layer 4 into the second base layer 15 are accelerated vertically towards the edge of the first base layer 14 by a strong built-in field that the acceptor density distribution is formed in the second base layer 15. Diffusion of the injected electrons in a direction of the base contact region 13 is thus reduced to an ignorable level. Consequently, all electrons injected from the emitter layer 4 into the second base layer 15 can reach the collector layer 2, with the exception of the electrons that recombine in the first base layer 14 and in the second base layer 15 existing in a transistor intrinsic region directly under the emitter layer 4. A current gain of at least 35 can there be obtained, even if L1 that has traditionally needed to be at least 3 μm is reduced to 2 μm or less.
Hereunder, examples of manufacturing process steps for the npn-type GaN bipolar transistor shown in
First, as shown in
Next, a SiO2 film 9 is deposited, then after photolithography and SiO2 dry etching, a photoresist is removed to form a SiO2 pattern, and first mesa processing is executed for portions of both the n-type GaN emitter layer 4 and the p-type GaN second base layer 15 by dry etching via the SiO2 pattern. The transistor construction in up to this phase is shown in
The above is followed by, as shown in
After that, the SiO2 pattern is removed using hydrofluoric acid, and then annealing is performed at a temperature of 1,500° C. to activate the acceptor within the base contact region 13. After this, a SiO2 film 9 is deposited and after photolithography and SiO2 dry etching, a photoresist is removed to form a SiO2 pattern. Second mesa processing is next executed for both a remainder of the second base layer 15 and portions of the first base layer 14 and the collector layer 2 by dry etching. The SiO2 pattern is removed using hydrofluoric acid, and after a SiO2 film 9 has been deposited once again, a collector electrode is deposited on the reverse side of the GaN substrate 1. The transistor construction in up to this phase is shown in
The GaN substrate 1 (sample) is unloaded from the electrode metal evaporator and then is subjected to photolithography and SiO2 dry etching to hole the SiO2 section on the surface of the emitter layer 4. After this, an emitter electrode 6 is formed by deposition and lift-off. The transistor construction in up to this phase is shown in
Next, a SiO2 film 9 is deposited, then after photolithography and SiO2 dry etching, a base electrode 7 is formed on the base contact region 13 by deposition and lift-off, and the emitter electrode 6, the base electrode 7, and the collector electrode 8 are each alloyed at 1,000° C. simultaneously. The transistor construction in up to this phase is shown in
Finally, a SiO2 film 9 is deposited and then photolithography and SiO2 dry etching are conducted to remove a photoresist. After this, Al electrical interconnections are deposited and then photolithography and Al dry etching are conducted. In this way, the mesa-type bipolar transistor shown in
The present embodiment yields an advantageous effect in that a high-breakdown-voltage, high-temperature adaptable GaN mesa-type npn bipolar transistor capable of achieving miniaturization and a current gain high enough for practical use can be realized by combining the first base layer that is a high-voltage blocking layer, and the second base layer that is a built-in field layer.
In accordance with the plan view shown in
The multi-finger type bipolar transistor according to the present embodiment is constructed by connecting a plurality of mesa-type bipolar transistors in parallel on a substrate 1, as shown in
The present embodiment yields an advantageous effect in that it is possible to realize a multi-finger-type bipolar transistor capable of achieving miniaturization simultaneously with a current gain high enough for practical use, and switching electric power, even at high temperature.
A high-temperature adaptable inverter according to an eighth embodiment of the present invention is described below using
The present embodiment yields an advantageous effect in that since multi-finger-type bipolar transistors capable of achieving miniaturization simultaneously with a current gain high enough for practical use, and switching electric power, even at high temperature, is employed, an inverter featuring a low electrical loss ratio which has heretofore been difficult to obtain at high temperatures exceeding 200° C. can be realized, even at these high temperatures.
The meanings of the reference numbers and symbols used in the accompanying drawings are shown below.
1, 101 . . . Substrate, 2, 102 . . . n-type collector layer, 3, 103 . . . p-type base layer, 4, 104 . . . n-type emitter layer, 5, 105 . . . Termination region, 6, 106 . . . Emitter electrode, 7, 107 . . . Base electrode, 8, 108 . . . Collector electrode, 9, 109 . . . Insulating film, 10, 10′, 10″, 110, 110′, 110″ . . . Electrical interconnection, 11, 111 . . . First mesa, 12, 112, . . . Second mesa, 13 . . . p-type base contact region, 14 . . . First p-type base layer, 15 . . . Second p-type base layer, 16 . . . Base pad, 16′ . . . Base electrical interconnection, 17 . . . Emitter pad, 18 . . . Cathode electrode, 19 . . . Anode electrode connection pattern, 20 . . . Collector electrode connection pattern, 21 . . . Bonding wire, 22 . . . Heat-sink fin.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2006-110755 | Apr 2006 | JP | national |
