Patent Application
20240290705
Not applicable.
A portion of this disclosure contains material which is subject to copyright protection. The copyright owner has no objection to the photocopy reproduction by anyone of the patent document or the patent disclosure in exactly the form it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. 37 C.F.R 1.71(d).
BACKGROUND OF THE INVENTIVE CONCEPT
The present inventive concept relates to metal core substrate based package interconnect systems. More particularly, but not exclusively, the present inventive concept relates to metal core substrate based package interconnect systems fabricated with various electronic, optical and other type components therein.
The high cost of advancing to the next semiconductor technology node (e.g., 5 nm) is changing the role of packaging in the electronics industry. With each new node, Moore's Law has historically fulfilled the economic and technological promises of density, speed, power, and cost scaling. However, these benefits are now slowing, and new packaging solutions are needed to maintain the pace of economic advantages previously met with silicon scaling.
Conductive through substrate vias are required for nearly all advanced packaging applications since successfully partitioning a System-on-Chip (SoC) design requires an abundance of Inputs/Outputs (I/Os). This is because SoC designs comprise millions of logic gates connected by complex networks of wires, in the form of multiple buses, complicated clock distribution networks, and control signals. Standard device I/Os impose pin-to-pin delays that degrade overall circuit performance. Moreover, using time-domain multiplexing (TDM) on standard I/Os to increase the virtual pin count by running multiple signals on each I/O imposes even greater latencies that can slow I/O speeds down by a factor of 4×-32× or more. TDM approaches also result in higher power consumption. When used to drive hundreds of package-to-package connections across PCB traces between multiple chips, standard device I/O pins carry a heavy power penalty compared to connecting logic nets on a monolithic die. These requirements all lead to a demand for vias through the substrate.
There are presently three options to achieve a feedthrough within an electronic substrate: Through Panel Vias (TPVs)—electrical conduits through printed circuit boards or organic substrates; Through Silicon Vias (TSVs)—electrically isolated copper traces through a thinned silicon wafer; and Through Glass Vias (TGVs)—metal filled holes through a glass wafer. All of the processing techniques to create conductive center pins for conductive through vias use electrodeposited copper or a conductive paste screen printing process that uses gold, silver or copper mixed with a glass powder and a polymer binder to form the conductive paste.
One issue with TPVs in printed circuit boards is the minimum resolution of wires (metal lines) and space is limited for larger features. Most printed circuit boards can pattern 4 mil (100 μm) or 3 mil (75 μm) lines and spacing and the state of the art is around 1.2 mil (30 μm), but at a very high premium price. Holes for through panel vias are limited to about 6 mils (150 μm). These large features mostly limit printed circuit boards to packaged components and do not allow for high resolution components, such as flip chip dies. Because of issues with electroplating copper to fill the large drilled holes in the printed circuit boards the TPVs are usually large barrel coated holes with an opening in the center of the via. One example of a TPV is described in U.S. Pat. No. 6,717,071 “Coaxial Via Hole and Process of Fabricating the Same.”
Besides the high cost of TSV, they also have low mechanical strength. Because the silicon interposers are thinned down to create the TSV, they are weak and subject to cracking and breaking. When a silicon interposer package is increased in size and attached to a printed circuit board the coefficient of thermal expansion (CTE) mismatch between the silicon interposer and organic substrate can cause the bonding bumps to physically crack or break. The TSV can also warp, which can prevent fabrication or assembly, leading to phenomenons such as ball grid array (BGA) non-wets.
Through glass vias (TGVs), and to a lesser extent through silicon vias (TSVs), suffer from a lack of their ability to dissipate heat. The glass substrates in TGVs are insulators, thus only allowing heat to escape out of the top of the package. The TGVs are also not flexible, thus limiting their role in certain applications.
System-on-Foil, detailed in PCT/US20/54245 “System-on-Foil Device,” included herein by reference, is a system-level advanced packaging technology designed to address the shortcomings of the current 2.5/3D packaging architecture. Within System-on-Foil and all advanced packages, there exists a substrate with multilevel wiring layers to allow surface mounted electronic components to communicate with one another.
However, an issue with using a metal substrate for HI is that larger pads and solder bumps attached to wiring layers on the metal substrate can capacitively couple to the substrate, therefore limiting the high-frequency bandwidth.
Accordingly, there is a need for circuit packages and circuit boards having substrate vias formed in System-on-Foil devices.
There is also a need for System-on-Foil devices having through substrate vias that allow power, ground, and signals to pass between electronic components inside the package and outside the package.
There is also a need for System-on-Foil devices which can pass signals, power and ground through the substrate.
There is also a need for System-on-Foil devices having a common metal shell as the substrate and one or more through via metal pins that are made from the same metal as the common metal shell.
There is also a need for System-on-Foil device structures which have isolative dielectric through vias which eliminate capacitive coupling between electronic devices disposed on opposite sides of the device structure.
There is also a need for a System-on-Foil fabrication process which removes capacitive coupling during the formation of the through metal vias (TMVs) therein.
There is also a need for System-on-Foil devices which provide lower latency.
There is also a need for System-on-Foil devices which provide increased bandwidth and data rate (GHz, Gbps).
There is also a need for System-on-Foil devices which provide lower power consumption (pJ/bit), higher routing density (#of lanes per mm/layer), and higher IO density (10/mm2).
There is also a need for System-on-Foil devices which include interconnect layers of various thickness and width to support high speed digital, low speed digital, RF, power, current density.
There is also a need for System-on-Foil devices which provide low impedance power delivery networks with a patterned metal core power/ground co-plane.
There is also a need for System-on-Foil devices which provide low substrate warpage/high young's modulus substrate.
There is also a need for System-on-Foil devices which provide quick heat removal, hence high thermal conductivity.
There is also a need for System-on-Foil devices which provide thin dielectric layers between ground and power planes for power distribution networks (PDN).
There is also a need for System-on-Foil devices which provide 50 ohm impedance tuning, which cannot be met with deposition methods
The present general inventive concept provides semiconductor substrates and/or interposer packaging having through metal vias, and methods of making the same. More particularly, but not exclusively, the present inventive concept relates to semiconductor substrates and/or interposer packaging formed of a metal material and having metal through vias surrounded by a dielectric material, and methods of making the same.
Additional features and utilities of the present general inventive concept will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the general inventive concept.
The foregoing and/or other features and utilities of the present general inventive concept may be achieved by providing a metal core substrate based package interconnect system (PIS), comprising: a metal core substrate with metal in-substrate structures patterned therein using the same metal body as the metal core substrate and a dielectric material patterned therein to isolate each of the metal in-substrate structures from the metal core substrate; and an interconnect structure bonded to each of a first surface of the metal core substrate and to a second surface of the metal core substrate, each interconnect structure including an insulation material patterned with a plurality of metal interconnect structures formed therethrough, at least one of the metal interconnect structures from one interconnect structure being electronically bonded to at least one metal in-substrate structure at the first surface of the metal core substrate and at least two metal interconnect structures from the other interconnect structure being electronically bonded to at least one metal in-substrate structure at the second surface of the metal core substrate to form at least one package interconnect component (PIC).
In an example embodiment, the at least one package interconnect component is a differential PIC.
In another example embodiment, the at least one package interconnect component is a signal array PIC.
In still another example embodiment, at least one of the package interconnect components is a multi-distribution PIC for one of a signal, power, or ground line.
In still another example embodiment, the at least one package interconnect component is an optical waveguide PIC.
In still another example embodiment, the at least one package interconnect component is an array PIC.
In still another example embodiment, the insulation material is an inorganic or organic dielectric material.
In yet another example embodiment, the metal core substrate based package interconnect system may further comprise a second metal core substrate based package interconnect system connected to the top surface thereof by bonding the interconnect structure on the top surface thereof to a back side interconnect structure of the second metal core substrate based package interconnect system such that metal interconnect structures from the metal core substrate based package interconnect system are electronically connected to interconnect structures of the second metal core substrate based package interconnect system.
In still another example embodiment, the metal core substrate based package interconnect system may further comprise a third metal core substrate based package interconnect system connected to a top surface of the second metal core substrate based package interconnect system through contacts configured to connect metal interconnect structures of the second metal core substrate based package interconnect system and metal interconnect structures of the third metal core substrate based package interconnect system.
In yet another example embodiment, the metal core substrate based package interconnect system may further comprise an electronic component attached to a top surface of the third metal core substrate based package interconnect system through contacts connected to metal interconnect structures patterned therein, wherein the electronic component receives signals through metal in-substrate structures patterned in the metal core substrate based package interconnect system, the second metal in-substrate structures patterned in the metal core substrate based package interconnect system and the third metal in-substrate structures patterned in the metal core substrate based package interconnect system.
In yet another example embodiment, the metal core substrate based package interconnect system may further comprise contacts connected to at least two exposed metal interconnect structures patterned in the interconnect structure bonded to the second surface of the metal core substrate; and a component attached to the two contacts to receive signals that pass through at least two metal in-substate structures before passing through the at least two exposed metal interconnect structures.
The foregoing and/or other features and utilities of the present general inventive concept may also be achieved by providing a metal core substrate based package interconnect system (PIS), comprising: a first metal core substrate including a metal core and metal in-substrate structures patterned therein using the same metal body as the metal core and dielectric in-substrate structures patterned therein to isolate each of the metal in-substrate structures from the metal core; and a second metal core substrate including a metal core and metal in-substrate structures patterned therein using the same metal body as the metal core and dielectric in-substrate structures patterned therein to isolate each of the metal in-substrate structures from the metal core, wherein at least part of the top surface of the second metal core substrate being bonded to at least part of the bottom surface of the first metal core substrate such that the at least one of the metal in-substrate structures of the first and second metal core substrates are aligned to form at least one single metal in-substrate structure and at least one single dielectric in-substrate structure.
In an example embodiment, the metal core substrate based package interconnect system (PIS) may further comprise a cavity formed in at least one of the top surface of the second metal core substrate and the back side surface of the first metal core substrate; and a component embedded within the cavity such that the component is electronically or optically connected to at least one of the metal in-substrate structures or dielectric in-substrate structures patterned through one of the first or second metal core substrates.
In another example embodiment, the metal core substrate based package interconnect system (PIS) may further comprise a third metal core substrate having at least part of a top surface thereof bonded to at least part of the back side surface of the second metal core substrate such that the at least one metal in-substrate structure of the third and second metal core substrates are aligned to form at least one single metal in-substrate structure and the component receives a signal through the metal in-substrate structures connected between the third and second metal core substrates.
In still another example embodiment, the metal core substrate based package interconnect system (PIS) may further comprise an interconnect structure deposited on the backside of the third metal core substrate and including at least one dielectric interconnect structure and at least one metal interconnect structure patterned therethrough and being aligned with and in contact with at least one respective in-substate dielectric structure and metal in-substrate structure of the third metal core substrate, wherein the component receives a signal through the metal in-substrate structures connected together from the second and third metal core substrates and through the at least one metal interconnect structure patterned through the interconnect structure.
In yet another example embodiment, the metal core substrate based package interconnect system (PIS) may further comprise an interconnect structure deposited on at least one of the top surface of the first metal core substrate and the backside of the second metal core substrate, the at least one interconnect structure including at least one dielectric interconnect structure and at least one metal interconnect structure patterned therethrough and being aligned with and in contact with at least one corresponding dielectric in-substrate structure and metal in-substrate structure of the metal core substrate in which the interconnect structure is deposited thereon.
In another example embodiment, the metal core substrate based package interconnect system (PIS) can further comprise contacts connected to at least two exposed metal interconnect structures patterned in an interconnect structure bonded to the top surface of the first metal core substrate; and a component attached to the two contacts to receive signals that pass through the first and second metal core substrates before passing through the at least two exposed metal interconnect structures.
Additional features and utilities of the present general inventive concept will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the general inventive concept.
These and/or other features and utilities of the present inventive concept will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
The drawings illustrate a few example embodiments of the present inventive concept and are not to be considered limiting in its scope, as the overall inventive concept may admit to other equally effective embodiments. The elements and features shown in the drawings are to scale and attempt to clearly illustrate the principles of exemplary embodiments of the present inventive concept. In the drawings, reference numerals designate like or corresponding, but not necessarily identical, elements throughout the several views.
Reference will now be made in detail to the embodiments of the present general inventive concept, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present general inventive concept while referring to the figures. Also, while describing the present general inventive concept, detailed descriptions about related well-known functions or configurations that may diminish the clarity of the points of the present general inventive concept are omitted.
Reference will now be made in detail to the embodiments of the present general inventive
It will be understood that although the terms “first” and “second” are used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element could be termed a second element, and similarly, a second element may be termed a first element without departing from the teachings of this disclosure.
Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.
All terms including descriptive or technical terms which are used herein should be construed as having meanings that are obvious to one of ordinary skill in the art. However, the terms may have different meanings according to an intention of the inventors, case precedents, or the appearance of new technologies. Also, some terms may be arbitrarily selected by the inventors, and in this case, the meaning of the selected terms will be described in detail in the detailed description herein. Thus, the terms used herein have to be defined based on the generally defined meaning of the terms together with the description throughout this specification.
Hereinafter, one or more exemplary embodiments of the present general inventive concept will be described in detail with reference to accompanying drawings.
Example embodiments of the present general inventive concept are directed to metal core substrate based package interconnect systems fabricated with various electronic, optical and other type components therein, such as, for example: through metal vias (TMVs) used, for example, to transmit signals, power, or ground through electrically isolated pins; dielectric isolation vias (DIVs) used, for example, to reduce or eliminate capacitive coupling between a component/bump and the metal substrate; power and ground planes used, for example, to route power and ground by patterning a plane within the metal substrate; passives used, for example, to fabricate components such as capacitors, resistors, inductors, and other components by using a metal core for at least a portion of each component; transmission lines used, for example, to route signal, power, and/or ground within the metal substrate to support high current densities or impedance matched interconnects; dielectric cutouts for redistribution layers (RDLs) used, for example, to provide additional dielectric thickness, beyond that within interconnect layers, for target impedance design; photonic vias and waveguides used, for example, to fabricate waveguides in metal core dielectric; heat spreader channels, used, for example, to increase convective or conductive heat dissipation by patterning a cavity in the metal substrate and leaving empty or filling with high thermal conductivity material; microfluidic channels and heat pipes, used, for example, to eliminate heat from the metal substrate by patterning a cavity in the metal substrate for microfluidic cooling; and antennas in a package formed of the same body as the metal core.
After the metal core substrate 102 is fabricated with metal in-substrate structures 102b and dielectric in-substrate structures 102c patterned therein an interconnect structure 104 can be fabricated on one or both the top and back surfaces of the metal core substrate 102. The interconnect structure(s) 104 can be formed to include different shaped dielectric interconnect and metal interconnect structures (104a, 104b) therein which can be aligned with different ones of the metal in-substrate structures 102b and dielectric in-substrate structures 102c patterned into the metal core 102a to form continuous transmission lines, and more importantly various different types of electronic, optical, liquid based, etc., circuit components within the substrate based package interconnect system 100, according to various example embodiments of the present inventive concept as described in detail below with reference to
Due to its mechanical, temperature, and chemical compatibility with semiconductor processes, the metal core substrate can be made into wafer format in order to pattern high fidelity interconnect layers using lithographic patterning processes. As a result, lines and vias within the interconnect structure can be patterned more densely and at finer resolution than possible in non-wafer patterning techniques. The higher density of interconnects allows for an overall reduction in the number of interconnect layers that are required.
Additionally, more vias can be stacked using a wafer-based interconnect patterning process than in a conventional substrate build up process. Therefore, the combination of a reduced number of interconnect layers and an increased number of stacked vias can allow for interconnects to run entirely vertically through the package, as shown in 210, 220, and 230, improving performance. This is often not possible in conventional build up substrates, which required interconnects to be ‘staggered’ left or right to another set of stacked vias before continuing down through the substrate core.
Further, by using wafer-based interconnect patterning techniques, the interconnect line roughness can be significantly reduced, compared to non-wafer processes, which increases transmission line performance.
Due to the mechanical rigidity of the metal substrate, layer balancing between the topside and the backside is not required to the same extent as it is in organic substrate package technologies.
In this example embodiment an interconnect structure 204 is deposited on both the top surface and the back side of the metal core substrate 202 such that the patterned insulation material (also referred to herein as dielectric interconnect structures) 204a and a plurality of the metal interconnect structures 204b are fabricated on the top and bottom surfaces of the metal core substrate 202 to align with the dielectric in-substrate structures 202c and the metal in-substrate structures 202b of the metal core substrate 202. More specifically, with this configuration a single ended electronic transmission line 210 is an example of a package interconnect component which can be formed to extend through the metal core substrate based package interconnect system 200. The single ended electronic transmission line 210 can launch from one contact “C” disposed at either the top or the bottom of the metal core substrate based package interconnect system 200, connect with a first interconnect structure metal 204b within a first one of the interconnect structures 204, traverse through the interconnect structure 204, connect with a coaxial through metal via (TMV) 202b, connect with a second metal interconnect structure 204b within the second interconnect structure 204, traverse through the second interconnect structure 204 and then terminate at another contact C disposed at an opposite side of the metal core substrate based package interconnect system 200.
Coaxial Through Metal Vias can be formed in the substrate and designed for impedance matching to support high frequency single ended electronic transmission lines 210. By using the substrate metal as both the inner and outer conductor, these can be formed in higher density than would be capable in other substrate technologies. This further supports an overall reduced package size and layer count, when coupled with the high density wafer-based interconnects.
Additionally, Coaxial Through Metal Vias provide more area for signal and return currents to flow, especially at high frequency, which improves insertion loss and return loss relative to non-coaxial vias like through silicon vias, through glass vias, and through package vias. Also, since coaxial through metal vias are shielded from each adjacent via by a grounded metal core, there is no crosstalk between coaxial through metal vias, unlike through silicon vias, through glass vias, and through package vias.
Further, a differential electronic transmission line 220 is another example embodiment of a package system component which can be formed to extend through the metal core substrate based package interconnect system 200. The differential electronic transmission line 220 can be configured as a combination of signal, power and/or ground lines. The differential electronic transmission line 220 can launch from one of the contacts C disposed at either the top or the bottom of the metal core substrate based package interconnect system 200, connect with an interconnect structure metal 204b formed in a first one of the interconnect structures 204, traverse through the interconnect structure 204, connect with a differential coaxial TMV 202b, traverse through the differential coaxial TMV 204b, connect with an interconnect structure metal 204b formed in the second one of the interconnect structures 204, traverse through the second interconnect structures 204 and terminate at a contact C disposed at the opposite end of the metal core substrate based package interconnect system 200.
Impedance matched differential through vias can be formed in the substrate at higher density than competing substrate technologies, as a result of using the substrate metal as both the inner and outer conductors, and thus support a higher density of differential electronic transmission lines 220. This increased density, when coupled with wafer-based interconnects, allows for an overall reduction in package size.
Further, a signal array 230 is another example embodiment of a package system component which can be formed to extend through the metal core substrate based package interconnect system 200. The signal array 230 can launch from multiple contacts C disposed at one end of the metal core substrate based package interconnect system 200, connect with an interconnect structure metal 204b, traverse through the interconnect structure 204, connect with a TMV 202b, traverse through the metal core substrate 202, connect with an interconnect structure metal 204b formed in the second one of the interconnect structures 204, traverse through the interconnect structure 204 and terminate at multiple contacts disposed at the opposite side of the metal core substrate based package interconnect system 200.
The signal array 230 can be used to maximize routing density in the metal core substrate based package interconnect system, allowing for an overall reduction in package size.
The decoupling circuit 310 reduces parasitic capacitance between an interconnect structure, such as a contact, and the metal substrate. This increases the electronic performance of the package interconnect system for metal substrates.
Further, an isolated circuit 320, including a signal, power or ground line is another example embodiment of a package system component which can be formed to extend through the metal core substrate based package interconnect system 300. The isolated circuit 320 can include a pair of metal interconnect structures 304b which extend through the first interconnect structure 304 and connect with a metal in-substrate structure 302b, and another metal interconnect structure 304b which extends from the metal in-substrate structure 302b through the second interconnect structure 304 and can have another contact disposed at an opposite end thereof. The isolated circuit 320 can launch from at least one contact C, connect with interconnect structure metal 304b, traverse through the interconnect structure 304, connect with and traverse through an in-substrate plane 302b, connect with at least one interconnect structure metal 304b in the other one of the interconnect structures 304 and traverse through the interconnect structure 304 to terminate at the at least one contact C. This isolated circuit 320 type interconnect system component can provide a multiport connection from one side of the package system to the other side thereof.
The multi-distribution signal 320, power, or ground PIC allows for routing of signal, power, or ground within the substrate itself, for instance distributing power to multiple end points. This offers a low-resistivity isolated conduction path within the substrate which would otherwise need to occur within the interconnect structure layers, and thus can reduce the package size and the number of interconnect structure layers required.
Further, substrate interconnect electronic transmission line 330 is another example embodiment of a package system component which can be formed to extend through the metal core substrate based package interconnect system 300. The substrate interconnect electronic transmission line 330 can include aa metal interconnect structure 304b which extends through the first interconnect structure 304 and connects with an in-substrate waveguide 302b formed in the metal core substrate 302, and includes another metal interconnect structure 304b which extends from the in-substrate waveguide 302b through the second interconnect structure 304. The substrate interconnect electronic transmission line 330 can launch from a contact C, connect with the interconnect structure metal 304b, traverse through the interconnect structure 304, connect with and traverse through the in-substrate waveguide 302b, connect with the other interconnect structure metal 304b in the second interconnect structure 304 and traverse through the interconnect structure 304 to terminate at another contact C.
The substrate interconnect electronics transmission line 330 allows for routing of signal within the metal substrate which would otherwise need to occur within the interconnect structure layers, and thus can reduce the package size and the number of interconnect structure layers required. Moreover, the substrate interconnect transmission line 330 can be impedance matched, based on its geometry, to support high frequency signal transmission.
With the configuration of
Alternatively, as illustrated by reference number 420, a power line can incorporate a partial isolated package interconnect component to supply a different power to the meal core 402 and instead use a ground supply from a contact C disposed at an end of a metal interconnect structure 404b formed through the second interconnect structure 402. A power line 420 allows for capacitance to be formed between the metal substrate and interconnect structures to serve as a decoupling capacitor between ground and a supplied voltage level.
Further, an Antipad 430, acting as a signal, power or ground line is another package example embodiment of a package system component which can be formed to extend through the metal core substrate based package interconnect system 300. In this example package interconnect component, the Antipad 430 can include an metal interconnect structure 404b, a metal in-substrate structure 402b, and another metal in-substrate structure 402b, wherein antipads are patterned into one or both metal core 402a surfaces/sides to reduce capacitive coupling between one or more contacts C and the metal core 402. Here the antipad launches from one contact C, connects with an metal interconnect structure 404b of one of the interconnect structures 404 and traverses through the interconnect structure 404, connects with a TMV 402b with antipads patterned into the surfaces/sides of the metal core 402a and traverses through the TMV 402b, connects with the other one of the metal in-substrate structures 402b and traverses through the other interconnect structure 404 and terminates at a contact C.
An antipad 430 serves to reduce the capacitance between the metal substrate and structures above or below the interconnect systems, such as a solder ball, bump, or microbump.
With the configuration of
Here a transmission line launches from a contact C, connects with an metal interconnect structure 504b and traverses through the interconnect structure 504, connects with a TMV 502b patterned in a metal core 502a of the metal core substrate 502, and radiates electromagnetic energy outward from the TMV 502b. This substrate antenna 510 can also be run in reverse as a receiver.
A substrate antenna 510 allows for antenna functionality within the substrate itself, which would otherwise need to be formed in the interconnect structure or attached to a surface. Embedding the antenna within the substrate itself can offer both performance and package size advantages.
Further, a substrate array 520 is another example embodiment of a package interconnect component which can be formed to extend through the metal core substrate based package interconnect system 500. In this example package interconnect component, a pair of electronic transmission lines launch from two or more contacts C connected to metal interconnect structures 504b, traverse through the interconnect structure 504, connect with and traverse through a TMV array (a pair of metal in-substrate structures 502b) and radiate electromagnetic energy outward from the TMV array. The Substrate Array 520 can also be run in reverse as a receiver. Further, the antennas 502b within the array may or may not have metal between them. As shown, there is metal structure 502b between them.
A substrate array 520 allows for antenna functionality within the substrate itself, which would otherwise need to be formed in the interconnect structure or attached to a surface. Embedding an antenna array within the substrate itself can offer both performance and package size advantages.
With the configuration of
A substrate reference 610 can be used to specifically tune the capacitance and impedance of interconnect structures above or below, by varying the depth and other geometries of the substrate reference, relative to the metal substrate surface.
Alternatively, a different substrate reference 620 can be formed with an metal interconnect structure 604b fabricated within the first interconnect structure 604, an in-substrate dielectric isolation pocket (DIP) 602c patterned into the metal core 602a of the metal core substrate 602, a TMV 602b surrounded by the DIP 602c, and a dielectric interconnect structure 604a extending through the second interconnect structure 604. Here a transmission line is formed which launches from a contact C disposed on the metal interconnect structure 604b of the first or second interconnect structure 604, traverses through the metal interconnect structure 604b located above or below the DIP 602c, traverses through the TMV 602b, traverses through the metal interconnect structure 604b formed in the other one of the metal interconnect structures 604b located above or below the DIP 602c and terminates at a second contact C.
This type of substrate reference 620 allows for tuning of capacitance and impedance of an interconnect structure that then traverses through the substrate, by varying the depth and other geometries of the substrate reference, relative to the metal substrate surface.
With the configuration of
A photonic optical waveguide 710 in this configuration allows for the transmission of photonic signals within the interconnect structure dielectric material, encased in interconnect structure metal.
Further, a photonic optical waveguide 720 is another example embodiment of a package interconnect component which can be formed to extend through the metal core substrate based package interconnect system 700. Here a dielectric in-substrate structure 702c is formed through the metal core substrate 702. A first metal interconnect structure 704b can be fabricated to extend through the first interconnect structure 704 to contact the metal core 702a at one side of the dielectric in-substrate structure 702c of a metal core substrate 702, and a second metal interconnect structure 704b can be fabricated to extend through the first interconnect structure 704 to contact the metal core 702a at an opposite side of the dielectric in-substrate structure 702c of a metal core substrate 702. Between the first and second metal interconnect structures 704b can be disposed a contact C on the surface of the interconnect structure 704. Through the second interconnect structure 704, which is disposed on the back side of the metal core substrate 702, are a pair of metal interconnect structures 704b, a first one of the pair of metal interconnect structures 704b being in contact with the metal core 702a at one side of the dielectric in-substrate structure 702c of a metal core substrate 702, and the second one of the pair of metal interconnect structures 704b being in contact with the metal core 702a at the opposite side of the dielectric in-substrate structure 702c of a metal core substrate 702. Between the pair of metal interconnect structures 704b is a contact C disposed on the surface of the second interconnect structure 704. With this configuration the photonic optical waveguide 720 can launch from one contact C and connect with the dielectric interconnect structure 704a that is surrounded by two metal interconnect structures 704b, traverse through the interconnect structure 704 (always being surrounded by either metal core metal 702a and/or metal interconnect structures 704b), connect with the dielectric in-substrate structure 702c and traverse therethrough, connect with the dielectric interconnect structure 704a that is surrounded by the pair of metal interconnect structures 704b in the second interconnect structure 704, traverse through the second interconnect structure 704 and terminate at the other contact C.
A photonic optical waveguide 720 can also be configured to transmit photonic signals within the interconnect structure dielectric material, which then traverses through the substrate to a photonic optical waveguide on the other side, thus allowing for through substrate optical transmission.
With the configuration of
Another configuration of photonic optical waveguide 810 allows for transmission of photonic signals within the interconnect structure dielectric material, which then traverses within the substrate, not-through, to another photonic optical waveguide on the same side.
Further, a photonic optical waveguide 820 is another example embodiment of a package interconnect component which can be formed to extend through the metal core substrate based package interconnect system 800. Here a dielectric isolation pocket (DIP) 802c is formed to extend across a top surface of the metal core 802a of the metal core substrate 802 and then turn downward and through a dielectric in-substrate structure the metal core 802a. A first metal interconnect structure 804b can be fabricated to extend through the first interconnect structure 804 to contact the metal core 802a at one end of the DIP 802c, and a second metal interconnect structure 804b can be fabricated to extend through the first interconnect structure 804 to contact the DIP 802c and then turn and extend along the entire upper surface of the DIP 802c until making contact with the metal core 802a at an opposite end of the DIP 802c. Between the first and second metal interconnect structures 804b can be disposed a contact C on the surface of the interconnect structure 804. Through the second interconnect structure 804, which is disposed on the back side of the metal core substrate 702, are a pair of metal interconnect structures 804b A first one of the pair of metal interconnect structures 804b being in contact with the metal core 802a at one side of the DIP 802c and the second one of the pair of metal interconnect structures 804b being in contact with the metal core 802a at the opposite side of the DIP 802c. Between the pair of metal interconnect structures 804b and on the surface of the second interconnect structure 804 can be disposed another contact C. With this configuration the photonic optical waveguide 820 can launch from one contact C and connect with the dielectric interconnect structure 804a that is surrounded by two metal interconnect structures 804b, traverse through the interconnect structure 804, connect with the DIP 802c and traverse therethrough, connect with the dielectric interconnect structure 804a that is surrounded by the pair of metal interconnect structures 804b in the second interconnect structure 804, traverse through the second interconnect structure 804 and terminate at the other contact C.
Another configuration of photonic optical waveguide 820 allows for transmission of photonic signals within the interconnect structure dielectric material, which then traverses within the substrate, and then through the substrate, to a photonic optical waveguide within the interconnect structure on the opposite side.
With the configuration of
An antenna 910 can be formed within the interconnect structure above or below a dielectric in-substrate structure, allowing for communication to that antenna from the opposite side of the substrate.
Further, a different type of antenna 920 is another example embodiment of a package interconnect component which can be formed to extend through the metal core substrate based package interconnect system 900. Here the metal core substrate 902 includes an dielectric in-substrate structure 902c patterned through the metal core 902a, wherein the dielectric in-substrate structure 902c includes a dielectric insolation pocket (DIP) pattered along the top surface of the metal core 902a, and an metal in-substrate structure 902b patterned through the dielectric in-substrate structure 902c with the dielectric insolation pocket (DIP) disposed to one side of the metal in-substrate structure 902b. An metal interconnect structure 904b can be fabricated to extend through the interconnect structure 904 deposited on the top surface of the metal core substrate 902 down to the DIP 902c and then extend along the DIP 902c until making contact with the metal in-substrate structure 902b. Another metal interconnect structure 904b can be fabricated to extend through the interconnect structure 904 deposited on the back side of the metal core substrate 902 to contact the same metal in-substrate structure 902b. A contact C can be disposed on the end of the metal interconnect structure 904b formed through the interconnect structure 904 deposited on the top surface of the metal core substrate 902.
With this configuration an electronic transmission line can launch from the contact C and connect with and traverse through the metal interconnect structure 904b formed through the interconnect structure 904 deposited on the top surface of the metal core substrate 902 using the metal core 902 as a ground reference, connect with the TMV 902b, connects with the and traverses through the metal interconnect structure 904b formed through the interconnect structure 904 deposited on the back side of the metal core substrate 902 and radiates electromagnetic energy out of the antenna 920.
An antenna 920 can be formed within the interconnect structure which can be electronically connected through a dielectric in-substrate structure, to interconnect structures on the opposite side that may route the signal through the package.
Further, an Array 930 is still another example embodiment of a package interconnect component which can be formed to extend through the metal core substrate based package interconnect system 900. Here the metal core substrate 902 includes dielectric in-substrate structures 902c patterned through the metal core 902a and a pair of metal in-substrate structures 902b patterned through the dielectric in-substrate structure 902c and an metal in-substrate plane structure 902b disposed between the pair of metal in-substrate structures 902b and separated therefrom by the dielectric in-substrate structures 902c. A pair of metal interconnect structure 904b can be fabricated to extend through the interconnect structure 904 deposited on the top surface of the metal core substrate 902 down to make contact with a corresponding one of the metal in-substrate structure 902b. Another pair of metal interconnect structures 904b can be patterned through the interconnect structure 904 deposited on the back side of the metal core substrate 902 and formed to make contact with corresponding ones of the metal in-substrate structures 902b. A contact C can be disposed on the end of each of the metal interconnect structures 904b formed through the interconnect structure 904 deposited on the top surface of the metal core substrate 902.
In this example package interconnect component, a pair of electronic transmission lines can launch from two or more contacts C connected to metal interconnect structures 904b, traverse through the interconnect structure 904, connect with and traverse through a TMV array (a pair of metal in-substrate structures 902b), connect with interconnect system metal structures 904b patterned through the interconnect structure 904 deposited on the back side of the metal core substrate 902 and radiate electromagnetic energy outward from the TMV array. The Array 930 can also be run in reverse as a receiver. Further, the antennas 902b within the array may or may not have metal between them. As shown, there is metal structure 502b between them.
An antenna array 930 can be formed within the interconnect structure above or below a dielectric in-substrate structure array, allowing for communication to the array from the opposite side of the substrate. A substrate reference, or cutaway within the metal substrate, can be used to tune the capacitance of the antennas relative to the metal substrate.
Within an electrically isolated region of the metal core substrate 1002, the metal core 1002b can be etched (i.e. laser ablated) at the top and back side surfaces therein to etch trenches into the top and back surfaces of the metal core 1002b. The etched trenches are preferably formed to create shaped cavities 1002d that remain unfilled to serve as ports for electrical or optical connectors.
On both the top surface and the back side of the metal core substrate 1002 can be fabricated an interconnect structure 1004 including patterned dielectric interconnect structures 1004a and one or more metal interconnect structures 1004b. Here patterned dielectric interconnect structures 1004a are fabricated on the top and bottom surfaces of the metal core substrate 1002, not including above or below cavity 1002d, while a single metal interconnect structure 1004b is fabricated only on the top surface of the metal core substrate 1002. Here, as described from the top down of the center image of
This embodiment allows for creation of mechanical connection interfaces, or connectors, such that an external component or connector can mechanically seat itself within the receiving cavity, with electrical terminations, formed within the metal core based package interconnect system.
The metal in-substrate structures 1102b are formed from the top surface to a back side thereof of the metal core substrate 1102, each being separated by dielectric in-substrate structures 1102c such that the metal in-substrate structures 1102b can be isolated from each other as well as from the metal core 1102a. On both the top surface and the back side of the metal core substrate 1102 can be fabricated an interconnect structure 1104 including patterned dielectric interconnect structures 1104a and one or more metal interconnect structures 1104b. Here patterned dielectric interconnect structures 1104a and some of the metal interconnect structures 1104b are fabricated on the top and bottom surfaces of the metal core substrate 1102 to align with several dielectric in-substrate structures 1102c and metal in-substrate structures 1102b of the metal core substrate 1102. Further, the metal interconnect structures 1104b patterned in both the interconnect structures 1104 deposited on the top surface and back side of the metal core substrate 1102 include contacts C connected to exposed ends thereof in order to receive or transmit signals from or to external devices. In the embodiment of
The metal core substrate based package interconnect system provides a lower coefficient of thermal expansion (CTE) and higher Young's modulus substrate than conventional substrate materials. This reduces CTE mismatch between components and the substrate, and reduces substrate warpage, improving overall reliability of the package.
In this example embodiment the two or more metal core substrates 1202 are each bonded together in a stacking manner. More specifically, a first metal core substrate 1202 (bottom substrate) can be configured to have metal in-substrate structures 1202b and dielectric in-substrate structures 1202c patterned through a first metal core 1202a. A second metal core substrate 1202 (middle substrate) can be configured to be bonded on the top surface of the first metal core substrate 1202 (bottom substrate) and have metal in-substrate structures 1202b and dielectric in-substrate structures 1202c patterned through a second metal core 1202a, as well as having at least one cavity formed therein to embed components therein. In this example embodiment a cavity is formed through the top surface of the second metal core substrate 1202. This cavity extends across a pair of dielectric in-substrate structures 1202c and an metal in-substrate structure 1202b, wherein the metal in-substrate structure 1202b is patterned between the pair of dielectric in-substrate structures 1202c. On top of the metal in-substrate structure 1202b is a contact C with an electronic component (EC) disposed thereon to receive power through the metal in-substrate structure 1202b. Further, a third metal core substrate 1202 (topmost substrate) can be configured to be bonded on the top surface of the second metal core substrate 1202 (middle substrate). This third metal core substrate 1202 (topmost substrate) is configured to have metal in-substrate structures 1202b and dielectric in-substrate structures 1202c patterned therethrough, as well as having a cavity etched into a back side to align with the cavity etched into the top surface of the second metal core substrate 1202 (middle substrate). This example embodiment is configured when an electronic component is large enough that forming a cavity into one metal core substrate 1202 cannot fully embed the electric component EC. Once the EC is placed within the cavity etched into the second metal core substrate 1202 (middle substrate) the third metal core substrate 1202 (topmost substrate) can be aligned with the second metal core substrate 1202 (middle substrate) such that the EC can be fully embedded within the two aligned cavities. Then the second metal core substrate 1202 (middle substrate) the third metal core substrate 1202 (topmost substrate) can be bonded together to form metal core substrate based package interconnect system 1200A including three metal core substrates 1202 bonded together with aligned dielectric in-substrate structures 1202c and an metal in-substrate structures 1202b, as well as at least one cavity with an embedded EC therein. The substrates can be bonded together using a metal-to-metal bond, like a Cu to Cu compression bond, or bonded together using a soldering paste. If the multi-layer stack does not require high subsequent process temperatures, then the substrates can be bonded together using a conductive polymer. Additional electronic components (EC) and/or contacts C can be disposed on either side of the metal core substrate based package interconnect system 1200A. The multi-level System-on-Foil stacked interconnected wafers are referred to as Jetty Blocks or Jetty Boards.
The embodiment in 1200A allows for the stacking of metal core substrates in order to produce more complex routing within the resulting stack than is capable in a single metal core substrate. Additionally, it allows for the inclusion of embedded electronic components within the stack.
In this example embodiment the two or more metal core substrates 1202 are each bonded together in a stacking manner. More specifically, a first metal core substrate 1202 (bottom substrate) can be configured to have metal in-substrate structures 1202b and dielectric in-substrate structures 1202c patterned through a first metal core 1202a. A second metal core substrate 1202 (middle substrate) can be configured to be bonded on the top surface of the first metal core substrate 1202 (bottom substrate) and have metal in-substrate structures 1202b and dielectric in-substrate structures 1202c patterned through a second metal core 1202a. In this example embodiment dielectric in-substrate structures 1202c and metal in-substrate structures 1202b are exposed on the top surface of the second metal core substrate 1202 (middle substrate), wherein one of the metal in-substrate structures 1202b is patterned between a pair of dielectric in-substrate structures 1202c. On top of this metal in-substrate structure 1202b is a contact C with an electronic component (EC) disposed thereon to receive power through the metal in-substrate structure 1202b. Further, a third metal core substrate 1202 (topmost substrate) can be configured to be bonded on the top surface of the second metal core substrate 1202 (middle substrate). This third metal core substrate 1202 (topmost substrate) is configured to have metal in-substrate structures 1202b and dielectric in-substrate structures 1202c patterned therethrough, as well as having a cavity etched into a back side thereof. This cavity is aligned to cover and embed the metal in-substrate structure 1202b having the contact and the electronic component (EC) disposed thereon. Then the second metal core substrate 1202 (middle substrate) the third metal core substrate 1202 (topmost substrate) can be bonded together to form metal core substrate based package interconnect system 1200A including three metal core substrates 1202 bonded together with aligned dielectric in-substrate structures 1202c and an metal in-substrate structures 1202b, as well as at least one cavity with an embedded EC therein. metal core substrate based package interconnect system 1200B.
The embodiment in 1200B allows for the stacking of metal core substrates in order to produce more complex routing within the resulting stack than is capable in a single metal core substrate. Additionally, it allows for the inclusion of embedded electronic components within the stack.
The embodiment in 1300 allows for the stacking of metal core substrates in order to produce more complex routing within the resulting stack than is capable in a single metal core substrate. Additionally, it allows for the inclusion of embedded electronic components within the stack. This stack can be fabricated in wafer format so that wafer-based interconnect structures can then be patterned on the top and back sides, enabling even more routing capacity and attachment of surface components.
The embodiment in 1400 allows for the stacking of multiple metal core substrate based package interconnect systems in order to produce more complex routing and capability than possible in a single metal core substrate based package interconnect system. Electronic components can be attached to the uppermost or bottommost interconnect structures.
On opposite surfaces of the two metal core substrates 1502 (the surfaces metal core substrates 1502 which are not bonded to each other) can be deposited an interconnect structure 1504 having metal interconnect structures 1504b connected to the metal in-substrate structures 1502b of both metal core substrates 1502 and dielectric interconnect structures 1504c patterned between the metal interconnect structures 1504b. Some of the metal interconnect structures 1504b patterned in one of the interconnect structures 1504 can have contacts C connected thereto. Connected to the contacts can be metal in-substrate structures 1502b of a second metal core substrate based package interconnect system 1500b having a metal core substrate 1502 and an interconnect structure 1504 deposited on a top surface and back side thereof. As such, signals, power and ground can pass through the metal in-substrate structures 1502b of the two directly bonded metal core substrates 1502, through the metal interconnect structures 1504b of the interconnect structures 1504 deposited on the metal core substrates 1502, through the contacts, and through the metal interconnect structures 1504b and the metal in-substrate structures 1502b of the second metal core substrate based package interconnect system 1500. Further, additional contacts C can be connected to at least one of metal interconnect structures 1504b which are exposed at a top surface of the second metal core substrate based package interconnect system 1500b. On these contacts C can be connected additional electronic components EC.
The interconnect structure 1504 deposed on the other side of the two bonded metal core substrates 1502 of the first metal core substrate based package interconnect system 1500a can include additional metal core substrates 1502 and interconnect structures 1504 connected thereto, with metal in-substrate structures 1502b and metal interconnect structures connected together.
Here, one package interconnect system is being used as a board to support the connection of at least one other package interconnect system, operating as a package. The benefit is that both the board and the package have the same metal cores and so the same CTE, which minimizes thermomechanical stress formation and improves reliability.
Although a few embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the appended claims and their equivalents.
This application claims the benefit of Provisional Application No. 63/487,345, filed Feb. 28, 2023, entitled “SYSTEM ON FOIL.” The benefit under 35 USC § 119(e) of the United States provisional application is hereby claimed, and the aforementioned provisional application is hereby incorporated herein by reference in its entirety.
| Number | Date | Country | |
|---|---|---|---|
| 63487345 | Feb 2023 | US |
