Patent Application
20240153864
Generally, semiconductor devices can include a plurality of circuits which form an integrated circuit fabricated on a substrate. A complex network of signal paths can be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals can include the formation of multilevel or multilayered schemes (e.g., single or dual damascene wiring structures) during the back-end-of-line (BEOL) phase of manufacturing. Within an interconnect structure, conductive vias can run perpendicular to the substrate and conductive lines can run parallel to the substrate.
Illustrative embodiments of the present application include techniques for use in semiconductor manufacture. In an illustrative embodiment, a semiconductor structure comprises a skip via disposed on a metal line of a first metallization layer, and a dielectric layer disposed on sidewalls of the skip via to define an opening. The dielectric layer has uniform sidewalls from an uppermost portion of the opening to a lowermost portion of the opening.
According to another exemplary embodiment, a semiconductor structure comprises a skip via disposed on a metal line of a first metallization layer. The skip via comprises a first portion disposed in a first interlayer dielectric layer, and a second portion disposed in a second interlayer dielectric layer. The semiconductor structure further comprises a dielectric layer disposed on sidewalls of the first portion and the second portion of the skip via to define an opening. The dielectric layer has a varying thickness. The dielectric layer has uniform sidewalls from an uppermost portion of the opening to a lowermost portion of the opening.
According to yet another exemplary embodiment, an integrated circuit comprises one or more semiconductor structures. At least one of the one or more semiconductor structures comprises a skip via disposed on a metal line of a first metallization layer, and a dielectric layer disposed on sidewalls of the skip via to define an opening. The dielectric layer has uniform sidewalls from an uppermost portion of the opening to a lowermost portion of the opening.
These and other exemplary embodiments will be described in or become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings.
Exemplary embodiments will be described below in more detail, with reference to the accompanying drawings, of which:
This disclosure relates generally to semiconductor devices, and more particularly to skip via connections between metallization levels and methods for their fabrication. Exemplary embodiments will now be discussed in further detail with regard to semiconductor devices and methods of manufacturing same and, in particular, to skip via connections between metallization levels and methods for their fabrication.
A semiconductor device can include multiple metallization levels (“levels”), each including a conductive line (“line”) formed in an interlayer dielectric layer (ILD). Although the term metallization is used herein, metallization levels can be formed to include any suitable conductive material in accordance with the embodiments described herein. Upper lines can be connected to lower lines by vias. Levels can be identified herein using the designation X, where X is a positive integer from 1 to N. The levels are identified from the level closest to the substrate to the level furthest from the substrate as 1 through N where 1 is the first or lowermost level and N is the last or uppermost level. A line in the X level is designated as an MX line, and a via in the X level is designated as a V(X−1) via. Note that there are no V0 vias or via bars. When a line in an upper level is designated MX, then a line in an immediately lower level can be designated M(X−1). Likewise, when a line in a lower level is designated MX, then a line in an immediately higher level is designated M(X+1). For a first level (X=1), the line is M1 and there are no “V0” vias as the connection from M1 to devices below M1 is generally made through separately formed contacts in a contact layer (“CA”). For a second level (X=2), the line is M2 and the vias are V1 and, for a third level (X=3), the line is M3 and the vias or via bars are V3.
A skip via in accordance with the embodiments described herein can provide a connection between conductive lines of respective metallization levels in a manner that bypasses an intermediate metallization level. Skip vias are typically formed through one or more dielectric layers to establish an electrically conductive connection between a pair of targeted metallization layers, while bypassing (i.e., avoiding an electrically conductive connection) with one or more intervening metallization layers located between the targeted metallization layers.
Presently, a method to form a skip via involves forming a single via through the interconnect structure, and then subsequently performing a single metal fill process that fills the via with a metal material to form the skip via. This method, however, has a tendency to form metal fill voids due to undercut and a bowing profile which can result in potential short risk between the skip via and adjacent metal lines.
The illustrative embodiments described herein overcome the foregoing drawbacks by providing for the fabrication of a skip via having a partial dielectric fill on sidewalls of the skip via thereby eliminating bowing in the formation of skip vias. This, in turn, can prevent any potential short risk between the skip via and adjacent metal lines.
It is to be understood that the various layers, structures, and/or regions shown in the accompanying drawings are schematic illustrations that are not necessarily drawn to scale. In addition, for ease of explanation, one or more layers, structures, and regions of a type commonly used to form semiconductor devices or structures may not be explicitly shown in a given drawing. This does not imply that any layers, structures, and regions not explicitly shown are omitted from the actual semiconductor structures.
Furthermore, it is to be understood that the embodiments discussed herein are not limited to the particular materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it is to be emphasized that the descriptions provided herein are not intended to encompass all of the processing steps that may be used to form a functional semiconductor integrated circuit device. Rather, certain processing steps that are commonly used in forming semiconductor devices, such as, for example, wet cleaning and annealing steps, are purposefully not described herein for economy of description.
Moreover, the same or similar reference numbers are used throughout the drawings to denote the same or similar features, elements, layers, regions, or structures, and thus, a detailed explanation of the same or similar features, elements, layers, regions, or structures will not be repeated for each of the drawings. Also, in the figures, the illustrated scale of one layer, structure, and/or region relative to another layer, structure, and/or region is not necessarily intended to represent actual scale.
It is to be understood that the terms “about” or “substantially” as used herein with regard to thicknesses, widths, percentages, ranges, etc., are meant to denote being close or approximate to, but not exactly. For example, the term “about” or “substantially” as used herein implies that a small margin of error may be present, such as 1% or less than the stated amount.
Reference in the specification to “one embodiment” or “an embodiment” of the present principles, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment of the present principles. Thus, the appearances of the phrase “in one embodiment” or “in an embodiment”, as well any other variations, appearing in various places throughout the specification are not necessarily all referring to the same embodiment. The term “positioned on” means that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements, such as an interface structure, e.g., interface layer, may be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the scope of the present concept.
As used herein, “height” refers to a vertical size of an element (e.g., a layer, trench, hole, opening, etc.) in the cross-sectional views measured from a bottom surface to a top surface of the element, and/or measured with respect to a surface on which the element is located. Conversely, a “depth” refers to a vertical size of an element (e.g., a layer, trench, hole, opening, etc.) in the cross-sectional views measured from a top surface to a bottom surface of the element. Terms such as “thick”, “thickness”, “thin” or derivatives thereof may be used in place of “height” where indicated.
As used herein, “width” or “length” refers to a size of an element (e.g., a layer, trench, hole, opening, etc.) in the drawings measured from a side surface to an opposite surface of the element. Terms such as “thick”, “thickness”, “thin” or derivatives thereof may be used in place of “width” or “length” where indicated.
Referring now to the drawings in which like numerals represent the same of similar elements,
Semiconductor structure 100 further includes a first metallization level Mx−1 having a plurality of metal containing lines 104 disposed on substrate layer 102 and dielectric layer 106-1 disposed on substrate layer 102 and between adjacent metal containing lines 104. First metallization layer Mx−1 with metal containing lines 104 may be formed from any suitable conductive metal including, for example, copper (Cu), aluminum (Al), chromium (Cr), cobalt (Co), hafnium (Hf), iridium (Ir), molybdenum (Mo), niobium (Nb), osmium (Os), rhenium (Re), rhodium (Rh), ruthenium (Ru), tantalum (Ta), titanium (Ti), tungsten (W), vanadium (V), zirconium (Zr), and alloys thereof. In one embodiment, a conductive metal layer is one or more of Al, Ru, Ta, Ti or W. In one embodiment, a conductive metal is Ru. The plurality of metal containing lines 104 may be formed using photolithography, etching and deposition processes. For example, in some embodiments, a pattern (not shown) is produced on the metal layer by applying a photoresist to the surface to be etched; exposing the photoresist to a pattern of radiation; and then developing the pattern into the photoresist utilizing resist developer. Once the patterning of the photoresist is completed, the photoresist is removed. The etch process may be an anisotropic etch, such as reactive ion etch (RIE). The etch process may also be a selective etch process.
A dielectric layer 106-1 is deposited on substrate layer 102 and in between adjacent metal containing lines 104. Dielectric layer 106-1 may be made of any known dielectric material such as, for example, silicon oxide, silicon nitride, hydrogenated silicon carbon oxide, low-k dielectrics, ultralow-k dielectrics, flowable oxides, porous dielectrics, or organic dielectrics including porous organic dielectrics. Low-k dielectric materials have a nominal dielectric constant less than the dielectric constant of SiO2, which is approximately 4 (e.g., the dielectric constant for thermally grown silicon dioxide can range from 3.9 to 4.0). In one embodiment, low-k dielectric materials may have a dielectric constant of less than 3.7. Suitable low-k dielectric materials include, for example, fluorinated silicon glass (FSG), carbon doped oxide, a polymer, a SiCOH-containing low-k material, a non-porous low-k material, a porous low-k material, a spin-on dielectric (SOD) low-k material, or any other suitable low-k dielectric material. Ultra-low-k dielectric materials have a nominal dielectric constant less than 2.5. Suitable ultra-low-k dielectric materials include, for example, SiOCH, porous pSiCOH, pSiCNO, carbon rich silicon carbon nitride (C-Rich SiCN), porous silicon carbon nitride (pSiCN), boron and phosporous doped SiCOH/pSiCOH and the like.
The dielectric layer 106-1 may be formed by any suitable deposition technique known in the art, including atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), chemical solution deposition or other like processes.
Although the first metallization level Mx−1 is shown as being formed directly on the substrate layer 102, the semiconductor structure 100 is not limited thereto. For example, one or more additional layers including, but not limited to, an adhesion layer, a nucleation layer and/or an etch stop layer can be formed between the substrate layer 102 and the first metallization level Mx−1.
Semiconductor structure 100 further includes a first via level Vx−1 and a second metallization level Mx formed on etch stop layer 108-1. Etch stop layer 108-1 is deposited on dielectric layer 106-1 and metal containing lines 104 using conventional deposition techniques such as ALD. The etch stop layer 108-1 is a dielectric material such as SiN and SiCN.
First via level Vx−1 and second metallization level Mx include dielectric layer 106-2 having via 110 and metal containing line 112 disposed therein. For example, dielectric layer 106-2 is patterned and subjected to an etching process such as a wet or dry etch to form via 110 of first via level Vx−1, with the etch stop layer 108-1 at the bottom of via 110 being removed by a dry etching. Dielectric layer 106-2 can be formed by a similar process and of similar material as dielectric layer 106-1. Metal containing line 112 is connected to one of metal containing lines 104 through via 110. Via 110 and metal containing line 112 can be formed of any of the conductive metals discussed above for metal containing lines 104.
Second layer 114b is deposited on the top surface of first layer 114a by conventional deposition techniques such as ALD, CVD, PVD or spin on deposition. Suitable material for second layer 114b includes any hardmask material such as, for example, TiN, SiO2, TaN, SiN, AlOx, SiC and the like. Second layer 114b is patterned by forming metal containing lines and a skip via in third metallization layer Mx+1, as discussed below, and by forming openings 116a, 116b, 116c and 116d using standard lithographic processing.
Next, the mask layer 118 is patterned and a selective etch process such as reactive ion etching (ME) can be carried out to form skip via opening 120. When forming skip via opening 120, a first portion of skip via opening 120 disposed in dielectric layer 106-2 will be formed having a varying width “W3” and a second portion of skip via opening 120 disposed in ILD layer 106-3 will be formed having a varying width “W2” with widths W2 and W3 being greater than width W1 of opening 116b (see
Semiconductor devices and methods for forming the same in accordance with the above-described techniques can be employed in various applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing embodiments of the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell and smart phones), solid-state media storage devices, functional circuitry, etc. Systems and hardware incorporating the semiconductor devices are contemplated embodiments of the invention. Given the teachings provided herein, one of ordinary skill in the art will be able to contemplate other implementations and applications of embodiments of the invention.
In some embodiments, the above-described techniques are used in connection with semiconductor devices that may require or otherwise utilize, for example, CMOSs, MOSFETs, and/or FinFETs. By way of non-limiting example, the semiconductor devices can include, but are not limited to CMOS, MOSFET, and FinFET devices, and/or semiconductor devices that use CMOS, MOSFET, and/or FinFET technology.
Various structures described above may be implemented in integrated circuits. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case the chip is mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a motherboard or other higher-level carrier) or in a multichip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case the chip is then integrated with other chips, discrete circuit elements, and/or other signal processing devices as part of either: (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
