Patent Application
20070278002
An understanding of the present teachings can be gained from the following detailed description, taken in conjunction with the accompanying drawings of which:
As shown in
As shown in
The epoxy mixture 180, may be copper epoxy or silver epoxy, or any known thermally conductive epoxy. The epoxy may also be non-thermally conductive. The via hole 130 structure may be filled with printed circuit board resin. Even thought the via hole is filled with non-thermally conductive material, the via hole structure will be significantly improved in terms of thermal impedance, due to the fact that the land pad or solder pad and pin escape traces are removed from the path between the solder ball and the via, since the solder ball can now be soldered directly to the via hole 130. As shown in the flow chart of
The epoxy 180 may be planarized (230) with the surface of the printed circuit board assembly 100 with any known planarizing process, such as a chemical etch process, followed by a mild, quick sanding operation. The surface 182 of the epoxy 180 may be plated (235) with copper nickel, and/or gold, which is known as capping the via, or the via may be left as is, depending on the application and desired thermal and electrical performance. The via hole 130 may then be attached (240) directly to the solder ball 140 of the surface mount device package 120 using a surface mount reflow process (250).
As will be readily appreciated, attaching device solder balls 140 directly to solid filled via holes 130 completely eliminates the pin escape traces and solder pads of the prior art, and also reduces the overall thermal path and thermal impedance of the printed circuit board assembly. This also permits the via hole 130 to be drilled to a larger diameter than in the past. The larger via hole 130 contains more copper due to the larger circumference of the via hole 130. This will improve the thermal impedance of the via hole 130.
It will be appreciated that other methods and materials may be used within the spirit of the present invention. For example, the vias may be filled with copper epoxy, silver epoxy, or non-thermally conductive printed circuit board resin. The planarization process may be omitted if the solder stencil is thick enough to compensate for the surface roughness of the filled via 130. If the planarization is done, this may be done by a process called nub removal, which involves a simple sanding process followed by a quick chemical polish. The vias 130 may be capped with copper, nickel, gold or with copper, pladium, gold. The nickel deposition may be electroplated or electroless deposition. The gold may be pure immersion gold or hard electroplated gold. The pladium may be either electroplated or electroless.
