Patent Application
20080145536
1. Field of the Invention
Embodiments of the present invention generally relate to methods and apparatus for depositing films on semiconductor substrates. More particularly, embodiments of the invention relate to methods and apparatus for depositing silicon boron nitride films.
2. Description of the Related Art
Ultra-large-scale integrated (ULSI) circuits typically include more than one million transistors that are formed on a semiconductor substrate and which cooperate to perform various functions within an electronic device. Such transistors may include complementary metal-oxide-semiconductor (CMOS) field effect transistors.
A CMOS transistor includes a gate structure that is disposed between a source region and a drain region defined in the semiconductor substrate. The gate structure or stack generally comprises a gate electrode formed on a gate dielectric material. The gate electrode controls a flow of charge carriers beneath the gate dielectric in a channel region that is formed between the drain region and the source region so as to turn the transistor on or off. Typically disposed proximate the gate stack is a spacer, which forms a sidewall on both sides thereof. Sidewall spacers serve several functions, including, electrically isolating the gate electrode from source and drain contacts or interconnects, protecting the gate stack from physical degradation during subsequent processing steps, and providing an oxygen and moisture barrier to protect the gate electrode.
A conventional gate stack is formed from materials having dielectric constants of less than about 6 (k<6) and is typically protected by a silicon nitride spacer. Further reduction in transistor sizes will likely require gate layers having dielectric constants of greater than 10 (k>10). If the sidewall spacer is then fabricated from a relatively high k (k>7) material, such as silicon nitride, excessive signal crosstalk between adjacent interconnection lines can occur during use of the device containing the completed gate electrode. While ultra-low k materials (k<3) may be employed as a spacer layer, these materials often lack the necessary structural integrity to survive subsequent processing steps and/or requisite oxygen and moisture imperviousness to protect the gate electrode from corrosion.
In addition, conventional thermal chemical vapor deposition (CVD) process used to prepare silicon nitride spacers requires high deposition temperatures which are typically greater than 650° C. Such silicon nitride spacers deposited at high temperatures have very good conformality. However, the high deposition temperature results in a large thermal budget for the gate device and is not compatible with advanced device manufacturing for 65 nm technology and beyond.
Therefore, there is a need for lower temperature and lower k sidewall spacers for gate stacks.
The present invention generally provides methods and apparatus for depositing silicon boron nitride films. In one embodiment, an apparatus for processing a substrate comprises a chamber and a gas delivery system connected to the chamber. The gas delivery system comprises a gas mixing block, a first gas line system having an input connected to a source of a boron-containing precursor and an output connected to a first inlet of the mixing block, a second gas line system having an input connected to a source of nitrogen-containing precursor that does not include silicon and an output connected to a second inlet of the mixing block, and a third gas line system having an Input connected to a source of a silicon-containing precursor and an output connected to a third inlet of the mixing block.
In another embodiment, a method of processing a substrate comprises introducing a substrate into a chamber, introducing a nitrogen-containing precursor that does not include silicon into the chamber at a first flow rate, introducing a boron-containing precursor into the chamber at a second flow rate, wherein the ratio of the first flow rate to the second flow rate is greater than or equal to about 10, introducing a silicon-containing precursor into the chamber, and reacting the nitrogen-containing precursor, the boron-containing precursor, and the silicon-containing precursor in the chamber to deposit a silicon boron nitride film on the substrate. Diborane may be used as the boron-containing precursor. Ammonia may be used as the nitrogen-containing precursor. Bis(tertiary butylamino)silane may be used as the silicon-containing precursor.
So that the manner in which the above recited features of the present invention can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
The present invention provides methods and apparatus for depositing silicon boron nitride (SiBN) films. The silicon boron nitride films have lower dielectric constants, e.g., between about 4.2 and about 5.7, and low wet etch rates that are desirable for spacer layers.
The silicon boron nitride films may be deposited by conventional thermal chemical vapor deposition (CVD) or pulsed CVD. Examples of CVD chambers that may be modified to deposit the silicon boron nitride films include the SiNgen® and SiNgen-Plus™ chambers, both of which are available from Applied Materials, Inc. of Santa Clara, Calif. An exemplary CVD chamber will be described below with respect to
A substrate support 111 supports the substrate and may provide heat to the chamber. In addition to the substrate support, the base of the chamber may contain additional apparatus further described below, including a reflector plate, or other mechanism tailored to facilitate heat transfer, probes to measure chamber conditions, an exhaust assembly, and other equipment to support the substrate and to control the chamber environment.
Feed gas may enter the chamber through a gas delivery system before passing through an inlet 113 in the lid 110 and holes (not shown) in a first blocker plate 104. The feed gas then travels through a mixing region 102 created between a first blocker plate 104 and a second blocker plate 105. The second blocker plate 105 is structurally supported by an adapter ring 103. After the feed gas passes through holes (not shown) in the second blocker plate 105, the feed gas flows through holes (not shown) in a face plate 108 and then enters the main processing region defined by the chamber wall 106, the face plate 108, and the substrate support 111. Exhaust gas then exits the chamber at the base of the chamber through the exhaust pumping plate 107. Optionally, the chamber may include an insert piece 101 between the chamber wall 106 and the lid 110 that is heated to provide heat to the adaptor ring 103 to heat the mixing region 102. Another hardware option illustrated by
The lid assembly includes an initial gas inlet 213 through which the feed gas passes before entering a space 202 defined by the lid 209, the thermal break elements 212, the heater jacket 203, and the blocker plates 204 and 205. The space 202 provides increased residence time for the reactant precursor gases to mix before entering the substrate processing portion of the chamber. Heat that may be applied by a heater 210 to the surfaces that define the space 202 helps prevent the buildup of raw materials along the surfaces of the space. The heated surfaces also preheat the reactant precursor gases to facilitate better heat and mass transfer once the gases exit the face plate 208 and enter the substrate processing portion of the chamber.
Returning to
Gas line system 250 comprises an input 251 connected to a source 252 of a silicon-containing precursor and an output 259 connected to an inlet 228 of the gas mixing block 220. The silicon-containing precursor may be such as bis(tertiary butylamino)silane (BTBAS), for example. The source 252 of the silicon-containing precursor may be a bulk ampoule. The silicon-containing precursor flows from the source 252 to a process ampoule 253 and then flows into a liquid flow meter 254. The metered silicon-containing precursor flows into a vaporizer 255, such as a piezo-controlled direct liquid injector. Optionally, the silicon-containing precursor may be mixed in the vaporizer 255 with a carrier gas such as nitrogen from a gas source 256 that is connected to the vaporizer 255. Additionally, the carrier gas may be preheated before addition to the vaporizer. The resulting gas is then flowed through gas line 257 and introduced to an inlet 228 of the gas mixing block 220 via output 259. Optionally, the gas line 257 connecting the vaporizer 255 and the gas mixing block 220 may be heated.
By using three separate gas line systems for introducing the silicon-containing precursor, nitrogen-containing precursor, and boron-containing precursor into the gas mixing block, the mixing volume and time during which the precursors are mixed before they are introduced into the processing region of the chamber are minimized. It has been found that using the apparatus described herein to deposit silicon boron nitride films resulted in significantly fewer in-film particles compared to silicon boron nitride films deposited using an apparatus in which the boron-containing precursor and the nitrogen-containing precursor are pre-mixed before they are introduced into a gas mixing block. Also, the generation of equipment contaminating or clogging particles is minimized by not pre-mixing the precursors before they are introduced into the gas mixing block.
Deposition of Silicon Boron Nitride Films
Embodiments of the invention provide a method of depositing a silicon boron nitride film that comprises reacting a nitrogen-containing precursor, a boron-containing precursor, and a silicon-containing precursor to deposit a silicon boron nitride film on a substrate in a chamber. The nitrogen-containing precursor, boron-containing precursor, and silicon-containing precursor may be reacted in a conventional chemical vapor deposition process or a pulsed chemical vapor deposition process.
In one embodiment, a substrate is introduced into an apparatus comprising a chamber, a substrate support disposed in the chamber, a chamber lid, and a gas delivery system connected to the chamber lid, wherein the gas delivery system comprises a gas mixing block, a first gas line system having an input connected to a source of a boron-containing precursor and an output connected to a first inlet of the mixing block, a second gas line system having an input connected to a source of a nitrogen-containing precursor that does not include silicon and output connected to a second inlet of the mixing block, and a third gas line system having an input connected to a source of a silicon-containing precursor and an output connected to a third inlet of the mixing block. A silicon boron nitride film is then deposited on the substrate in the chamber. An example of an apparatus that may be used to perform this embodiment is described above with respect to
In any of the embodiments of the invention, the boron-containing precursor preferably comprises diborane (B2H6), such as pure diborane or diborane mixed with hydrogen, helium, or argon, for example. However, other boron-containing precursors, such as boron trichloride (BCl3), may be used. A preferred nitrogen-containing precursor that does not contain silicon is ammonia (NH3). However, other nitrogen-containing precursors that do not contain silicon, such as hydrazine (N2H4), may be used. Silicon-containing precursors that may be used include dichlorosilane (SiH2Cl2), hexachlorodisilane (Si2Cl6), silane (SiH4), and disilane (Si2H6). A preferred silicon-containing precursor, which is also a nitrogen-containing precursor, is bis(tertiary butylamino)silane (BTBAS). Silicon boron nitride films deposited using BTBAS may comprise a small amount of carbon.
Examples of processing conditions that may be used to deposit the silicon boron nitride films will now be provided. The boron-containing precursor, e.g., diborane, may be introduced into a chamber at a flow rate between about 5 sccm and about 50 sccm, such as between about 10 sccm and about 30 sccm. The nitrogen-containing precursor, e.g., NH3, may be introduced into a chamber at a flow rate between about 50 sccm and about 2000 sccm. The silicon-containing precursor, e.g., BTBAS, may be introduced into a chamber at a flow rate between about 100 mg/min and about 800 mg/min, such as between about 300 mg/min and about 600 mg/min. A carrier or diluent gas such as nitrogen (N2) may also be introduced into the chamber at a flow rate between about 2000 sccm and about 20000 sccm.
In one embodiment, the flow rates of the nitrogen-containing precursor, e.g., NH3, and the boron-containing precursor, e.g., diborane, are chosen such that the ratio of the flow rate of the nitrogen-containing precursor to the flow rate of the boron-containing precursor is greater than or equal to about 10. It has been unexpectedly found that using such a ratio for depositing the silicon boron nitride films reduces the number of in-film particle adders having a size of 0.16 μm or greater to about 50 or less.
The substrate temperature during the deposition of the silicon boron nitride films may be between about 300° C. and about 600° C., such as between about 520° C. and about 550° C. The chamber pressure during the deposition of the silicon boron nitride films may be between about 10 Torr and about 500 Torr. The spacing between the substrate support and the faceplate or showerhead may be between about 500 and about 1000 mils, such as between about 500 mils and about 800 mils.
In one aspect, the silicon boron nitride films provided herein may be used as spacer layers in transistor gates.
Further, an electrically conductive gate electrode layer 436 is blanket deposited over gate dielectric layer 450. Generally, the gate electrode layer 436 may comprise a material such as doped polysilicon, undoped polysilicon, silicon carbide, or silicon-germanium compounds. However, contemplated embodiments may encompass a gate electrode layer 436 containing a metal, metal alloy, metal oxide, single crystalline silicon, amorphous silicon, silicide, or other material well known in the art for forming gate electrodes.
A hard-mask layer (not shown), such as a nitride layer, is deposited via a CVD process over gate electrode layer 436. A photolithography process is then carried out including the steps of masking, exposing, and developing a photoresist layer to form a photoresist mask (not shown). The pattern of the photoresist mask is transferred to the hard-mask layer by etching the hard-mask layer to the top of the gate electrode layer 436, using the photoresist mask to align the etch, thus producing a hard-mask (not shown) over the gate electrode layer 436.
The structure is further modified by removing the photoresist mask and etching the gate electrode layer 436 down to the top of the gate dielectric layer 450, using the hard-mask to align the etch, thus creating a conductive structure including the remaining material of gate electrode layer 436 underneath the hard-mask. This structure results from etching the gate electrode layer 436, but not the hard-mask or gate dielectric layer. Continuing the processing sequence, gate dielectric layer 450 is etched. The gate electrode 436 and the gate dielectric layer 450 together define a composite structure 424, sometimes known as a gate stack, or gate, of an integrated device, such as a transistor.
In further processing of the gate stack, shallow source/drain extensions 440 are formed adjacent source/drain regions 448 by utilizing an implant process. The gate electrode 436 protects the substrate region beneath the gate dielectric from being implanted with ions. A rapid thermal process (RTP) anneal may then be performed to drive the tips 440 partially underneath the gate dielectric.
Next, an optional conformal thin oxide layer 425 is deposited over the entire substrate surface. This oxide layer is used to protect the silicon surface from the spacer layer 426, which is typically a silicon nitride layer. The conformal thin oxide layer is typically deposited in a low pressure chemical vapor deposition chamber at high temperature (>600° C.). The thin oxide layer relaxes the stress between the silicon substrate and the nitride spacer and it also protects the gate corners from the silicon nitride spacer by providing another layer of material.
In one embodiment of the invention, a silicon boron nitride spacer layer 426, with a thickness in the range between about 100 Å to about 800 Å, preferably between about 100 Å to about 500 Å, is blanket deposited over the top of the composite structure 424 and along the entire length of the sides of the gate stack 424, including the entire length of the sidewalls of the gate electrode 436 and the gate dielectric. At the same time, the silicon boron nitride spacer layer 426 is deposited on top of any exposed portion of the substrate 400 or isolation regions 422.
The silicon boron nitride films provided herein have several properties that are desirable properties for spacer layers. The silicon boron nitride films can be deposited at temperatures as low as 350° C. at a good deposition rate. By tuning the flow rates of the precursors, silicon boron nitride films having a dielectric constant (k) between about 4.2 and about 5.7 can be obtained. For example, a dielectric constant of about 4.5 (as measured by a SSM 6200 metrology system, available from Solid State Measurements, Inc., at a frequency of 1 MHz for a capacitor area of 3×10−5 cm2) was obtained for a silicon boron nitride film deposited at 520° C. and 275 Torr with a diborane flow rate of 30 sccm, an NH3 flow rate of 40 sccm, a BTBAS flow rate of 305 mgm, and a nitrogen flow rate of about 1300 sccm. Such low dielectric constant spacers improve device performance, e.g., device speed, by reducing the fringe capacitance between the gate electrode and the source and drain regions of a transistor, which is becoming an increasingly important factor as gate lengths reach 45 nm or less.
The silicon boron nitride films provided herein also have good step coverage and pattern loading effect (PLE) performance. The silicon boron nitride films were deposited over densely patterned features (60 nm line width, 180 nm line spacing) semi-densely patterned features (65 nm line width, 435 nm line spacing), and isolated features (65 nm line width, 1185 nm line spacing). The silicon boron nitride films provided greater than 92% step coverage for all three feature densities, and the pattern loading effect was about 10%.
Additionally, as shown by Table 1, the silicon boron nitride films provided herein have low wet etch rates, which is a desirable property for films that are used as spacers or other types of protection layers.
While the foregoing is directed to embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.
