METHOD AND APPARATUS FOR MONITORING AND CONTROLLING WAFER FABRICATION PROCESS

Abstract

A method and apparatus for monitoring, measuring and/or controlling the etch rate in a dry etch semiconductor wafer processing system. The wafer processing system has a monitoring assembly which comprises an electromagnetic radiation source and detector which interferometrically measures the etch rate. The source, preferably a UV light source, is directed at a portion of the wafer surface where the etching is taking place. A first portion of the UV light reflects back from the surface at one phase because it is reflected from the surface of the features of the wafer and a second portion of the UV light reflects from the bottom of the features at a slightly different phase. The differences in these phases when properly filtered set up interference patterns which are more intense where the differently phased first and second portions of the light combine or interfere and less intense where they cancel. The interference pattern by its change in wave length is proportional or representative of the rate of change in the etch pattern. The actual rate of change of the etch as it progresses is measured by this technique and is compared to a model of a desired rate of change in a controller. The error between the actual rate of change and the desired rate of change is then used to vary at least one of the process parameters of the system in a direction tending to null the difference.

Description

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates generally to semiconductor wafer processing systems, and more particularly, to method and apparatus for monitoring, processing and fabrication of such wafers using interferometric in situ measurement of the etch rate.

[0004] 2. Description of Background

[0005] Integrated circuit wafer processing systems, particularly those which fabricate VLSI circuits on silicon wafers, can use many processes to form the circuit features on a wafer. One of the more prevalent processes is “dry etching” where a reactive gas in a plasma state is used to react with material on the wafer surface or an underlying substrate through a series of photoresist masks to produce the desired circuit features. Dry etching, also known as reactive ion etching (RIE), requires constant monitoring of the process to produce the desired results. Even relatively small uncontrolled changes in process parameters such the composition, pressure, flow rate or the ionization state of the etching gas, or the wafer temperature, electrode bias, etc. may cause unsatisfactory results.

[0006] When etching a three dimensional structure, conditions at the etch front change significantly during processing. The presence of side walls in the vicinity of the etching surface influences the influx of neutrals, ions and inhibitor precursors as well as the removal of reaction products causing changes in the etch rate. This effect is called aspect ratio dependent etch rate (ARDE) (also known as RIE lag), and as the name suggests the etch rate changes with the aspect ratio of a feature and not the etch depth. The aspect ratio of a feature is generally given by the ratio of the width of the feature to the depth of the feature.

[0007] The modality of ARDE is not fully understood and is a highly complex phenomenon. Various models have been proposed to explain the change in etch rate with increasing aspect ratio and differ mainly in which aspect of the etch mechanism, the ionic or the neutral component, is emphasized. Those studies which concentrate on the ionic component investigate such mechanisms as mask charging, ion shadowing, and localized surface charging giving rise to a significant ion flux to the sidewall. The ionic component etching may also be influenced by the power density loss at the bottom of the feature and the deposition of passivating layers at the bottom of the etched feature. This modality of etching is therefore very complex, hard to control and has some particularly detrimental effects to the etched feature including sidewall imperfections.

[0008] The influence of the neutral species on ARDE can be described by the easier to control effects of neutral shadowing and Knudsen transport. In a model proposed by Coburn and Winters in Applied Physics Letters 55 (1989) 2730, the neutral species effects on ARDE are described with the assumption that the etch rate is determined solely by the reaction of neutral etch species and the ionic component is neglected. Further, it is assumed that there is no etching of the sidewalls and the neutral species are reflected diffusely when colliding with the sidewall. Therefore, it would be highly desirable to control the ARDE of an integrated circuit etching process by the control of the neutral species effects of etching.

[0009] As feature size in modern integrated circuit fabrication continues to shrink, aspect ratios in general become larger and mask layers thinner. It is desirable to control the complex ARDE rate while fabricating an integrated circuit upon a semiconductor wafer.

[0010] Therefore, a need exists in the art for a method and apparatus for measuring and controlling the etch rate during the fabrication of integrated circuits that contain high aspect ratio features.

SUMMARY OF THE INVENTION

[0011] The invention provides a method and apparatus for monitoring, measuring and/or controlling the etch rate in a semiconductor wafer processing system. Specifically, a wafer processing system has a monitoring assembly which comprises an electromagnetic radiation source and detector which interferometrically measures the etch rate. The source, preferably a UV light source, is directed at a portion of the wafer surface where the etching is taking place. A portion of the UV light reflects back from the surface of the features of the wafer and another portion of the UV light reflects from the bottom of the features. There is a difference in phase between these two portions due to the extra distance of travel for the portion reflected from the bottom of the features. The difference in these phases forms an interference pattern which is more intense where the differently phased first and second portions of the light combine or interfere constructively and less intense where they cancel. The interference pattern is proportional or representative of the rate of change in the etch depth. The actual rate of change of the etch as it progresses is measured by this technique and is compared to a model of a desired rate of change in a controller. The error between the actual rate of change and the desired rate of change is then used to vary at least one of the process parameters of the system in a direction tending to null the difference. The actual rate of change is also an indicator of RIE lag (i.e., the change in etch rate that depends upon aspect ratios).

[0012] According to one aspect of the invention, the control of the parameters of the system is made to maintain the etch rate constant over the process. This will provide uniformity to the features particularly for a wafer with a high aspect ratio or with an ARDE feature.

[0013] According to another aspect of the invention, important process parameters such as etch gas flow, chamber pressure, source power and cathode temperature, either alone or in combination, can be used to control RIE lag.

[0014] These and other objects, aspects and features of the invention will be more clearly understood and better described when the following detailed description is read in conjunction with the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The teachings of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings, in which:

[0016] FIG. 1 is a cross-sectional schematic view of a wafer processing chamber that operates in accordance with the present invention;

[0017] FIG. 2 is a graphical representation of intensity as a function of time for an interference pattern produced by the etch rate measurement system illustrated in FIG. 1;

[0018] FIG. 3 is a pictorial system flow diagram of the etch rate processing routine of the controller illustrated in FIG. 1;

[0019] FIG. 4 is a pictorial representation of the geometry and aspect ratio of a feature used for a number of processing runs using the system illustrated in FIG. 1;

[0020] FIG. 5 is a cross-sectional side view taken along lines 5-5 of the feature illustrated in FIG. 4;

[0021] FIG. 6 is a tabular representation of a number of processing runs a-i for measuring RIE lag as a function of the various process parameters for the system illustrated in FIG. 1;

[0022] FIGS. 7 a -7i are graphical representations of the measurement of the etch rate (normalized by starting etch rate) as a function of aspect ratio for the processing runs a-i illustrated in the table of FIG. 6;

[0023] FIGS. 8 a -8d are graphical representations of normalized RIE lag as a function of particular process parameters for the data of FIGS. 6 and 7; and

[0024] FIG. 9 is a graphical representation of normalized etch rate as a function of aspect ratio for theoretical and experimental conditions.

[0025] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures.

DETAILED DESCRIPTION

[0026] FIG. 1 is cross-sectional side schematic view of an illustrative wafer processing system 100 that operates in accordance with the present invention. The wafer processing system 100 is particularly adapted to vacuum process workpieces, such as silicon wafers, for integrated circuits of the very large system integration (VLSI) type. Regulation of the dry etch chemical processes performed in the chamber, the sequence of those processes, and the transfer of the wafers to the chamber is controlled by a general purpose computer with associated memory, control circuitry and driver circuitry, and an operator interface in the form of a controller 102.

[0027] The wafer processing system 100 comprises a processing chamber 104 with an entry slit 106 (e.g., a slit valve) for the insertion and removal of a workpiece, for example, a silicon wafer 108. The chamber 104 houses a support pedestal 110 upon which the wafer is retained. The pedestal 110 generally comprises a chuck 112 (either electrostatic or mechanical) for physically retaining the wafer and a cathode 114 for supporting the chuck and biasing the wafer. An RF excitation source 118 (e.g., 13.56 MHz) is also electrically connected to the pedestal 110 which acts as a cathode. The cathode can be biased by a DC bias source 116 regulated by the controller 102 to influence the ion energy of the plasma gas in chamber 104. The ion energy ranges between 5 and 10 eV and is typically determined by the self bias of the plasma in contact with the wafer surface. Preferably, the plasma is a high density quasi remote fluorine plasma. The control of process gas flow, in the preferred example SF6 via source 120, is provided by a flow control valve 122 under regulation of the controller 102. The SF6 flow rate is typically in the range of 30 to 180 standard cubic centimeters per minute (sccm). The dome 132 enclosing the top of the process chamber 104 supports a set of coils (an antenna) which form an RF radiating element 134. The element 134 is coupled to an RF power source 124 (e.g., 13.56 MHz) also regulated by controller 102 for the purpose of ionizing the process gas in the chamber 104. The high density plasma may be sustained using the RF radiating element 134 only. The RF power applied to the radiating element 134 is typically between 50 and 900 Watts. Power may be applied to the cathode 114 for short periods of time (approximately 6 seconds) during breakthrough steps. The temperature of the cathode 114 is typically between 20 and 65° C. Additional heating of the chamber may be provided by infra-red heating elements located above the dome 132 within the dome temperature control unit (DTCU) 136.

[0028] The chamber 104 and associated processing equipment is preferably embodied by a Metal Etch Decoupled Plasma Source (DPS) chamber manufactured by Applied Materials of Santa Clara, Calif. A dome temperature control enclosure and apparatus of the Metal Etch DPS chamber is disclosed in U.S. patent application Ser. No. 08/767,071, filed Dec. 16, 1996 and is herein incorporated by reference. An etch depth measuring system of the Metal Etch DPS chamber is disclosed in U.S. patent application Ser. No. 08/944,240, filed Oct. 6, 1997 and is herein incorporated by reference.

[0029] The controller 102 receives feedback on the process parameters through a series of sensors and measurement devices including a temperature sensor 140 which provides a temperature signal to it indicative of cathode temperature, and a pressure sensor 142 which provides a pressure signal indicative of the chamber pressure. The wafer processing system 100 includes an etch rate measurement system 144 comprising a source 130 and detector 128 operating in conjunction with an etch rate processing routine 138 that is executed on a computer such as the controller 102. The source 130 is preferably a mercury lamp generating light in the UV range while the detector 128 is a photodiode or photomultiplier tube sensitive to UV radiation. The source light is guided through an optical fiber 146 onto a mirror 148. The source light is directed by the mirror 148 to the surface of the wafer 108 through a lens 150 which focuses it on a small portion of the surface. Preferably, the spot diameter is approximately 25 mm. in order to cover more than one die on the wafer surface. The source light is then reflected from the surface and refocused on the mirror 148 by lens 150. The reflected light passes back through optical fiber 146 to a filter in the detector 128. The filter allows light within a narrow band of wavelengths (λ) to pass. For example a band pass filter that transmits a narrow band centered on λ=254 nm with a full width at half maximum (FWHM) of 2 nm may be used. The light transmitted by the filter is, thus, approximately monochromatic. Interference of the reflected light can therefore by readily observed at the detector 128. The interference is due to first and second portions of the reflected light being out of phase because of the difference in travel time due to one part reflecting off the top of a feature (trench) on the wafer and the other part reflecting off the bottom of a feature. The detector 128 senses the filtered reflected light and transduces it into an electrical signal.

[0030] The interference signal sent to the controller 102 is more fully shown in FIG. 2. It can be readily shown that the depth change in a feature (trench) that corresponds between two maxima, or two minima, is λ/2 (or 127 nm when λ=254 nm). Therefore, measuring the elapsed time between two depths, (i.e., the time between two conjugate points, i.e. two maxima or two minima, points on the waveform of FIG. 2) allows for the calculation of the average etch rate between the two points. When calculating the etch rate for all pairs of extrema (minima and maxima), the etch rate change as a function of time for etching deeper into the structure can be determined. As the depth of the trench increases, the etch rate generally decreases. It is noted from the interference signal that normally for constant process parameters, the time between extrema increases, indicating a decreasing etch rate with increasing etch depth. The rate of change in the frequency indicates the rate of change of the etch rate. Although normally the frequency decreases with etch depth, ARDE may cause other variations in etch rate due to an aspect ratio change as the etch progresses. For example, in inverse RIE (inverse ARDE) etch rate increases with increasing depth.

[0031] FIG. 3 is a flow diagram of the process of controlling etch rate for the system illustrated in FIG. 1 where in block A10 the process parameters of the system are initialized. The controller 102 brings the chamber up to processing temperature and pressure and controls the flow rate of processing gas into the chamber, the initial bias is set on the cathode 114 and the RF power supplies 118 and 120 controlled to initiate plasma conditions within the chamber 104. The etch rate measurement system 144 is then activated in block A12 to measure the actual etch rate for the process. Once the actual etch rate has been determined and stored, the controller 102 will determine from an etch rate profile for the particular process and the operating parameters, including time, temperature and process gas flow rate, the desired etch rate. The actual etch rate is compared in block A16 to the stored profile of the desired etch rate of the process and an error is calculated.

[0032] Alternatively, an average etch rate profile can be calculated from measured etch rate profiles for many wafers (e.g., several hundred) having a given set of process parameters and stored, for example, in the controller 102. The etch rate processing routine then processes subsequent wafers by comparing the stored profile of the average etch rate to the stored profile of the desired etch rate in block A16 to calculate the etch rate error.

[0033] The etch rate error is tested in block A18 for its sign, i.e., whether the actual etch rate of the process is too fast or too slow. For a too fast etch rate (sign positive) the program continues at block A22 and block A24 where one or more etch rate parameters which increase etch rate are decremented, or alternatively, one or more process parameters which decrease etch rate are incremented. For a too slow etch rate (sign negative) the program continues at block A20 and block A26 where one or more etch rate parameters which increase etch rate are incremented, or alternatively, one or more process parameters which decrease etch rate are decremented.

EXAMPLES A-I

[0034] To better understand the dependence of etch rate on the variance of the process parameters of the system illustrated in FIG. 1, a series of process runs a-i were made using differing values for the process parameters of process gas flow, chamber pressure, source power, and cathode temperature. The etch rate was measured in situ using the interferometric measurement system described. FIGS. 4-8 will now be more fully described to disclose the results of those test runs.

[0035] FIG. 4 pictorially illustrates the geometry of the features used in the test runs a-i after etching to a final depth of z=1000 nm. The features 50 are essentially holes in the shape of a pyramidal frustum having a rectangular cross-section that is reduced at larger depths z. This results in a reduction of the open area during the etch and has been taken into account in the data analysis. These features were chosen for their large aspect ratio which produces considerable ARDE, i.e., as the etch progresses the aspect ratio changes and causes a substantial change in etch rate.

[0036] A cross-section of one of the features 50 is shown in FIG. 5. A silicon wafer 52 has been manufactured with a deep trench 54 filled with arsenic doped polysilicon 56. The trench 54 has thin side walls of oxynitride 58 and the top of the silicon 52 is covered by a nitride layer 60. This configuration was used to determine if etch rate and the wafer processing system could be improved for selective etching, i.e., it was desired that the etch process be very selective to the top nitride layer and the sidewall oxynitride. The tests achieved selectivities of 200:1 between polysilicon 56 in the trenches 54 and the top nitride layer 60 with SF6 plasma and without power applied to the cathode, i.e., using antenna power only.

[0037] FIGS. 7 a -7i illustrate normalized etch rates (instantaneous etch rate divided by starting etch rate for a flat wafer) as a function of the aspect ratio for nine different sets of process conditions. The values of the particular process parameters for each example is set forth in the table illustrated in FIG. 6. The slope of a least squares fit through the data points is a measure of the RIE lag effect. As can be seen in FIGS. 7a-7i, the RIE lag effect differs significantly for different process parameter values. Example c indicates an inverse RIE lag which, however, is not usually observed unless the etch process is accompanied by a deposition process, which is believed highly unlikely for the illustrated silicon etch with a fluorine chemistry. It is believed the inverse RIE lag in example c is an artifact and that the RIE lag for this example is more likely close to zero for this process run.

[0038] FIGS. 8 a -8d show RIE lag (as given by the slopes of FIGS. 7a-7i) as a function of the four different process parameters of source power, chamber pressure, cathode temperature and process gas flow. The error bars in the figures illustrate the scatter of data points of FIGS. 7a-7i. These figures reveal that the chamber pressure and cathode temperature influence RIE lag strongly. For higher pressure (20 m Torr) and lower cathode temperature (20 deg C.), the RIE lag is reduced and close to zero when averaging the data points. It is believed that the strong influence of the chamber pressure and cathode temperature on RIE lag is predicted by the Knudsen transport model.

[0039] The Knudsen transport model divides the incoming flux of etch species (e.g., fluorine) on top of the structure νt into a first portion of neutrals that are reflected out of the feature without reaching the etch front (1−K)νt, and a second portion that reaches the etch front but does not react K(1−S)νb. Here, K is the transmission probability for the feature, S is the reaction probability and νb is the flux of etch species at the bottom of the feature. The incoming flux also includes a third portion, namely that portion of etch species which reaches the etch front and does react Sνb. The transmission probability K is dependent on the geometry of the feature. The value of K for round pipes or slit like tubes can be found in standard vacuum technology references such as A Users Guide to Vacuum Technology, J. F. O'Hanlon; John Wiley & Sons, New York, 1989, pp. 36-37, or Scientific Foundations of Vacuum Technique, Second Edition, S. Dushman, J. M. Lafferty; John Wiley & Sons, New York, 1962, p. 94, both of which are incorporated herein by reference. The three portions balance according to the equation:

Sν b =νt−(1−K)νt−K(1−S)νb  (eq. 1).

[0040] The model assumes that the etch rate will be proportional to the flux of fluorine atoms (the ionic component is neglected). Therefore, the relative change of the etch rate for a certain aspect ratio z/d can be expressed as:

R (z/d)/R(0)=K/(K+S−KS)  (eq. 2).

[0041] Here z is the depth of the feature and d is the width. R(0) is, therefore, the etch rate at the bottom of a feature having either zero depth or infinite width and is proportional to νt. R(z/d) is the etch rate at the bottom of a feature having depth z and width d and is proportional to νb. The fit parameter in eq. 2 is the reaction probability S, which is generally unknown for the given etch conditions. If this parameter can be determined for given set of experimental conditions, a theoretical value of the normalized etch rate R(z/d)/R(0) can be determined from equation 2 for all values of z/d for those experimental conditions. A reaction probability S of 0.00168 has been reported for fluorine atoms at 23° C. with an undoped single crystal of silicon at a pressure range of several Torr (see D. L. Flamm, V. M. Donelly, J. A. Mucha; Journal of Applied Physics, 52 (1981) 3633 incorporated herein by reference).

[0042] FIG. 9 shows a graph 900 of theoretical and experimental dependence of the normalized etch rate R(z/d)/R(0) on aspect ratio z/d using K values for a round tube. The normalized etch rate is plotted along a vertical axis 901 and aspect ratio is plotted along a horizontal axis 903. The theoretical dependence has an upper limit given by S=0.00168. An upper curve 902 bounds a first shaded region 904. The first shaded region 904 indicates values of the normalized etch rate that are larger than possible under the Knudsen transport model. Note that curve 902 indicates that almost no RIE lag would be present for a reaction probability of 0.00168. A lower curve 906 has been calculated for a reaction probability S=1, which is the upper limit for RIE lag due to the Knudsen effect. A stronger decline in etch rate with increasing aspect ratio than that indicated by a lower curve 906 cannot be explained solely by Knudsen transport. Thus a second shaded region 908 indicates values for the normalized etch rate that are too small to be possible under the Knudsen model. Acceptable values lie in an unshaded region 910 that lies between the upper and lower curves 902 and 906.

[0043] The circles 912 in FIG. 9 represent data points from experiment (e) and the triangles 914 represent data points from experiment (h). The data points lie substantially within the unshaded region 910. These data points can be fitted using eq. 2 resulting in reaction probabilities of 0.03 and 0.11 for experiments (e) and (h) respectively. In these fits the change in the open area of the feature due to the taper angle of the structures has been taken into account. Excluding experiment (c), which shows a reverse RIE lag, all other experimental runs gave reaction probabilities of between 0.03 and 0.11. Once a reaction probability has been established for a given set of experimental conditions, an expected etch rate can be calculated.

[0044] One consequence of the Knudsen model is that the RIE lag depends mainly on the reaction probability and, hence, on surface coverage. This is why a reduced RIE lag effect is observed for experiments at high pressure and/or lower cathode temperature. For these conditions, the surface coverage is larger and the transport of the neutrals is no longer a limiting factor.

[0045] The dependence of the RIE lag on process gas flow and source power are less clear. When averaging the data points for the same value of one of the parameters, either source power or process gas flow, only a weak dependence is obtained. Source power and process gas flow have, however, a strong impact on the silicon etch rate. Further, the RIE lag shows a strong correlation with the quotient of chamber pressure divided by cathode temperature, while the silicon etch rate shows a dependence on the product of the source power and process gas flow. The latter can be readily explained by the fact that the silicon etch rate is determined by the fluorine atom supply at the etch front. For high process gas flows and source powers, this effect levels out indicating a fluorine saturation at the etch front.

[0046] This data, and other similarly derived empirical information, can be used to formulate the desired etch rate schedule used in the closed loop control described for FIG. 1. Such schedules are then stored as functions or look up tables which the controller 102 uses to determine the desired etch rate for the process under consideration at the time. Different processes will use different parameters to advantage, with strongly influencing parameters such as process gas flow and cathode temperature being used for gross or overall control, or for fast correction, and secondary parameters perhaps being used for close tolerances and slower changes.

[0047] While the invention has been described in connection with a preferred embodiment, this specification is not intended to limit the scope of the invention to the particular forms set forth, but, on the contrary, it is intended to cover any such alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims.

Claims

1. Apparatus for controlling a wafer processing system, having a chamber, and a pedestal within said chamber, the apparatus comprising: an interferometer for generating a signal indicative of a rate of an aspect ratio dependent etch (ARDE) occurring within said chamber; and a controller coupled to said interferometer and said wafer processing system, for varying one or more process parameters of said wafer processing system in response to said signal.

2. The apparatus of claim 1, wherein said interferometer further comprises: a light source; a lens, optically coupled to said light source; and a detector.

3. The apparatus of claim 2 wherein said interferometer further comprises: an optical fiber, coupled between said light source, said lens and said detector.

4. The apparatus of claim 1 further comprising: an antenna proximate said chamber; and an RF power supply, coupled to said antenna and said controller, for supplying RF power to said chamber.

5. The apparatus of claim 1 further comprising: a pressure sensor coupled to said chamber and said controller for measuring a pressure within said chamber.

6. The apparatus of claim 1 further comprising a cathode and a temperature sensor coupled to said cathode and said controller.

7. The apparatus of claim 6 further comprising a chuck.

8. The apparatus of claim 1 further comprising: a reactive gas source, coupled to said chamber and said controller, for delivering a reactive gas to said chamber.

9. The apparatus of claim 1 further comprising: an etch rate processing routine executed by said controller, controlling an etch rate of said wafer processing system, said etch rate processing routine executing the steps of: measuring an actual etch rate; determining a desired etch rate; comparing said actual etch rate to said desired etch rate to determine an etch rate error; and varying said one or more process parameters.

10. A method for controlling a wafer processing system which uses a dry etching process, the system comprising a chamber, RF antennae, an interferometer and a controller, the method comprising the steps of: measuring an actual aspect ratio dependent etch (ARDE) rate in situ; comparing the actual ARDE rate to a desired etch rate and generating an error signal indicative thereof; varying at least one processing parameter of the system to achieve the desired etch rate.

11. The method of claim 10, wherein the step of measuring the actual ARDE rate includes: measuring the actual ARDE rate interferometrically.

12. The method of claim 11, wherein the interferometric measuring further comprises light reflected from a top surface of a feature on a wafer in the wafer processing system interfering with light reflected from a bottom surface of said feature.

13. The method of claim 10, wherein said at least one processing parameter is chosen from the group consisting of source power, chamber pressure, cathode temperature and process gas flow.

14. A wafer processing system comprising: a chamber; a pedestal, within said chamber, for supporting a wafer; an etch rate measurement system coupled to said chamber, having a source and a detector, wherein said source provides light that is reflected off said wafer and said detector receives said light and said detector produces a signal that is indicative of a rate of an aspect ratio dependent etch (ARDE) occurring within said chamber; and a controller, coupled to said chamber, for receiving said signal and controlling one or more process parameters of said ARDE.

15. The wafer processing system of claim 14 further comprising: an etch rate processing routine executed by said controller, controlling an etch rate of said wafer processing system, said etch rate processing routine executing the steps of: measuring said aspect ratio dependent etch rate; determining a desired etch rate; comparing said actual etch rate to said desired etch rate to determine an etch rate error; and varying said one or more process parameters.

16. A method for controlling a wafer processing system which uses a dry etching process, the system comprising a chamber and a controller the method comprising the steps of: measuring an actual etch rate profile for each of a plurality of wafers; calculating an average etch rate profile for said plurality of wafers; storing said average etch rate profile in said controller; determining a desired etch rate profile; comparing said average etch rate profile to said desired etch rate profile while processing a subsequent wafer to determine an etch rate error; and varying one or more process parameters to achieve the desired etch rate.