BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a simplified diagram of a phase change device;
FIG. 2 is a graph illustrating the low resistance crystalline state and the high resistance amorphous state of a phase change device;
FIG. 3A is a graph showing the characteristics of a set pulse used to program a phase change device, according to a prior art method;
FIG. 3B is a graph showing the characteristics of a set pulse used to program a phase change device, according to another prior art method;
FIG. 4 is a graph illustrating the resistance after programming of soft, typical and hard phase change devices for different programming currents;
FIG. 5 is a graph of the resistance after programming of a phase change device versus programming current for various programming pulses of different durations;
FIG. 6 is a block diagram of an exemplary programming apparatus for programming a phase change device, according to an embodiment of the present invention;
FIG. 7 is a schematic drawing of an exemplary verify circuit, which can be used in the programming apparatus shown in FIG. 6;
FIG. 8 is a flow chart illustrating an exemplary method of programming a phase change device to a low resistance state, according to an embodiment of the present invention;
FIG. 9 is a schematic drawing of an exemplary current magnitude adjustment circuit, which may be used to adjust the current magnitude of a programming pulse, according to an aspect of the present invention;
FIG. 10 is a schematic drawing of a duration control circuit, which can be used to adjust the duration of a programming pulse, according to an aspect of the present invention; and
FIG. 11 is a drawing illustrating a series of programming pulse sequences, according to an exemplary embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
Referring to FIG. 6, there is shown a block diagram of an exemplary apparatus 60 for programming a phase change device (PCD), according to an embodiment of the present invention. The programming apparatus 60 is operable to program a PCD to a low resistance state from any other resistance state, according to a novel programming method of the present invention. The programming apparatus 60 comprises a pulse generator 600, a verify circuit 602, a control circuit 604. A PCD to be programmed 606 is selectively coupled to either the pulse generator 600 or the verify circuit 602. As explained in detail below, the novel programming method of the present invention comprises one or more sequences of two principle operations —a set operation and a verify operation. The control circuit 604 is operable to selectively couple the pulse generator 600 and verify circuit 602 to the PCD 606 during application of the programming method, which is described in detail below. According to an aspect of the invention, the control operations performed by the control circuit 604 are based on observed device behavior, so that program time and possibilities of failure are minimized.
FIG. 7 is a schematic drawing of an exemplary verify circuit 70, which may be used to implement the verify circuit 602 in the programming apparatus 60 in FIG. 6. The verify circuit 70 comprises a comparator 700 having two inputs 702, 704 and an output 706. A first input 702 is coupled to the PCD 606 when the control circuit 604 has selected the verify circuit 60. The second input 704 of the comparator 700 is coupled to a reference device 708, which may comprise a pre-programmed reference PCD having known current characteristics, or any other suitable device capable of providing a reference. Other verify techniques such as, for example, use of a voltage reference may also be employed.
FIG. 8 is a flow chart illustrating a method 80 of programming a PCD to a low resistance state, according to an embodiment of the present invention. While the various steps of the method 80 are shown as occurring in a particular ordered sequence of steps, this order is only exemplary and one or more of the steps may be performed before or after one or more other steps of the method 80. At step 800 the magnitude (e.g., 350 μA) and/or duration (e.g., 100 ns) of a programming current pulse (i.e., set pulse) to be applied to the PCD 606 is determined and set. Those of ordinary skill in the art will understand that the actual magnitude and pulse duration may depend on the particular technology employed. So, for example, the set pulse magnitude selected could vary from a few tens of microamperes to a few milliamperes, and the set pulse duration selected could vary from a few nanoseconds to a few microseconds. At step 802 the control circuit 604 operates to couple the pulse generator 600 to the PCD 606. Then, at step 804, in a first attempt to program the PCD 606 to a low resistance state, the pulse generator 600 directs the set pulse having the characteristics defined in step 800 through the PCD 606. After the set pulse has completely passed through the PCD 606, at step 806 the control circuit 604 operates to deselect the pulse generator 600 and couple the verify circuit 602 to the PCD 606. Once coupled to the PCD 606, at step 808 the verify circuit 602, using for example the reference device 708 of the comparator in the exemplary verify circuit 70 in FIG. 7, determines whether the resistance value of the PCD 606 satisfies a predetermined target resistance or falls within a range of predetermined acceptable resistances. If a test current is passed through the PCD 606 during the verification process, the current is maintained at a relatively lower magnitude of the programming current, so that the test current does not affect the set state established during the programming steps. If the verify circuit 602 determines that the initial set pulse has succeeded in setting the PCD 606 to the target resistance, the method 80 is complete. If, on the other hand, the verify circuit 602 determines that the initial set pulse was unsuccessful in setting the PCD 606 to the target resistance, the method continues at the decision in step 810.
According to an exemplary aspect of the method 80, if the PCD 606 is determined not to have been programmed to the predetermined target resistance, one or more subsequent set pulses in a sequence of set pulses having the same magnitude and pulse duration may be applied to the PCD 606, in an attempt to lower the resistance to the predetermined target resistance. After each time the verify circuit determines that the resistance of the PCD 606 has not been set to the predetermined target resistance, a decision at step 810 determines whether a maximum allowable number of set pulses in the sequence have been applied. If “no”, steps 802 through 808 are repeated until the desired target resistance is achieved or the maximum allowable number of pulses in the sequence has been applied. If the maximum number of set pulses in the sequence is determined to have been applied by the decision at step 810 (i.e., “yes” at step 810), it is likely that the PCD 606 is not typical. In other words, an unsuccessful setting of the PCD 606 to the desired low resistance target state is an indication that the PCD 606 is a soft device, a hard device (see FIG. 4 above), or possibly a defective device.
According to an exemplary aspect of the method 80, the magnitude and/or pulse duration of the set pulse may be adjusted to form one or more subsequent sequences of set pulses, if the decision at step 810 determines that the maximum allowable number of original set pulses of the initial sequence have been applied. Before any adjustments to the magnitude or pulse duration are effected, however, a decision at step 812 queries as to whether a predefined maximum allowable programming time has been exceeded. A maximum allowable programming time may be necessary, given that certain PCDs may be defective or otherwise incapable of being programmed to the desired target resistance. Accordingly, at step 812, if it is determined that a maximum allowable programming time has been exceeded, the method 80 terminates, and the PCD 606 is sorted out as a failed device. If, on the other hand, it is determined that the maximum allowable programming time has not been exceeded, the method branches back to step 800.
If the decisions at steps 810 and 812 determine that the PCD 606 is either a soft device or a hard device, and that the maximum allowable programming time has not been exceeded, at step 800 the magnitude of the set pulses is adjusted. Whether the set pulse magnitude should be increased or decreased depends on whether the PCD being programmed 606 is a soft device or is a hard device. Because it cannot be definitively determined whether the PCD 606 is a soft device or is a hard device, an assumption is made that it is a soft device. As was shown in FIG. 4, compared to hard devices, soft devices are capable of being programmed to a low resistance state using a lower magnitude set pulse. Adjusting the set pulse magnitude to a lower magnitude current (e.g., 250 μA) is preferred, since it avoids the risk of damaging or melting the device. It also avoids the potential problem of inadvertently programming softer devices into the amorphizing range (see FIG. 4), which has the effect of increasing the device resistance. Nevertheless, whereas the adjustment to a lower magnitude is preferred, it is not mandatory, and the method 80 could also be continued by increasing the magnitude of the set pulse.
FIG. 9 is a schematic diagram of an exemplary current magnitude adjustment circuit 90, which may be used to adjust the current magnitude of the set pulse in step 800. The current magnitude adjustment circuit 90 comprises a unit current generator 902 and one or more current mirrors 904 having predetermined multiplication ratios. The desired total programming current pulse magnitude (i.e., set pulse magnitude) is achieved by turning on or turning off control devices 906 associated with each current mirror 904. By turning one or more of the control devices 906 off, the total programming current pulse magnitude is decreased. Conversely, by turning one or more of the control devices 906 on, the total programming current pulse magnitude is increased.
As alluded to above, the duration of the set pulse may also (or alternatively) be adjusted at step 800. FIG. 10 is a schematic drawing of duration control circuit 1000, which can be used to adjust the duration of the set pulse. The duration control circuit 1000 comprises a down counter 1002 and an AND logic gate 1004. The down counter has an output that is coupled to a first input of the AND gate 1004. A second input of the AND gate 1004 is configured to receive logic high signal (identified in FIG. 4 as “magnitude_i”). The down counter 1002 also includes a clock input (“clk”) configured to receive a clock signal of a predetermined frequency, a reset input configured to receive a reset signal defining the start of the set pulse, and a value (“val”) input, which may comprise several input signals for the required multiple of clock period. The output of the down counter 1002 remains high as the counter 1002 counts from the beginning of the reset signal until it counts down to the required time interval defining the desired pulse duration. Because the magnitude_i input also receives a high signal, the output of the AND gate 1004 (labeled “ctl_i” in the drawing), which is coupled to one or more of the control device inputs in the current magnitude adjustment circuit 90 in FIG. 9, also remains high during this time interval. Once the counter 1002 reaches the end of the count down time interval, the clock signal causes the output of the counter 1002 to go low, thereby causing the output of the AND gate to also drop low.
After the magnitude and/or duration of the set pulse have/has been adjusted, at step 802 the control circuit 604 operates to couple the pulse generator 600 to the PCD 606. FIG. 11 shows an example of the programming sequence. A first sequence 1100 of two initial set pulses described above has pulses with the original magnitude of (350 μA) and duration (100 ns). The first sequence 1100 of two initial set pulses is followed by a second sequence 1102 of two adjusted set pulses, each having a magnitude of, for example, 250 μA.
After the control circuit 604 couples the pulse generator 600 to the PCD 606, at step 804 the pulse generator 600 directs the first reduced-magnitude set pulse of the second sequence 1102 of set pulses through the PCD 606. After the first reduced-magnitude set pulse has completely passed through the PCD 606, at step 806 the control circuit 604 operates to deselect the pulse generator 600 and couple the verify circuit 602 to the PCD 606. Once coupled to the PCD 606, at step 808 the verify circuit 602 determines whether the resistance value of the PCD 606 satisfies the predetermined target resistance. If the verify circuit 602 determines that the modified set pulse has succeeded in setting the PCD 606 to the target resistance, the method 80 is complete. If, on the other hand, the verify circuit 602 determines that the modified set pulse was unsuccessful in setting the PCD 606 to the target resistance, the method continues at the decision in step 810. The decision at step 810 determines whether a maximum allowable number of set pulses in the second sequence 1102 has been applied. If “no”, steps 802 through 808 are repeated until the desired target resistance is achieved or until the maximum allowable number of pulses in the second sequence 1102 has been applied.
The decision at step 812 then once again queries as to whether the predefined maximum allowable programming time has been exceeded. If “yes”, the method 80 terminates, and the PCD 606 is sorted out as a failed device. If “no”, i.e., the maximum allowable programming time has not been exceeded, the method branches back to step 800, where it is assumed that the PCD 606 is a hard device. At step 800, the set pulse magnitude is increased (to, for example, 450 μA) and the process described above is repeated above with an increased magnitude sequence of set pulses (see sequence 1104 in FIG. 11).
While the method 80 has been described in terms of a specific exemplary programming sequence, those of ordinary skill in the art will readily appreciate and understand that various modifications to the method can be used to successfully program a PCD to a low resistance state. For example, instead of fixing the duration of set pulses in a sequence of set pulses in the hundreds of nanoseconds, a sequence of set pulses having shorter but increasing durations (e.g., such as a few nanoseconds to a few tens of nanoseconds) may be generated and applied. The sequence of shorter pulses of increasing pulse duration may then be used to precisely set the desired low resistance value. Second, different pulse durations within a sequence or among sequences of set pulses may also be used, depending on the application and programming requirements. Third, the number of different set pulse magnitudes can be modified within a programming sequence or among a plurality of programming sequences. For example, instead of using a series or sequence of set pulses, if the uniformity of the technology is good, a single or multiple large magnitude set pulses may be applied to reduce programming time. Accordingly, if a plurality of PCDs fabricated from a particular technology across a die or chip is known to have very uniform material and operating characteristics, a single large magnitude pulse may be sufficient to set one or more of the plurality of PCDs to their low resistance states. The required set pulse magnitude and duration can be characterized in advance using a reference PCD, after which the predetermined set pulse magnitude and duration can be applied to selected ones of the plurality of PCDs. Indeed, if the fabrication and material is very uniform, the verify steps described in the method 80 may not be necessary.
Finally, the methods described above, including the one or more possible variations just discussed, can be combined to enable multiple level resistance states. Using the data in FIG. 5, for example, it is seen that the set and reset states discussed above occupy resistance ranges of <3 kΩ and >100 kΩ, respectively. These two resistance ranges are useful for binary memory. However, a tri-level resistance device can be implemented by utilizing the resistance values between 3 kΩ and 100 kΩ. Further, a two-bit storage device can be realized by programming the PCD to one of four different resistance values (e.g., <3 kΩ, 6-10 kΩ, 20-50 kΩ, and >100 kΩ), using the data in FIG. 5 as an example. To achieve resistance values in these four ranges, a short-duration pulse in the range of a few nanoseconds to a few tens of nanoseconds may be applied, while the magnitudes of pulses in a sequence of the applied pulses are increased from a lower magnitude to a higher magnitude.
Although the present invention has been described with reference to specific embodiments thereof, these embodiments are merely illustrative, and not restrictive, of the present invention. Additionally, various modifications or changes to the specifically disclosed exemplary embodiments will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.
Patent Application
20080025080
