Claims
- 1. An apparatus for functional verification of a device design, comprising:a test generator module for constraint based random test generation for automatically creating a verification test for said device; and a checking module for checking the data accuracy of said test when performed on said device; wherein said design can be verified.
- 2. The apparatus of claim 1, wherein said device is a simulation of any module, chip, and system.
- 3. The apparatus of claim 1, further comprising:an interactive debugging module for displaying data events and the interrelations of said data events, and for permitting modifications to said device design.
- 4. The apparatus of claim 1, further comprising a reporting module for generating reports regarding said test and said device.
- 5. The apparatus of claim 4, further comprising a coverage module for showing the distribution of occurrences in a multi-dimensional space thus providing the user with information to locate gaps in the verification process.
- 6. The apparatus of claim 1, wherein said test generator automatically creates a test from a functional description.
- 7. The apparatus of claim 1, wherein said apparatus is operable to perform any combination of deterministic tests, random tests, dynamic tests, and static tests.
- 8. An apparatus for functional verification of a device design, comprising:a test generator module for constraint based random test generation for automatically creating a verification test for said device, said test generator dynamically creating said test in response to a current state of said device; and a checking module for checking the data accuracy of said test when performed on said device; wherein said design can be verified.
- 9. An apparatus for functional verification of a device design, comprising:a test generator module for constraint based random test generation for automatically creating a verification test for said device; a checking module for checking the data accuracy of said test when performed on said device; wherein said design can be verified; and a verified specific object-orientated programming language for constructing and customizing said verification tests.
- 10. The apparatus of claim 9, wherein said verification specific object-orientated programming language is extensible.
Parent Case Info
This is a continuation of application Ser. No 09/020,792, filed Feb. 6, 1998 which claims the benefit of U.S. Ser. No. 60/048,755 filed Jun. 3, 1997.
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Entry |
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Provisional Applications (1)
|
Number |
Date |
Country |
|
60/048755 |
Jun 1997 |
US |
Continuations (1)
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Number |
Date |
Country |
Parent |
09/020792 |
Feb 1998 |
US |
Child |
09/668001 |
|
US |