Patent Application
20230387238
The present disclosure relates to complementary metal oxide semiconductor (CMOS) structures and methods of forming the same. More particularly, the present disclosure provides a method of forming CMOS structures having low contact resistance.
Complementary metal-oxide-semiconductor (CMOS) technology may be used to form integrated circuits (ICs), useful in various applications including but not limited to microprocessors, microcontrollers, logic circuits, static random access memory (RAM), etc. CMOS field effect transistors (FETs) are employed in almost every electronic circuit application such as signal processing, computing, and wireless communications.
According to some embodiments of the disclosure, there is provided a CMOS device. The device includes a pFET epi and an nFET epi. The pFET epi includes a single dielectric layer that wraps around a first portion of the pFET epi and a confined trench epi on a second portion of the pFET epi that is adjacent a first contact. The nFET epi includes a bi-layer dielectric liner that wraps around a first portion of the nFET epi and a second portion of the nFET epi that is adjacent a second contact.
According to some embodiments of the disclosure, there is provided a semiconductor structure. The structure includes a first field-effect transistor (FET) having a first source/drain (S/D), wherein the first S/D comprises an nFET material. The structure also includes a second FET having a second S/D, wherein the second S/D comprises a pFET material. Also, the structure includes an epi layer containing germanium (Ge) and located on the second S/D.
According to some embodiments of the disclosure, there is provided a method of forming a CMOS structure. One operation in the method or process is forming an nFET epi on a substrate in a first S/D region. Another operation is depositing a first dielectric liner over the nFET epi. A further operation is forming a pFET epi on the substrate in a second S/D region. Yet another operation is depositing a second dielectric liner over both the pFET epi and the first dielectric liner that is deposited over the nFET epi. Another operation is depositing an interlayer dielectric (ILD) layer in the first and second S/D regions. A further operation is etching the ILD layer to remove portions of the ILD layer to form a first contact opening in the first S/D region and a second contact opening in the second S/D region, wherein during the etching, the second dielectric liner is removed within the first and second contact openings. Another operation is forming a trench epi on the pFET epi. Other operations include removing the first dielectric liner from the first contact opening, and forming a first contact in the first contact opening and a second contact in the second contact opening.
The above summary is not intended to describe each illustrated embodiment or every implementation of the present disclosure.
The drawings included in the present application are incorporated into, and form part of, the specification. They illustrate embodiments of the present disclosure and, along with the description, serve to explain the principles of the disclosure. The drawings are only illustrative of certain embodiments and do not limit the disclosure.
While the disclosure is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the disclosure to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure.
Aspects of the present disclosure relate generally to complementary metal oxide semiconductor (CMOS) structures and methods of forming the same. More particularly, the present disclosure provides a method of forming CMOS having low contact resistance. While the present disclosure is not necessarily limited to such applications, various aspects of the disclosure can be appreciated through a discussion of various examples using this context.
Embodiments of the present disclosure relate to an IC having a CMOS transistor comprising a p-type field-effect transistor (pFET) and an n-type field-effect transistor (nFET). The pFET and the nFET each have a channel region, and a source and a drain region formed in a first semiconductor region. Embodiments of the present disclosure generally relates to various methods of reducing the contact resistance between a metal silicide material and an epi semiconductor material, and the resulting semiconductor devices. Moreover, as will be readily apparent to those skilled in the art upon a complete reading of the present application, the present method is applicable to a variety of devices, including, but not limited to, logic devices, memory devices, etc. The methods and devices disclosed herein may be employed in manufacturing products using CMOS, etc., and they may be employed in manufacturing a variety of different devices, e.g., memory devices, logic devices, application-specific integrated circuits (ASICs), etc. As will be further appreciated by those skilled in the art, the disclosure can be employed in forming IC products using planar transistor devices or a variety of so-called three-dimensional (3D) devices, such as finFETs. For example, although the figures of the disclosure include a finFET, the disclosure applies to all devices, including nanosheet, nanowire, and vertical transport field effect transistor (VTFET), for example.
As is known, a finFET is a transistor built around a thin strip of semiconductor material generally referred to as the fin. The transistor includes the standard FET nodes, including a gate, a gate dielectric, a source region, and a drain region. The conductive channel of the device resides on the outer sides of the fin beneath the gate dielectric. Specifically, current runs along both sidewalls of the fin (sides perpendicular to the substrate surface) as well as along the top of the fin (side parallel to the substrate surface). Because the conductive channel of such configurations essentially resides along the three different outer, planar regions of the fin, such a finFET design is sometimes referred to as a tri-gate finFET. Other types of finFET configurations are also available, such as double-gate finFETs, in which the conductive channel principally resides only along the two sidewalls of the fin (and not along the top of the fin).
Increased performance of circuit devices including transistors, diodes, resistors, capacitors, and other passive and active electronic devices formed on a semiconductor substrate is typically considered during design, manufacture, and operation of those devices. For example, during design and manufacture or forming of, metal oxide semiconductor (MOS) transistor semiconductor devices, such as those used in a CMOS, it is often useful to reduce the parasitic resistance associated with contacts otherwise known as external resistance (Rext). Contact resistance (Rcontact) has become an Rext bottleneck as gate pitch is scaled in the transistor, and contact area becomes smaller. To reduce the Rcontact at a given contact area, contact resistivity may be reduced (e.g., below 2×10−9 Ωcm2).
In order to reduce contact resistivity, it has been found that it can be useful to have a relatively high percentage germanium (Ge) epi on a pFET material in a CMOS structure. However, forming a high percentage of Ge over pFET S/D epi in an early stage of the device fabrication can result in easy oxidation and Ge diffusion during subsequent processing steps with high thermal budget, such as a high-k dielectric reliability anneal. Forming a late trench Ge epi during contact formation can avoid processing steps with high thermal budget, on the other hand, and can have other drawbacks. For example, using a separate mask for the nFET in the CMOS structure during application of the trench Ge epi of Ge on the pFET of the CMOS late in the manufacturing process can be relatively costly. Also, it may be challenging to remove a protecting liner once the liner is deposited at the sidewalls of a contact trench. More specifically, isotropic liner removal can damage spacer and gate corners.
One feature and advantage of disclosed structures and processes is that formation of the trench Ge epi for only pFET devices for a CMOS application, using the disclosed process, may reduce costs in comparison to current solutions. Another feature or advantage of the disclosed process is that the process can be applicable to many technologies, such as finFET, nanosheet and VTFET, for example. Yet another feature or advantage of the disclosed process and structure is that contact resistance can be reduced.
For purposes of this disclosure, reference will be made to an illustrative process flow wherein for forming a single CMOS transistor device (“CMOS device”) 100. Of course, the disclosure herein should not be considered to be limited to the illustrative examples depicted and described herein. With reference to the attached figures, various illustrative embodiments of the methods and devices disclosed herein will now be described in more detail.
Turning to the subsequent figures,
The various layers of material depicted in the following drawings can be formed by any of a variety of different known techniques, e.g., a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a thermal growth process, spin-coating techniques, reactive-ion etching (RIE), etc.
The terms “epitaxially,” “epitaxy,” “epi,” etc., carry their customary usage: meaning the single crystal lattice structure carries across an interface. Typically, a single crystal material forms a platform onto which another single crystal material, with matching crystalline characteristics, can be deposited by one of several techniques known in the art. Such techniques are, for instance, molecular beam epitaxy (MBE), or various types of CVD.
As shown in the Y-Y view, the fins 104 extend through the STI regions 106. The STI regions 106 can be formed using conventional techniques, such as by performing additional patterning steps to remove any unwanted fins, then depositing dielectric material onto the trenches followed by planarization and recessing to form the STI regions 106. The STI regions 106 can be made from any suitable insulating material, such as SiO2 or a thin SiN liner followed by SiO2.
A plurality of gate stacks 108 (see X-X view) can be formed over a number of surfaces of the fins 104 to form gates. Three (3) gate stacks 108 are shown in the figures. In the operation shown in
Turning to
A mask layer 124 (e.g., organic planarization layer (OPL)) 124 can be deposited and patterned, such that the patterning layer 122 in the pFET region is covered by the mask layer 124, and the patterning layer 122 in the nFET region 120 is exposed. The mask layer or OPL 124 can be deposited using a spin-on deposition process, for example. It is useful for the mask layer 124 to have certain properties. For example, the mask layer 124 is sacrificial, so it can be a material that can be removed easily without damaging the surrounding structure. Further, the mask layer 124 can have useful “gap-fill” properties so that the mask layer 124 can fill trenches. Additionally, the mask layer 124 can be self-planarizing. Also, the mask layer 124 can be composed of a material that is easily etch-selective relative to the patterning layer 122.
Next, in
Next, in
In
After the forming the pFET epi on the substrate operation at 210, the process 200 can further include additional operations. For example, after the forming the first contact and the second contact operation, the second dielectric liner wraps around a first portion of the pFET epi and the trench epi is located on a second portion of the pFET epi that is adjacent the first contact, and both the first and second dielectric liners wrap around a first portion of the nFET epi and a second portion of the nFET epi is adjacent the second contact.
The process 200 can include another operation of forming at least one gate stack on the substrate, wherein the gate stack includes a dummy gate structure, a gate cap layer and sidewall spacers on both sides of the dummy gate structure and the hard mask cap. Yet another possible operation can be removing the at least one gate stack and replacing each gate stack with a replacement gate stack that includes a high K metal gate and an SAC cap. A further possible operation can be etching a pattern of trenches in the substrate that is configured to provide shallow trench isolation.
For purposes of description herein, the terms “upper,” “lower,” “top,” “bottom,” “left,” “right,” “rear,” “front,” “vertical,” “horizontal,” and derivatives thereof shall relate to the devices as oriented in the figures. However, it is to be understood that the devices can assume various alternative orientations and step sequences, except where expressly specified to the contrary. Moreover, as used herein, the word “adjacent” is to be given a broad interpretation and should be interpreted to cover situations where one feature actually contacts another feature or is in close proximity to that other feature.
It is also to be understood that the specific devices and processes illustrated in the attached drawings, and described in the following disclosure, are simply exemplary embodiments of the inventive concepts defined in the appended claims. Hence, other physical characteristics relating to the embodiments disclosed herein are not to be considered as limiting, unless the claims expressly state otherwise.
For purposes of this description, certain aspects, advantages, and novel features of the embodiments of this disclosure are described herein. The disclosed processes, and systems should not be construed as being limiting in any way. Instead, the present disclosure is directed toward all novel and nonobvious features and aspects of the various disclosed embodiments, alone and in various combinations and sub-combinations with one another. The processes, and systems are not limited to any specific aspect or feature or combination thereof, nor do the disclosed embodiments require that any one or more specific advantages be present, or problems be solved.
Although the operations of some of the disclosed embodiments are described in a particular, sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangement, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially can in some cases be rearranged or performed concurrently. Moreover, for the sake of simplicity, the attached figures may not show the various ways in which the disclosed processes can be used in conjunction with other processes. Additionally, the description sometimes uses terms like “provide” or “achieve” to describe the disclosed processes. These terms are high-level abstractions of the actual operations that are performed. The actual operations that correspond to these terms can vary depending on the particular implementation and are readily discernible by one of ordinary skill in the art.
As used in this application and in the claims, the singular forms “a,” “an,” and “the” include the plural forms unless the context clearly dictates otherwise. Additionally, the term “includes” means “comprises.”
The descriptions of the various embodiments of the present disclosure have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
