METHOD AND STRUCTURE FOR METAL GATE BOUNDARY ISOLATION

Abstract

A semiconductor structure includes a first transistor adjacent a second transistor. The first transistor includes a first gate metal layer over a gate dielectric layer, and the second transistor includes a second gate metal layer over the gate dielectric layer. The first and the second gate metal layers include different materials. The semiconductor structure further includes a first barrier disposed horizontally between the first gate metal layer and the second gate metal layer. One of the first and the second gate metal layers includes aluminum, and the first barrier has low permeability for aluminum. A bottom surface of the first gate metal layer is directly on a top surface of the first barrier.

Description

Claims

1. A semiconductor structure, comprising: a first transistor adjacent a second transistor, wherein the first transistor includes a first gate metal layer over a gate dielectric layer, and the second transistor includes a second gate metal layer over the gate dielectric layer, wherein the first and the second gate metal layers include different materials; anda first barrier disposed horizontally between the first gate metal layer and the second gate metal layer, wherein one of the first and the second gate metal layers includes aluminum, and the first barrier has low permeability for aluminum, wherein a bottom surface of the second gate metal layer is directly on a top surface of the first barrier.

2. The semiconductor structure of claim 1, wherein the first barrier includes oxygen and a material included in the first gate metal layer.

3. The semiconductor structure of claim 2, wherein the first barrier includes TiO, TiON, TiAlO, WO, WCO, WCNO, RuO, WON, TaO, TaCO, TaAlO TaTiO, TiOH, WOH, AlOH, TaOH, or a combination thereof.

4. The semiconductor structure of claim 1, wherein the first barrier is a tungsten-containing layer.

5. The semiconductor structure of claim 4, wherein the first barrier includes W, WC, WCN, WCI, WF, WB, WS, or a combination thereof.

6. The semiconductor structure of claim 1, wherein the first barrier includes fluorine and a material included in the first gate metal layer.

7. The semiconductor structure of claim 6, wherein the first barrier includes W, WC, WCN, WCI, WF, WB, WS, or a combination thereof.

8. The semiconductor structure of claim 1, wherein an extending portion of the second gate metal layer is disposed over the first gate metal layer.

9. The semiconductor structure of claim 8, further comprising a second barrier disposed vertically between the extending portion of the second gate metal layer and the first gate metal layer.

10. The semiconductor structure of claim 9, wherein the first and the second barriers include different materials.

11. The semiconductor structure of claim 10, wherein the first barrier includes oxygen, and the second barrier is free of oxygen.

12. A semiconductor structure, comprising: a first transistor having a first gate metal layer directly on a gate dielectric layer, a first barrier layer directly on the first gate metal layer, and a second gate metal layer directly on the first barrier layer;a second transistor having the second gate metal layer directly on the gate dielectric layer, wherein the first and the second gate metal layers include different materials; anda second barrier layer disposed horizontally between the first gate metal layer and the second gate metal layer, wherein one of the first and the second gate metal layers includes aluminum, and the first and second barriers have low permeability for aluminum.

13. The semiconductor structure of claim 12, further comprising a bulk metal layer over the first and the second gate metal layers.

14. The semiconductor structure of claim 12, wherein both the first and the second barrier layers include tungsten or fluorine.

15. The semiconductor structure of claim 12, wherein the first barrier layer includes tungsten, and the second barrier layer includes fluorine.

16. The semiconductor structure of claim 12, wherein the first barrier layer includes fluorine, and the second barrier layer includes tungsten.

17. A method comprising: depositing a gate dielectric layer over semiconductor channel layers;depositing a work-function (WF) metal layer over the gate dielectric layer;forming an etch mask covering a second portion of the WF metal layer and having an opening above a first portion of the WF metal layer;etching the WF metal layer through the etch mask, thereby removing the first portion of the WF metal layer while keeping the second portion of the WF metal layer, wherein a sidewall of the second portion of the WF metal layer is exposed after the etching;forming a first barrier on the sidewall of the second portion of the WF metal layer; anddepositing a gate metal layer over the gate dielectric layer, the first barrier, and the second portion of the WF metal layer, wherein the first barrier is disposed between the gate dielectric layer and the gate metal layer.

18. The method of claim 17, wherein the WF metal layer is a first WF metal layer, the gate metal layer is a second WF metal layer, and the first and second WF metal layers have different materials,wherein one of the first and second WF metal layers include aluminum.

19. The method of claim 17, further comprising: after forming the first barrier, removing the etch mask to expose a top surface of the WF metal layer; andforming a second barrier on the exposed top surface of the WF metal layer.

20. The method of claim 17, further comprising: before forming the first barrier, removing the etch mask to expose a top surface of the WF metal layer,wherein the forming of the first barrier includes forming a second barrier on the exposed top surface of the WF metal layer.