Claims
- 1. A method of processing a semiconductor wafer, comprising:
(a) measuring a CD of an isolated pattern of a patterned layer formed on an underlying layer on the wafer; (b) measuring a CD of a dense pattern that is one of a plurality of patterns of the patterned layer disposed proximal to each other; (c) selecting a first set of process parameter values for a first process to be performed on the wafer, based on the measurements of the isolated pattern CD and the dense pattern CD; and (d) performing the first process on the wafer at a processing tool using the first set of process parameter values.
- 2. The method of claim 1, comprising optically measuring the CDs of the isolated and dense patterns.
- 3. The method of claim 1, wherein the first process is an etch process for forming a structure in the underlying layer.
- 4. The method of claim 1, comprising forming the patterned layer by photolithographically forming a photoresist mask having a plurality of photoresist patterns, wherein the measuring steps comprise measuring CDs of the photoresist patterns.
- 5. The method of claim 4, wherein the first process is a photoresist trim process, and the first set of process parameter values includes a trim time.
- 6. The method of claim 5, comprising selecting the trim time based on the measured CDs of the isolated and dense photoresist patterns and further based on a desired post-trim microloading, wherein the microloading is a difference between a trimmed isolated photoresist pattern CD and a trimmed dense photoresist pattern CD.
- 7. The method of claim 6, comprising developing a mathematical expression wherein the trim time is a function of the isolated photoresist pattern CD; the dense photoresist pattern CD; a difference between the isolated photoresist pattern CD and a desired post-trim isolated photoresist pattern CD; and a difference between the dense photoresist pattern CD and the desired post-trim dense photoresist pattern CD.
- 8. The method of claim 6, further comprising etching the underlying layer using the trimmed photoresist patterns as a mask.
- 9. The method of claim 8, comprising performing the trim process and the etch process on the wafer at the processing tool.
- 10. The method of claim 8, comprising cleaning the wafer after performing the etch process.
- 11. The method of claim 8, comprising measuring a CD of a structure formed in the underlying layer by the etch process, and selecting a second set of process parameter values for a subsequently processed wafer using the CD measurement of the structure.
- 12. The method of claim 3, comprising measuring a CD of the structure formed in the underlying layer by the first process, and selecting a second set of process parameter values for a subsequently processed wafer using the CD measurement of the structure.
- 13. The method of claim 8, comprising choosing an etch recipe for the underlying layer etch process based on the measured CDs of the isolated and dense photoresist patterns.
- 14. The method of claim 6, wherein the photoresist mask comprises a plurality of the isolated and dense photoresist patterns, the method comprising:
measuring the CD of the plurality of the isolated and dense photoresist patterns; averaging the CD measurements; and using the average CD measurements to select the trim time.
- 15. The method of claim 6, comprising measuring a sidewall profile of the isolated photoresist pattern and a sidewall profile of the dense photoresist pattern, and selecting the trim time further based on the measured sidewall profiles.
- 16. The method of claim 6, comprising determining a thickness of the photoresist layer, and selecting the trim time further based on the photoresist layer thickness.
- 17. The method of claim 16, comprising determining a thickness of the underlying layer, and selecting the trim time further based on the underlying layer thickness.
- 18. The method of claim 6, comprising determining a percentage of open area of the photoresist layer wherein no photoresist patterns are located, and selecting the trim time further based on the open area percentage.
- 19. The method of claim 8, comprising etching the underlying layer using a set of etch parameters to form an isolated pattern in the underlying layer corresponding to the isolated photoresist pattern and having a CD, and a dense pattern in the underlying layer corresponding to the dense photoresist pattern and having a CD;
wherein the etch parameters are selected based on a desired post-etch microloading, wherein the microloading is a difference between the post-etch isolated pattern CD and the post-etch dense pattern CD.
- 20. The method of claim 19, comprising determining a percentage of open area of the photoresist layer wherein no photoresist patterns are located, and selecting the etch parameters further based on the open area percentage to achieve the desired post-etch microloading.
- 21. The method of claim 1, wherein the isolated and dense patterns comprise lines, each having a line width;
wherein the isolated pattern is spaced at least about 5 line widths from the closest pattern on the patterned layer; and wherein the dense pattern is spaced from about 1 to about 3 line widths from the closest pattern on the patterned layer.
- 22. The method of claim 6, wherein the first set of process parameter values includes a source power, comprising selecting the source power based on the desired post-trim microloading.
- 23. An apparatus for processing a semiconductor wafer, comprising:
a measuring tool for measuring a CD of an isolated pattern on a patterned layer formed on an underlying layer on the wafer, and for measuring a CD of a dense pattern that is one of a plurality of patterns of the patterned layer disposed poximal to each other; a processing tool for performing a process on the wafer using a first set of process parameter values; and a processor configured to select the first set of process parameter values based on the measurements of the isolated pattern CD and the dense pattern CD.
- 24. The apparatus of claim 23, wherein the measurement tool comprises an optical measuring tool.
- 25. The apparatus of claim 24, wherein the optical measuring tool is for employing scatterometry or reflectometry.
- 26. The apparatus of claim 23, wherein the processing tool is an etcher.
- 27. The apparatus of claim 26, wherein the patterned layer is a photoresist mask having photoresist patterns, and the measuring tool is for measuring CDs of the photoresist patterns.
- 28. The apparatus of claim 27, wherein the etcher is for performing a photoresist trim process on the photoresist mask, and one of the first set of process parameters selected by the processor is a photoresist trim time.
- 29. The apparatus of claim 28, wherein the processor is configured to select the trim time based on the measured CDs of the isolated and dense photoresist patterns and further based on a desired post-trim microloading, wherein the microloading is a difference between a trimmed isolated photoresist pattern CD and trimmed dense photoresist pattern CD.
- 30. The apparatus of claim 29, wherein the processor is configured to select the trim time using a mathematical expression wherein the trim time is a function of the isolated photoresist pattern CD; the dense photoresist pattern CD; a difference between the isolated photoresist pattern CD and a desired post-trim isolated photoresist pattern CD; and a difference between the dense photoresist pattern CD and the desired post-trim dense photoresist pattern CD.
- 31. The apparatus of claim 29, wherein the etcher is for etching the underlying layer using the trimmed photoresist patterns as a mask.
- 32. The apparatus of claim 31, further comprising a stripping tool for removing residue from the wafer after etching the underlying layer.
- 33. The apparatus of claim 31, wherein the measuring tool is for measuring a CD of a structure formed in the underlying layer by the etch process, and the processor is configured to select a second set of process parameter values for a subsequently processed wafer using the CD measurement of the structure.
- 34. The apparatus of claim 26, wherein the etcher is for performing the first process to form a structure in the underlying layer, wherein the measuring tool is for measuring a CD of the structure formed in the underlying layer, and the processor is configured to select a second set of process parameter values for a subsequently processed wafer using the CD measurement of the structure.
- 35. The apparatus of claim 31, wherein the processor is configured to choose an etch recipe for the underlying layer etch process based on the measured CDs of the isolated and dense photoresist patterns.
- 36. The apparatus of claim 29, wherein the photoresist mask comprises a plurality of the isolated and dense photoresist patterns, wherein the measuring tool is for measuring the CD of the plurality of the isolated and dense photoresist patterns, and the processor is configured to:
average the CD and profile measurements; and use the average CD and profile measurements to select the trim time.
- 37. The apparatus of claim 29, wherein the measuring tool is for measuring a sidewall profile of the isolated photoresist pattern and a sidewsall profile of the dense photoresist pattern, and the processor is configured to select the trim time further based on the measured sidewall profiles.
- 38. The apparatus of claim 29, wherein the measuring tool is for determining a thickness of the photoresist layer, and the processor is configured to select the trim time further based on the photoresist layer thickness.
- 39. The apparatus of claim 29, wherein the mesasuring tool is for determining a thickness of the underlying layer, and the processor is configured to select the trim time further based on the underlying layer thickness.
- 40. The apparatus of claim 29, wherein the processor is further configured to determine a percentage of open area of the photoresist layer wherein no photoresist patterns are located, and select the trim time further based on the open area percentage.
- 41. The apparatus of claim 31, wherein the etcher is for etching the underlying layer using a set of etch parameters to form an isolated pattern in the underlying layer corresponding to the isolated photoresist pattern and having a CD, and a dense pattern in the underlying layer corresponding to the dense photoresist pattern and having a CD;
wherein the processor is further configured to select the etch parameters based on a desired post-etch microloading, wherein the microloading is a difference between the post-etch isolated pattern CD and the post-etch dense pattern CD.
- 42. The apparatus of claim 34, wherein the processor is further configured to determine a percentage of open area of the photoresist layer wherein no photoresist patterns are located, and select the etch parameters further based on the open area percentage to achieve the desired post-etch microloading.
- 43. The apparatus of claim 29, wherein the first set of process parameter values includes a source power, and the processor is further configured to select the source power based on the desired post-trim microloading,
- 44. An apparatus for processing a semiconductor wafer, comprising:
a measuring tool for measuring a CD of an isolated pattern on a patterned layer formed on an underlying layer on the wafer, and for measuring a CD of a dense pattern that is one of a plurality of patterns of the patterned layer disposed proximal to each other; a processing tool for performing a process on the wafer using a first set of process parameter values; a processor configured to select the first set of process parameter values based on the measurements of the isolated pattern CD and the dense pattern CD; a transfer mechanism for transferring the wafer between the measuring tool and the processing tool; and a chamber for enclosing the transfer mechanism and allowing communication between the transfer mechanism, the measuring tool and the processing tool in a clean environment.
- 45. The apparatus of claim 44, wherein the measurement tool is an optical measurement tool.
- 46. The apparatus of claim 45, wherein the measurement tool employs scatterometry or reflectometry.
- 47. The apparatus of claim 44, wherein the chamber comprises:
a mainframe for mounting a plurality of processing tools, including the first processing tool; a factory interface for mounting a wafer cassette; and a transfer chamber between and in communication with the mainframe and the factory interface; wherein the transfer mechanism comprises a first robot for transferring the wafer between the measurement tool, the transfer chamber and the wafer cassette, and a second robot for transferring the wafer between the transfer chamber and the processing tool; wherein the measurement tool is mounted on the factory interface or the mainframe.
- 48. The apparatus of claim 44, wherein the process tool comprises an etcher.
- 49. The apparatus of claim 48, wherein the processor is configured to:
control the transfer mechanism to transfer the wafer from the etcher to the measuring tool after the process is performed on the wafer; and control the measuring tool to measure the CD of a structure formed in the underlying layer at the etcher.
- 50. The apparatus of claim 47, wherein the process tool comprises an etcher, the process is a photoresist trim process, the first process parameter values comprise a photoresist trim recipe, and the processor is configured to control the etcher to perform an etch process on the wafer after the photoresist trim process is performed on the wafer.
- 51. The apparatus of claim 50, wherein the processor is configured to:
control the transfer mechanism to transfer the wafer from the etcher to the measuring tool after the etch process is performed on the wafer; and control the measuring tool to measure the CD of a structure formed in the underlying layer during the etch process.
- 52. The apparatus of claim 50, further comprising an ashing strip processing unit mounted to the mainframe or the factory interface for removing residue from the wafer, wherein the processor is configured to control the transfer mechanism to transfer the wafer to the ashing strip processing unit after the etch process is performed on the wafer.
- 53. The apparatus of claim 52, further comprising a cleaning chamber mounted to the factory interface for cleaning the wafer, wherein the processor is configured to control the transfer mechanism to transfer the wafer to the cleaning chamber after the ashing strip process is performed on the wafer at the ashing strip processing unit.
- 54. The method of claim 1, comprising measuring the CDs of the isolated and dense patterns using a CDSEM.
- 55. The method of claim 1, comprising measuring the CDs of the isolated and dense patterns using an AFM.
- 56. The apparatus of claim 23, wherein the measurement tool comprises a CDSEM.
- 57. The apparatus of claim 23, wherein the measurement tool comprises an AFM.
- 58. The apparatus of claim 44, wherein the measurement tool comprises a CDSEM.
- 59. The apparatus of claim 44, wherein the measurement tool comprises an AFM.
RELATED APPLICATIONS
[0001] This application is a continuation-in-part of U.S. application Ser. No. 10/238,453 (Attorney Docket No. 49959-301), filed Sep. 9, 2002. This application is based on and claims priority from U.S. Provisional Application Serial No. 60/390,480, filed Jun. 20, 2002.
Provisional Applications (1)
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Number |
Date |
Country |
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60390480 |
Jun 2002 |
US |
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
10238453 |
Sep 2002 |
US |
Child |
10464479 |
Jun 2003 |
US |