BRIEF DESCRIPTIONS OF THE DRAWINGS
FIG. 1 is a schematic diagram of a configuration and operation of a mask blank defect inspection system according to a first embodiment of the present invention;
FIG. 2A is a diagram for describing a concept of a defect inspection method in the mask blank defect inspection system according to the first embodiment of the present invention;
FIG. 2B is a diagram for describing the concept of the defect inspection method in the mask blank defect inspection system according to the first embodiment of the present invention;
FIG. 2C is a diagram for describing the concept of the defect inspection method in the mask blank defect inspection system according to the first embodiment of the present invention;
FIG. 3 is a characteristic diagram depicting characteristics of defect signals in the mask blank defect inspection system according to the first embodiment of the present invention;
FIG. 4 is a process flow diagram of an implementing process of a defect inspection method in the mask blank defect inspection system and method according to the first embodiment of the present invention;
FIG. 5 is a process flow diagram of an implementing process of a defect inspection method in a mask blank defect inspection system and method according to a second embodiment of the present invention;
FIG. 6 is a process flow diagram of an implementing process of a defect inspection method in a mask blank defect inspection system and method according to a third embodiment of the present invention;
FIG. 7A is a sectional view of main parts that depicts a semiconductor device manufacturing process according to a fourth embodiment of the present invention;
FIG. 7B is a sectional view of main parts that depicts the semiconductor device manufacturing process according to the fourth embodiment of the present invention;
FIG. 7C is a sectional view of main parts that depicts the semiconductor device manufacturing process according to the fourth embodiment of the present invention;
FIG. 7D is a sectional view of main parts that depicts the semiconductor device manufacturing process according to the fourth embodiment of the present invention;
FIG. 7E is a sectional view of main parts that depicts the semiconductor device manufacturing process according to the fourth embodiment of the present invention; and
FIG. 7F is a sectional view of main parts that depicts the semiconductor device manufacturing process according to the fourth embodiment of the present invention.