Patent Application
20060216875
This application is based upon and claims the benefit of priority from prior Japanese Patent Application P2005-092751 filed on Mar. 28, 2005; the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates to a method for annealing a semiconductor device, and particularly to a method for annealing and a method for manufacturing a semiconductor device using a high intensity light source.
2. Description of the Related Art
It is possible to achieve improvements in performance of a semiconductor device having a large scale integration (LSI) by increasing integration, or to put it more plainly, by miniaturization of the elements that build up a semiconductor device. Thus, LSIs are of increasingly large-scale while miniaturization of elements, such as metal-oxide-semiconductor (MOS) transistors, is being taken to a whole new level. Along with the miniaturization of elements, parasitic resistance and short channel effects on MOS transistors and the like, are increasing. Thus, there is increased importance placed on the formation of low resistance layers and shallow pn junctions.
For forming a shallow pn junction with a thickness of or below twenty nm, a thin impurity doped region is formed using an ion implantation in a semiconductor substrate with low acceleration energy. The impurities doped in the semiconductor substrate are activated by annealing, thus forming a shallow impurity diffusion region. In order to decrease layer resistance of an impurity diffusion region, it is necessary to perform activation annealing of the impurities at a high temperature.
However, the diffusion coefficients of p-type impurity such as boron (B), and n-type impurity such as phosphorus (P) or arsenic (As), in the crystal of the silicon (Si) substrate, are large. In the processing time needed to perform rapid thermal annealing (RTA) using current halogen lamps, impurities diffuse to both the interior and exterior of a semiconductor substrate. As a result, it is impossible to form a shallow impurity diffusion region having a high concentration of impurities on the semiconductor substrate. Also, it becomes impossible to activate a high concentration of impurities if the temperature of the RTA process is decreased in order to control the diffusion of the impurities. Because of such difficulties, it is difficult to form a shallow impurity diffusion region having low resistance and a high concentration of activated impurities.
Recently, a pulse light annealing method by the use of a pulse light source, such as a flashlamp and a YAG laser, which can instantly supply the energy essential to impurity activation, is being tested as a solution to the RTA problem. A xenon (Xe) flashlamp has a quartz glass tube filled with Xe gas, in which electrical charges stored in capacitors and the like, are instantaneously discharged. As a result, it is possible to emit a high intensity white light within a range of several hundred μs to several hundred ms. It is possible to attain the heat energy required for impurity activation in the instantaneous heating of a semiconductor substrate absorbing flashlamp light. Therefore, it is possible to activate a high concentration of impurities while leaving the concentration profile of the impurities, implanted into the semiconductor substrate, virtually unchanged.
However, on a semiconductor substrate, fine patterns of different materials such as polycrystalline silicon (poly-Si), silicon nitride (Si3N4), and silicon oxide (SiO2) are formed in different pattern densities. Reflectivity for a flashlamp light varies depending on the pattern density of the fine patterns. For example, as the pattern density increases, the reflectivity is decreased to increase heating efficiency of the flashlamp light. If the semiconductor substrate is irradiated and sufficiently heated with the flashlamp light in order to activate impurities implanted by ion implantation, a heating temperature may be elevated in a region having the high pattern density. Thus, damage or crystal defects, such as melting, cracks, a dislocation, a stacking fault, and a slip, are induced in the semiconductor substrate.
For example, it is possible to decrease damage to the semiconductor substrate having the fine patterns by increasing an emission time of the flashlamp so as to decrease an irradiation energy density thereof. However, since the reflectivity depending on the pattern density does not change, the dependence of the heating temperature on the pattern density may still remain due to a difference in heating efficiency of the flashlamp light. As a result, an activation rate of the implanted impurities varies. As mentioned above, a current flashlamp annealing process has a problem that a variation of characteristics of elements may be induced to narrow a process window in a manufacturing process of a semiconductor device.
In a manufacturing method of a semiconductor device, a technique of forming a light absorbing film on a surface of an insulating film has been disclosed (refer to Japanese Unexamined Patent Application No. 2000-138177). However, the light absorbing film formed on the surface of the insulating film generates heat by absorbing light, and a semiconductor substrate does not generate heat. Therefore, it is difficult to instantly and efficiently increase the temperature of the semiconductor substrate.
A first aspect of the present invention inheres in a method for annealing by light irradiation including depositing a translucent film with a predetermined thickness on a semiconductor substrate, the translucent film having a refractive index smaller than the refractive index of the semiconductor substrate, the thickness defined by a peak wavelength of the light and the refractive index of the translucent film; heating the semiconductor substrate in a temperature range of about 300° C. to about 600° C.; and heating a surface of the semiconductor substrate with the light, the light having a pulse width of about 0.1 ms to about 100 ms.
A second aspect of the present invention inheres in a method for manufacturing a semiconductor device including forming a gate insulating film on a semiconductor substrate; forming a gate electrode on the gate insulating film; implanting first impurity ions into the semiconductor substrate using the gate electrode as a mask; depositing a translucent film with a predetermined thickness on the semiconductor substrate, the translucent film having a refractive index smaller than the refractive index of the semiconductor substrate; heating the semiconductor substrate in a temperature range of about 300° C. to about 600° C.; and heating a surface of the semiconductor substrate with a light so as to activate the first impurity ions, the light having a pulse width of about 0.1 ms to about 100 ms; wherein the thickness of the translucent film is defined by a peak wavelength of the light and the refractive index of the translucent film.
FIGS. 4 to 7 are cross sectional views showing an example of a manufacturing process for a semiconductor device used in a description of an annealing method according to the embodiment of the present invention.
FIGS. 24 to 31 are cross section views showing an example of a manufacturing method for a semiconductor device according to the embodiment of the present invention.
Various embodiments of the present invention will be described with reference to the accompanying drawings. It is to be noted that the same or similar reference numerals are applied to the same or similar parts and elements throughout the drawings, and the description of the same or similar parts and elements will be omitted or simplified.
In an embodiment of the present invention, description will be given using an activation annealing process of the impurities implanted by ion implantation. For instance, P or As are used as n-type impurities, and B is used as p-type impurity. However, the annealing process according to the embodiment of the present invention is not limited to an impurity activation annealing process. It is obvious that annealing processes for applications such as an insulating film formation of an oxide film and a nitride film, and recrystallization of damaged layers and the like can be put into use.
An annealing apparatus according to the embodiment of the present invention, as shown in
The processing chamber 30 is fabricated from a metal such as stainless steel. The susceptor 31, on which the semiconductor substrate 1 is placed, is located on the bottom of the processing chamber 30. Aluminum nitride (AlN), ceramics, quartz glass, and the like, may be used as the susceptor 31. Also, the susceptor 31 may be stainless steel with a surface protected by AlN, ceramics, or quartz glass. A heat source 32 used to heat the semiconductor substrate 1 is provided in the susceptor 31. A hot plate, an embedded metallic heater of nichrome wire, a heating lamp such as a halogen lamp, are used as the heat source 32. Temperature of the heat source 32 is controlled by a control system (not shown) provided outside of the processing chamber 30. A gas supply system 34 including a gas source that supplies an inert gas during the annealing of the semiconductor substrate 1 is connected to the intake pipe 35.
The light source 38, such as a flashlamp, irradiates a pulsed light through the transparent, synthetic quartz window 37 and the like, onto the surface of the semiconductor substrate 1, to heat the semiconductor substrate 1. The power supply 39, such as a pulse power supply, drives the light source 38 at an extremely short pulse width. The full width at half maximum (FWHM) of the pulse is about 0.1 ms to about 100 ms. The power supply 39 controls the irradiation energy and pulse width of the light beamed from the light source 38. The energy density of the light source 38 is within the range of about 5 J/cm2 to about 100 J/cm2. The transparent window 37 transmits the light from the light source 38 to the semiconductor substrate 1 while maintaining an airtight barrier separating the processing chamber 30 from the light source 38.
On the annealing process used to activate impurities implanted by ion implantation, when irradiating the semiconductor substrate with an emitted light having a FWHM less than about 0.1 ms from the light source 38, an irradiation energy density of the emitted light for heating to an activation annealing temperature is increased so that the thermal stress induced in the semiconductor substrate 1 is increased. Further, when the FWHM of the emitted light exceeds 100 ms, the diffusion of the implanted impurities is enhanced.
In activation annealing, the semiconductor substrate 1, placed on top of the susceptor 31, is preheated by the heating source 32 within a temperature range of about 300° C. to about 600° C., and desirably at about 400° C. to about 500° C. The preheating is set to a temperature that does not cause damage to the semiconductor substrate 1. If a preheating temperature is less than about 300° C., an irradiation energy density of the light source 38 for heating to an activation annealing temperature is increased. As a result, crystal defects, such as slips and dislocations, which are caused by thermal stress, are easily generated in the semiconductor substrate 1. Further, if the preheating temperature exceeds 600° C., the implanted impurities may be diffused during the preheating.
Moreover, a desirable heating rate of the preheating is less than about 20° C./s. If the heating rate exceeds 20° C./s, the semiconductor substrate 1 is warped, deformed and easily damaged.
Furthermore, in activation annealing, a light source 38 emits a light to irradiate the semiconductor substrate 1 with only one pulsed light beam. If a FWHM of the pulsed light beam is about 2 ms, an irradiation energy density is, for example, within a range from about 28 J/cm2 to about 36 J/cm2 and a range from about 18 J/cm2 to about 26 J/cm2 at the preheating temperature of about 300° C. and about 600° C., respectively. Further, the irradiation energy density is within a range from about 20 J/cm2 to about 33 J/cm2 at the preheating temperature of about 450° C. In the description of the embodiment of the present invention, activation annealing conditions are a preheating temperature of about 450° C. and an irradiation energy density of about 25 J/cm2, for example
As shown in
In the embodiment of the present invention, it is possible to activate the implanted impurities in the semiconductor substrate 1 at a high temperature of about 900° C. or more in an extremely short period of time. As a result, impurity diffusion arising from activation annealing can be limited to a depth of about 5 nm or less. Thus, it is possible to form a shallow pn junction.
The luminous spectrum of the Xe flashlamp of the light source 38 is close to that of white light, and has a main peak intensity wavelength from about 400 nm to about 500 nm, as shown in
For example, a plurality of regions each having a different pattern density of element patterns are formed on the surface of the semiconductor substrate 1. Since a reflectivity for the flashlamp light depends on the pattern density, the semiconductor substrate 1 is not uniformly heated. In particular, in a region where the element patterns are densely arranged, reflectivity for the flashlamp light is smaller, so as to heat to a higher temperature. In this way, when activation annealing is performed on the semiconductor substrate 1 where the pattern density is not uniform, by use of the light source 38, implanted impurities are not uniformly activated, and the element characteristics vary. Further, due to crystal defects resulting from a thermal stress inside the semiconductor substrate 1, the semiconductor substrate 1 is easily damaged.
Next, an annealing method according to the embodiment of the present invention will be described using a manufacturing process of a p-MOS transistor as an example. Further, the semiconductor device is not limited to a p-MOS transistor. A semiconductor device such as an n-MOS transistor and a complementary MOS (CMOS) transistor, for instance, are also within the scope of the invention. Additionally, a metal-insulator-semiconductor (MIS) transistor using an insulating film such as a silicon oxynitride (SiON) film, a Si3N4 film, or a composite insulating film between a SiO2 film and a SiON film, a Si3N4 film, a various metal oxide film or the like, instead of the SiO2 film, is also within the scope of the invention.
As shown in
As shown in
As shown in
As shown in
In an annealing method according to an embodiment of the present invention, the flashlamp light emitted from the light source 38 is irradiated from above the surface of the semiconductor substrate 1. Then, the flashlamp light is transmitted through a translucent film 14 from an ambient gas in the processing chamber 30, and absorbed by the gate electrode 6 and the impurity implanted layer 11. The light transmittance of SiO2 used for the translucent film 14 is about 90% or higher. Therefore, it is possible to suppress an energy loss of the light transmitted through the translucent film 14 toward the semiconductor substrate 1.
Further, a refractive index of the ambient gas of the processing chamber 30 is about one, and the refractive index of Si used for the semiconductor substrate 1 is about four to five. A difference between the refractive indices is large. For example, when irradiating the flashlamp light to the semiconductor substrate 1 directly from the ambient gas, reflectivity at the surface of the semiconductor substrate 1 becomes larger in accordance with the difference of refractive index. The refractive index of SiO2 used for the translucent film 14 is about 1.4, which is an intermediate value between the refractive indices of the ambient gas and Si. Therefore, when irradiating the flashlamp light to the semiconductor substrate 1 through the translucent film 14 having a refractive index as an intermediate value between the refractive indices of the ambient gas and the semiconductor substrate 1, reflectivity at the translucent film 14 and at the surface of the semiconductor substrate 1 is reduced.
Further, the flashlamp light is irradiated to the translucent film 14 which covers the gate electrode 6 and the impurity implanted layers 11. Therefore, reflectivity of the entire surface above the semiconductor substrate 1 is made uniform, so that the pattern density dependence of reflectivity is reduced. Thus, it is possible to suppress local heating.
As mentioned above, the gate electrode 6 and the impurity implanted layers 11, which uniformly absorb the flashlamp light, are uniformly heated. Temperatures of the gate electrode 6 and the impurity implanted layers 11 instantaneously exceed 1100° C., so as to electrically activate the impurities implanted into the gate electrode 6 and the impurity implanted layers 11. By activating the impurities, resistances of the gate electrode 6 and the diffusion layers 13 are uniformly decreased. As described above, according to the embodiment of the invention, it is possible to suppress crystal defects generated in the semiconductor substrate 1 and to form a shallow pn junction. As a result, activation annealing can be carried out with high uniformity and a high yield rate.
In addition, reflectivity at a boundary between the translucent film 14 and the semiconductor substrate 1 can be reduced by adjusting the film thickness of the translucent film 14. The reflectivity at the boundary between the translucent film 14 and the semiconductor substrate 1 varies relative to the film thickness at a cycle of λ/(2*n). Here, λ denotes a peak wavelength of incident light, and n denotes a refractive index of the translucent film 14. A film thickness dmin that minimizes the reflectivity is defined by the wavelength λ and the refractive index n of the translucent film 14, as follows:
dmin=(2j−1)*λ/(4n), (1)
where j is an arbitrary positive integer.
As shown in
The film thickness d of the translucent film 14 is desirably set so as to satisfy conditions of the following expression that is defined by the peak wavelength λ, and the refractive index n of the translucent film 14.
(2j−1)*λ/(4n)−λ/(8n)<d<(2j−1)*λ/(4n)+λ/(8n) (2)
When the film thickness d of the translucent film 14 is within a range defined by Expression (2), the pattern density dependence of the semiconductor substrate 1 is suppressed. As a result, the semiconductor substrate 1 can be highly uniformly heated.
In the above explanation, a SiO2 film is used as the translucent film 14. However, as the translucent film 14, any transparent film having a refractive index as an intermediate value between the refractive indices of the ambient gas and the semiconductor substrate 1 can be used. For example, a Si3N4 film having a refractive index of about two, and a carbon doped silicon oxide (SiOC) film having a refractive index equivalent to that of the SiO2 film, and the like, can be used.
As the translucent film, a multilayer film which includes a plurality of insulating films, such as SiO2, Si3N4, and SiOC, may be used. For example, as shown in
natm<n1<n2<nSi, (3)
where natm and nSi denote refractive indices of the ambient gas and Si, respectively. Each of the differences in refractive indices between the ambient gas, the first insulating film 15, the second insulating film 16, and the semiconductor substrate 1 can be decreased, so that reflectivity at the interface of the semiconductor substrate 1 can be reduced.
Additionally, film thicknesses d1 and d2 of the first and second insulating films 15 and 16 are desirably provided to satisfy conditions of the following expressions.
(2j−1)*λ/(4n1)−λ/(8n1)<d1<(2j−1)*λ/(4n1)+λ/(8n1) (4)
(2k−1)*λ/(4n2)−λ/(8n2)<d2<(2k−1)*λ/(4n2)+λ/(8n2), (5)
where each of j and k is an arbitrary positive integer.
For example, as shown in
As the element pattern, as shown in
In order to check activation of impurities of the diffusion layer, sheet resistance is measured. As shown in
An impurity concentration profile of the diffusion layer of each sample of the embodiment of the present invention and the comparative example is measured by secondary ion mass spectrometry (SIMS). In the embodiment of the present invention, as shown in
The samples subjected to the activation annealing were observed for crystal defects, such as dislocations, by transmission electron microscope (TEM). As shown in
Further, the semiconductor substrate, on which the translucent film is formed, is subjected to activation annealing with various preheating temperatures and irradiation energy density, to observe crystal defects. As shown in
On the other hand, as shown in
In the comparative example, the semiconductor substrate is irradiated with the flashlamp light without the translucent film. As shown in
As shown in
Further, in the Si substrate without a pattern, the flashlamp light is incident to the Si substrate having a high refractive index of four to five from the ambient gas having a refractive index of about one. Accordingly, the flashlamp light is extremely reflected at the surface of the Si substrate. As a result, the heating efficiency of the Si substrate without a pattern is considerably decreased.
In practice, the flashlamp light is a continuous spectrum light having a wide wavelength range as shown in
In this way, for the flashlamp light having a wide wavelength range, variations in reflectivity with respect to a thickness of the translucent film are reduced with the condition that the value of the thickness of the translucent film exceeds a fixed value. Therefore, it is desirable to select the thickness of the translucent film 14 to be about {λ/(4n)} so as to provide the minimum reflectivity, when priority is given to the heating efficiency. On the other hand, when the thickness of the translucent film 14 is selected as {3λ/(4n)} or more, the variations in reflectivity with respect to the thickness variation of the translucent film 14 can be suppressed. Accordingly, for designing a process condition of activation annealing, robust design for optimizing a process condition can be made, and the annealing method is more practical from the viewpoint of manufacture of the semiconductor device.
Further, within a wavelength range equal to or less than the peak wavelength λ of the flashlamp light, reflectivity of a semiconductor substrate 1, such as Si, may have large changes. For example, as shown in
A manufacturing method for a semiconductor device according to the embodiment of the present invention will be described using a manufacturing process of a CMOS transistor as an example. Further, the semiconductor device is not limited to a CMOS transistor. A semiconductor device such as a p-MOS transistor or a n-MOS transistor is also within the scope of the invention. Additionally, a MIS transistor using an insulating film such as a SiON film, a Si3N4 film, or a composite insulating film between a SiO2 film and an SiON film, an Si3N4 film, a various metal oxide film or the like, instead of an SiO2 film of a MOS transistor, is also within the scope of the invention.
As shown in
As shown in
As shown in
As shown in
Then, by photolithography and the like, a photoresist film is formed to cover the nMOS region. Using the gate electrode 6b and the sidewall spacer 7b as a mask, group III element ions (second impurity ions), such as B ions, are selectively implanted into the PMOS region by beam line ion implantation. Ion implantation conditions are acceleration energy of about 4 keV and an implant dose of about 3×1015 cm−2. The photoresist film on the nMOS region is removed.
By spike RTA and the like, the P and B ions implanted in the p-well 2, the n-well 3, and the gate electrode 6a, 6b are activated at a temperature of about 1000° C. The term “spike RTA” refers to an RTA process that eliminates the time to maintain the highest attained temperature. As a result, n+-type source-drain regions 8 and p+-type source-drain regions 9 are formed between both ends of the sidewall spacer 7a, 7b and the STI 4, respectively.
As shown in
As shown in
Then, by photolithography and the like, a photoresist film is formed to cover the nMOS region. Using the gate electrode 6b as a mask, group III element ions (first impurity ions), such as B ions, are selectively implanted into the PMOS region by ion implantation. Ion implantation conditions are acceleration energy of about 0.5 keV and an implant dose of about 1×1015 cm−2.
As a result, impurity implanted regions 10 and 11 implanted with the P and B ions are formed in the nMOS and PMOS regions of the semiconductor substrate 1 between both ends of the gate insulating films Sa, 5b, and the STI 4, respectively.
As shown in
The semiconductor substrate 1 is placed on top of the susceptor 31 of the annealing apparatus shown in
As shown in
By sputter and the like, a metal film such as nickel (Ni) is deposited on top of the semiconductor substrate 1. By RTA and the like, silicidation of the deposited metal film is implemented on the surfaces of the gate electrodes 6a, 6b and the source-drain regions 8, 9, which are disposed between the STI 4 and the sidewall spacers 17a, 17b. By wet etching and the like, unreacted Ni is removed. An interlevel insulating film such as SiO2, is deposited on the surface of the semiconductor substrate 1. Then, contact holes are opened in the interlevel insulating film above the gate electrodes 6a, 6b, and the source-drain regions 8, 9, respectively. Interconnections are connected to the gate electrodes 6a, 6b, and the source-drain regions 14, 15 through the contact holes, respectively. Thus, a semiconductor device having the shallow extension regions 12, 13 of about 20 nm or less is manufactured.
In a manufacturing method of a semiconductor device according to the embodiment of the present invention, the extension regions 12, 13 are activated by irradiating with the flashlamp light from the light source 38 through the translucent film 14a. The refractive indices of the first and second insulating films 15, 16 of the translucent film 14a are larger than that of the ambient gas and smaller than that of the semiconductor substrate 1. In addition, the refractive index of the second insulating film 16 on the ambient side is smaller than that of the first insulating film 15. As mentioned above, since differences in the refractive index between the ambient gas, the first and second insulating film 15, 16, and the semiconductor substrate 1 can be reduced, reflectivity at the interface of the semiconductor substrate 1 can be decreased.
Further, the flashlamp light is irradiated to the translucent film 14a which covers gate electrodes 6a and 6b and the impurity implanted regions 10, 11. Since the reflectivity of the entire surface of the semiconductor substrate 1 becomes uniform, the pattern density dependence is reduced. Thus, it is possible to suppress local heating. In this way, in the embodiment of the present invention, it is possible to suppress crystal defects generated in the semiconductor substrate 1 and to form a shallow pn junction. As a result, highly uniform semiconductor devices can be manufactured with a high yield rate.
In addition, in the source-drain regions 8, 9 in which ion implant depths of the impurities are deep compared to the extension regions 12, 13, it is difficult to recover crystal defects due to the ion implantation by ultrarapid thermal annealing, such as flashlamp annealing. In particular, dislocations or stacking faults tend to remain around the pn junction. This is because heat may not reach to a deep portion over the pn junction by ultrarapid thermal annealing. If the irradiation energy density of the flashlamp light is increased, it become possible to recover crystal defects. However, due to the thermal stress, damage, such as slips and dislocations, are generated in the semiconductor substrate 1, and thus a production yield is decreased. Consequently, activation annealing for the source-drain regions 8, 9 is carried out by spike RTA to recover the crystal defects due to the ion implantation. In the deep source-drain regions 8, 9, since thermal diffusion is not a serious problem, spike RTA, which requires a longer time than flashlamp annealing, can be used.
After forming the deep source-drain regions 8, 9, the shallow extension regions 12, 13 are formed. In the shallow extension regions 12, 13, since the thermal diffusion is a serious problem, spike PTA cannot be used. Thus, an ultrarapid thermal annealing technique is inevitable. Since the impurity implanted regions 10, 11 are shallow, i.e., about 20 nm or less, heat can be transmitted throughout the impurity implanted regions 10, 11 even by ultrarapid thermal annealing. As a result, the crystal defects generated around the impurity implanted regions 10, 11 may be easily recovered. As mentioned above, the source-drain regions 8, 9 and the extension regions 12, 13 can reduce the crystal detects to active impurities at high concentration, and thus it is possible to improve transistor performance.
In the embodiment of the present invention, a Xe flashlamp is used as the light source 38 shown in
Various modifications will become possible for those skilled in the art after storing the teachings of the present disclosure without departing from the scope thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| P2005-92751 | Mar 2005 | JP | national |
