CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims the benefit of priority from Chinese Patent Application No. 202211323489.7, filed on Oct. 27, 2022. The content of the aforementioned application, including any intervening amendments thereto, is incorporated herein by reference in its entirety.
TECHNICAL FIELD
This application relates to manufacturing of ultra-large-scale integrated circuits, and more particularly to a method for fabricating a gate-all-around (GAA) structure.
BACKGROUND
Gate-all-around (GAA) electrical devices are critical structures in the fabrication of very large-scale integrated circuits (VLSI) at the 3 nm node and below. The fabrication process of the GAA device mainly includes: growth of silicon germanium (SiGe)/silicon (Si) superlattice, pattern etching in active region, patterning and etching of amorphous silicon (a-Si) dummy gate, etch back of source and drain regions, formation of inner spacer, selective epitaxy on source and drain regions, removal of dummy gate and filling of high-K metal gate (HKMG).
During the patterning and etching of the dummy gate, the large aspect ratio will lead to inconsistency in lengths of the upper and lower gates and large roughness in the pattern edge. In the removal of the dummy gate, the high-aspect-ratio etching process will easily cause damage to the sidewall of the superlattice Fin. When filling the metal gate in the dummy gate trench, the high-resistance titanium nitride is the predominant part. Moreover, there is a parasitic capacitance between the side wall of the dummy-gate trench and the parallel metal gate adjacent thereto, and between its Fin side walls.
In order to improve the gate length consistency of nanosheet devices, reduce the channel edge roughness, and enhance the performance of nanosheet devices, it is urgently required to develop a process for fabricating a low-aspect-ratio dummy gate.
SUMMARY
An objective of this application is to provide a method for fabricating a gate-all-around (GAA) structure. In this method, after the active region of a superlattice is etched, the selective epitaxy growth (SEG) of a SiGe layer (the SiGe layer has the same Ge level with the SiGe superlattice) is performed to form a SiGe stacked structure, and after the backfilling of silicon oxide and chemical mechanical polishing (CMP), an amorphous-silicon dummy-gate CMP process is conducted on a flat top to reduce the aspect ratio of the dummy gate, so as to effectively improve the patterning uniformity of dummy gate and edge roughness, and avoid damage to the sidewall of the active region.
Technical solutions of this application are described as follows.
This application provides a method for fabricating a gate-all-around (GAA) structure, comprising:
- (A) forming a silicon germanium (SiGe)/silicon (Si) periodic superlattice laminate on a substrate;
- (B) forming at least two active regions on the SiGe/Si periodic superlattice laminate by patterning;
- (C) forming an isolation structure between the at least two active regions;
- (D) performing selective epitaxy growth of a SiGe layer on the at least two active regions to form a SiGe-wrapped stacked structure; wherein the SiGe layer and a SiGe superlattice in the SiGe/Si periodic superlattice laminate have the same germanium (Ge) content;
- (E) depositing a layer of a first dielectric material, and polishing a top of the layer of the first dielectric material;
- (F) forming a dummy gate pattern on the top of the layer of the first dielectric material through steps of:
- (F1) depositing a dummy-gate material on the top of the layer of the first dielectric material, wherein a ratio of an etch rate of the dummy-gate material to an etch rate of Si and SiGe in dry etching or wet etching is greater than 5:1; and
- (F2) defining the dummy-gate pattern by photoetching and etching; wherein a width of the dummy-gate pattern defines a gate length of a nanosheet device;
- (G) performing doping in a source-drain extension region through steps of:
- (G1) taking the dummy-gate pattern as a mask, removing the first dielectric material exposed on a top of the at least two active regions by anisotropic etching; and
- (G2) taking the dummy-gate pattern as the mask, performing doping and activation in the source-drain extension region of the at least two active regions;
- (H) forming a gate spacer structure through steps of:
- (H1) isotropically depositing a layer of a second dielectric material; and
- (H2) performing maskless etching through anisotropic etching to form the gate spacer structure on each side of the dummy-gate pattern;
- (I) performing source-drain etch back through steps of:
- (I1) depositing a layer of a third dielectric material as an etching mask to protect the dummy gate and the gate spacer structure;
- (I2) exposing a source-drain etch-back window by photoetching;
- (I3) removing exposed SiGe/Si periodic superlattice laminate by anisotropic etching to complete the etch back of the source and the drain; and
- (I4) removing the third dielectric material;
- (J) forming an inner spacer through steps of:
- (J1) selectively etching the SiGe layer by isotropic etching, wherein an etching depth of the SiGe layer is equal to a thickness of the gate spacer structure;
- (J2) isotropically depositing a layer of a fourth dielectric material; wherein a thickness of the layer of the fourth dielectric material is greater than the etching depth of the SiGe layer; and
- (J3) removing exposed parts of the layer of the fourth dielectric material by anisotropic etching to form the inner spacer;
- (K) forming a source-drain structure by selective epitaxy and in-situ doping;
- (L) depositing a first interlayer dielectric material, and exposing the dummy gate through chemical mechanical polishing (CMP);
- (M) removing a dummy gate and forming a high-k metal gate (HKMG);
- (N) depositing a second interlayer dielectric material, and forming a gate-end contact hole, a source-end contact hole, a drain-end contact hole and a bulk-end contact hole; and filling Metal 0 in the gate-end contact hole, the source-end contact hole, the drain-end contact hole and the bulk-end contact hole by sputtering; and
- (O) performing a back-end-of-line (BEOL) process to complete device integration.
In an embodiment, step (B) is performed through steps of:
- (B1) depositing a layer of a hard mask material;
- (B2) patterning the layer of the hard mask material by photoetching to form a pattern whose shape and size respectively defines a shape and a size of each of the at least two active regions; and
- (B3) etching the SiGe/Si periodic superlattice laminate and the substrate by anisotropic etching to form the at least two active regions;
- wherein a ratio of an etch rate of the hard mask material in step (B2) to an etch rate of Si and SiGe is greater than 5:1.
In an embodiment, step (E) is performed through steps of:
- (E1) removing the hard mask material;
- (E2) depositing the layer of the first dielectric material on the at least two active regions, wherein a thickness of the layer of the first dielectric material is greater than a height of the at least two active regions;
- (E3) polishing the layer of the first dielectric material by CMP; and
- (E4) reducing the thickness of the layer of the first dielectric material by anisotropic etching, wherein the thickness of the layer of the first dielectric material is always kept greater than the height of the at least two active regions.
In an embodiment, step (M) is performed through steps of:
- (M1) selectively removing an exposed part of the dummy gate and a polished layer of the first dielectric material at a bottom thereof;
- (M2) selectively removing an exposed part of the SiGe layer; and
- (M3) isotropically depositing a gate dielectric material, a work-function metal and a gate metal material sequentially.
In an embodiment, the substrate is a bulk-silicon substrate or a silicon-insulator-silicon (SOI) substrate.
In an embodiment, in step (A), individual Si1-xGex layers in the SiGe/Si periodic superlattice laminate have the same x value.
In an embodiment, in step (C), for the bulk-silicon substrate, the isolation structure is formed by combination of well and shallow trench; and for the SOI substrate, the isolation structure is formed by shallow trench.
In an embodiment, in step (H), the gate oxide layer is made of a high-k (HK) dielectric material, and is formed by atomic layer deposition (ALD).
In an embodiment, in step (N), the Metal 0 is tungsten (W) or copper (Cu).
Compared with the prior art, this application has the following beneficial effects.
- (1) In the existing method, the gate structure is defined through the polycrystalline/amorphous silicon dummy gate lines. Compared with the existing method, the method provided herein reduces the aspect ratio of the dummy gate lines, which effectively reduces the impact on the channel surface during the removal of the dummy gate while ensuring the length consistency of the upper layer gate and the lower layer gate of the nanosheet device, and improves the device performance.
- (2) The method provided herein can effectively reduce the high-resistance metal area through the all-around gate defined by the epitaxial SiGe, thereby reducing the parasitic capacitance between the metal resistance and the gate lines, and thus improving the circuit speed.
BRIEF DESCRIPTION OF THE DRAWINGS
The patent or application file contains at least one drawing executed in color. Copies of this patent or patent application publication with color drawing(s) will be provided by the Office upon request and payment of the necessary fee.
FIGS. 1-17 are schematic diagrams of key processes in the fabrication of a gate-all-around (GAA) structure provided in the following embodiments of this application.
In FIGS. 1-17, a is a top view, b is a sectional view along A-A′ line in a, and c is a sectional view along B-B′ line in a;
FIGS. 1a-c schematically show growth of superlattice laminate on a substrate and patterning of hard mask to define active regions;
FIGS. 2a-c schematically show formation of active regions by patterning;
FIGS. 3a-c schematically show formation of isolation structure between active regions;
FIGS. 4a-c schematically show selective epitaxy growth of a silicon germanium (SiGe) layer on a semiconductor material, where the SiGe layer and a SiGe superlattice in the SiGe/Si periodic superlattice laminate have the same germanium (Ge) content
FIGS. 5a-c schematically show deposition of an interlayer dielectric and chemical mechanical polishing (CMP), etch back and thickness reduction of the interlayer dielectric;
FIGS. 6a-c schematically show deposition and patterning of a dummy-gate material;
FIGS. 7a-c schematically show deposition of a gate-spacer material;
FIGS. 8a-c schematically show maskless etching to form the gate spacer structure;
FIGS. 9a-c schematically show source-drain etch back;
FIGS. 10a-c schematically show selective etching of SiGe to form inner spacer;
FIGS. 11a-c schematically show deposition the inner-spacer material followed by etching to form the inner spacer;
FIGS. 12a-c schematically show in-situ doping epitaxy to form source and drain;
FIGS. 13a-c schematically show deposition of interlayer dielectric followed by chemical mechanical polishing (CMP) to expose the dummy-gate material;
FIGS. 14a-c schematically show removal of the dummy-gate material and dielectric material under dummy-gate material the by isotropic etching;
FIGS. 15a-c schematically show selective removal of the remaining SiGe to release the channel;
FIGS. 16a-c schematically show sequential deposition of high-k (HK) dielectric material, work function metal and gate metal material;
FIGS. 17a-c schematically show formation of the contact hole VO by photoetching, and filling of the contact hole VO with Metal 0 followed by CMP to isolate a conductive layer of the device; and
FIG. 18 explains graphic symbols in FIGS. 1-17.
DETAILED DESCRIPTION OF EMBODIMENTS
This application will be described in detail below with reference to the accompanying drawings and embodiments.
This application provides a method for fabricating a gate-all-around (GAA) structure, which was performed as follows.
- (1) A silicon germanium (SiGe)/silicon (Si) periodic superlattice laminate was formed on a (100) bulk silicon substrate by epitaxy. A thickness of the SiGe layer in the SiGe/Si periodic superlattice laminate was 15 nm, and a thickness of the Si layer in the SiGe/Si periodic superlattice laminate was 8 nm, as shown in FIG. 1.
- (2) A Si3N4 layer was deposited on the SiGe/Si periodic superlattice laminate as an etching hard mask by plasma enhanced chemical vapor deposition (PECVD). A SiO2 layer was employed as a stress buffer layer between the Si3N4 layer and the SiGe/Si periodic superlattice laminate. The Si3N4 layer was patterned through photoetching and etching.
- (3) The SiGe/Si periodic superlattice laminate was etched by taking the Si3N4 layer as the hard mask to define patterns of active regions, as shown in FIG. 2.
- (4) A SiO2 layer was deposited on the SiGe/Si periodic superlattice laminate by using PECVD, and then subjected to chemical mechanical polishing (CMP), until the Si3N4 layer was exposed. The SiO2 layer was subjected to etch back to a surface of the bulk silicon substrate by dry etching to form shallow trench isolation (STI), as shown in FIG. 3.
- (5) A single-crystal SiGe layer was grown on a surface of the Si layer and the SiGe layer by selective epitaxy. The single-crystal SiGe layer and a SiGe superlattice in the SiGe/Si periodic superlattice laminate have the same germanium (Ge) content, as shown in FIG. 4.
- (6) The active regions were respectively covered with a SiO2 layer through PECVD, and then flattened by CMP. After that, the SiO2 layer on the active regions was back etched to reduce the thickness. A distance between the surface of the SiO2 layer and the surface of the SiGe/Si periodic superlattice laminate was about 10 nm, as shown in FIG. 5;
- (7) Amorphous Silicon (a-Si) (80 nm) was deposited on the silicon layer by PECVD. A pattern of a dummy gate was defined by photoetching, as shown in FIG. 6.
- (8) Taking the dummy gate as a mask, the exposed SiO2 was anisotropically removed through dry etching to expose the surface of the SiGe/Si periodic superlattice laminate.
- (9) A SiO2 (1 nm) was deposited on a surface of the amorphous silicon by rapid thermal oxidation. A source-drain extension region was doped and activated through Spike activation through ion injection.
- (10) A Si3N4 layer (50 nm) was deposited on the SiO2 (1 nm) by PECVD, as shown in FIG. 7. A gate spacer structure was formed by maskless etching, as shown in FIG. 8.
- (11) A layer of the hard mask material was deposited on the Si3N4 layer (50 nm) and patterned to protect the dummy gate and the gate spacer structure. Exposed source and drain were subjected to etch back, as shown in FIG. 9.
- (12) SiGe was selectively etched through isotropic etching. An etching depth was the same as a thickness of the gate spacer structure, as shown in FIG. 10.
- (13) A SiOC layer was isotropically grown on the inner gate spacer structure by using atomic layer deposition (ALD). Exposed SiOC was removed by etching to form inter gate spacer structure, as shown in FIG. 11.
- (14) Source and drain were formed by in-situ doping and epitaxy. SiC or Si material were subjected to epitaxy on a negative-channel metal-oxide-semiconductor. SiGe material epitaxy was performed on positive-channel metal-oxide-semiconductor (PMOS), as shown in FIG. 12.
- (15) A SiO2 layer was deposited by PECVD, and then subjected to CMP to expose the a-Si dummy gate, as shown in FIG. 13.
- (16) The a-Si dummy gate and SiO2 layer at the bottom of the dummy gate were selectively removed with tetramethylammonium hydroxide (TMAH), as shown in FIG. 14.
- (17) The remaining SiGe was removed by isotropic etching to release the channel, as shown in FIG. 15.
- (18) Hafnium (IV) oxide (HfO2), NMOS work function metal (WFM), PMOS work function metal (WFM) and metallic tungsten (W) were sequentially deposited by ALD, as shown in FIG. 16;
- (19) A SiO2 layer (200 nm) was deposited by PECVE, and then subjected to CMP to form an interlayer dielectric.
- (20) A gate-end contact hole, a source-end contact hole, a drain-end contact hole and a bulk-end contact hole were formed.
- (21) The gate-end contact hole, the source-end contact hole, the drain-end contact hole and the bulk-end contact hole were filled with Metal 0 by sputtering.
- (22) The Metal 0 was subjected to CMP to separate the conductive layers of the devices to achieve the isolation effect, as shown in FIG. 17.
- (23) Back-end-of-line process (BEOL) (including through-hole fabrication, metal deposition and metal wire etching) was performed to complete device integration.
Graphic symbols in FIGS. 1-17 are explained in FIG. 18.
The above embodiments are merely illustrative of this application, and are not intended to limit this application. It should be understood that various changes, modifications and variations made by those skilled in the art to the above embodiments without departing from the spirit of the application should fall within the scope of the disclosure defined by the appended claims.
Patent Application
20230387249
