The present invention relates to the art of filling vias with an aspect ratio of at least approx. 1:1 in a substrate. The vias may have a depth in the small submicron as below 40 nm.
From the US 2007/0074968 it is known to deposit films onto high aspect ratio submicron featured semiconductor wafers by making use of ionized physical vapor deposition (iPVD) and etching.
Similarly, the U.S. Pat. No. 5,800,688 proposes to fill submicron high aspect ratio features on very large scale integrated semiconductor devices making use of iPVD.
The U.S. Pat. No. 5,178,739 addresses the deposition of material uniformly into high aspect ratio holes or trenches.
US 2003/0034244 addresses metallization of via and trenched structures on semiconductor wafers making use of sequentially applied deposition and etching steps.
The U.S. Pat. No. 6,719,886 addresses that ionized physical vapor deposition is a process which has particular utility in filling and lining high aspect ratio structures on silicon wafers. The principle of iPVD is explained.
Attention is also drawn on EP 0 782 172, U.S. Pat. No. 6,287,435 and U.S. Pat. No. 6,417,626.
Out of the generic art of filling high aspect submicron vias of high aspect ratio generically with a material as addressed above the present invention is more specifically directed on filling such vias with an aspect ratio of approx. 1:1 with a chalcogenide glass material which exhibits a thermally driven amorphous/crystalline phase change.
This technique is specifically addressed in the article DOI 10.1007/s00399-012-7463-8 “Nanoscale gap-filling for phase change material by pulsed deposition and inductively coupled plasma etching”, W. C. Ren et al., Applied Physics, Springer. The article departs from the recognition that gap-filling of phase-change material has become a critical module in the fabrication process of phase-change random access memory (PCRAM) as the device continues to scale down to 45 nm and below. It appears from the article that void-free gap filling with phase-change material on 30 nm vias with aspect ratios of 1:1 by a two-cycle deposition/etching/deposition process (DED) is achieved. As a specific example of chalcogenide glass material which exhibits a thermally driven amorphous/crystalline phase-change, Ge2Sb2Te5 (GST) is applied. For material deposition DC magnetron sputtering is applied, DC being in fact pulsed DC. For etching, soft etching is applied with the help of an inductively coupled plasma (ICP). The PVD material deposition step and the etching step are performed without vacuum break between the deposition and the etching process steps.
It is an object of the present invention to improve the method as addressed in the W. C. Ren et al. article and to provide a substrate via filling vacuum processing system to operate such improved method.
This object is achieved by a method of filling vias with an aspect ratio of at least approx. 1:1 within a substrate and thereby manufacturing substrates comprising vias filled with a material. The material is a chalcogenide glass material which exhibits a thermally driven amorphous/crystalline phase-change out of the group of following materials:
GeSbTe, AgInSbTe, InSe, SbSe, SbTe, InSbTe, GeSbSe, GeSbTeSe, AgInSbSeTe,
Thereby the material is especially GeSbTe (GST).
When discussing or claiming material deposition in vias as addressed, it is important to clarify what specific areas of a via and of the respective covering is addressed. These areas of via and respective covering shall be defined in context with
In a substrate 1 a via 3 comprises a via bottom 5 and a via top 7. In fact, the via top 7 is the part of the surface of substrate 1, wherein via 3 is worked.
Via sidewalls 9 link via bottom 5 to via top 7. The via covering 11 may be subdivided in top covering 13, which transits into sidewall top covering 15 of sidewall covering 17. Sidewall top covering 15, by which top covering 13 transits into sidewall covering 17 is approx. addressed by dashed line in
Sidewall covering 17 transits via bottom sidewall covering 19 into via bottom covering 20.
Via bottom sidewall covering 19, by which via sidewall covering 17 transits into via bottom covering 20 is also shown qualitatively by dashed line in
Turning back to the method, by which the object as addressed above is resolved, such method comprises:
In a subsequent step b) the addressed void is enlarged towards the surrounding of the via top covering by etching with the help of an inductively coupled plasma. Thus, the void which remains after step a) is wedge-like opened and enlarged towards the surface of the via top covering 13 as of
Subsequent to the addressed step b) a step c) is performed, in which the addressed material is sputter-deposited by DC sputtering upon the addressed area. This is performed to an extent so as to either complete the filling of the via by the addressed material at least from the via bottom to the via top or to again leave a void in the covered via which void is open towards the surrounding of the via top covering.
In the case that by the addressed step c) a void is left in the covered via which is open towards the surrounding of the via top covering, step b), i.e. the etching step, and step c), i.e. the sputter-depositing step, are repeated. The steps a) to step c) are performed in one common vacuum process chamber, so that not only no vacuum break occurs, but additionally only one processing chamber becomes necessary without transporting the substrates in vacuum from one processing chamber to the other. Transporting the substrate from a deposition chamber to an etching chamber and back to a deposition chamber several times has the significant disadvantage of complicated transport arrangements, possibly with loadlocks, and especially bears the danger of contaminating the substrate as by particles. Additionally, such forth and back transport significantly slows down the production rate, i.e. the throughput.
In a good embodiment of the method according to the invention, which may be combined with any of the subsequently addressed method embodiments, unless in contradiction, DC sputtering which may include continuous or pulsed DC sputtering and is in fact magnetron sputtering, is performed in the addressed steps a) and c) without applying a bias signal to the substrate by a settable biasing source operationally connected to the substrate. This means that no external biasing source is operationally connected via a substrate holder to the substrate.
In a good embodiment of the method according to the invention, which may be combined with any of the preaddressed and subsequently addressed method-embodiments, unless in contradiction, igniting the inductively coupled plasma as applied in step b) is performed by a plasma of sputter-depositing as exploited in step a) and/or step c). Inversely, the inductively coupled plasma of step b) ignites the sputtering plasma in step c). Thereby, it must be emphasized that it is perfectly clear to the skilled artisan that sputtering necessitates a plasma.
Thereby, not only the addressed process steps are performed without transport in one common vacuum process chamber, but additionally, in the addressed vacuum process chamber, a plasma is continuously maintained during the addressed steps, as one plasma of one step ignites the plasma of the subsequent step.
In a good embodiment of the method according to the invention, which may be combined with any of the preaddressed method embodiments and such embodiments still to be addressed, unless in contradiction, the substrate is a silicon wafer.
In a good embodiment of the method according to the invention, which may be combined with any of the preaddressed embodiments and such embodiments still to be addressed, unless in contradiction, the method further comprises providing the substrate in the one common vacuum process chamber along a substrate plate. The target arrangement, which comprises one or more than one targets, is provided along a substantially plane or dome-shaped cover part of the common vacuum process chamber. The addressed target arrangement faces the at least one substrate. The cover part, either plane or dome-shaped, transits into lateral walls of the common vacuum process chamber along a substantially circular area. Thus, the lateral walls of the common vacuum process chamber are realized, at least in the addressed transit area, by a cylindrical wall. With respect to a central axis of the addressed circular area this area thus defines for an inner radius Ri and an outer Ro. The circular area resides at least substantially in a plane, named transiting plane, which is at least substantially parallel to the addressed substrate plane.
A spacing d between the substrate plan and the transiting plane, with respect to the inner radius Ri of the substantially circular area, is selected to fulfil:
0.7≦Ri/d≦1.6.
In a today practiced good embodiment there is selected
1≦Ri/d≦1.6.
By this embodiment a medium-throw setup of the one common vacuum process chamber is realized. Such medium-throw setup results in a narrow angular distribution of the sputtered off material compared to a more common low-distance or low-throw sputtering setup. Thereby, it should be considered that the radius Ri substantially defines for the respective maximum extent of the target arrangement within the one common vacuum process chamber. The vacuum process chamber is customarily not tailored larger than necessary and is primarily governed by the extent of a target arrangement to be provided, besides of the extent of substrates to be treated. Thus, the addressed radius Ri of the circular area at least approx. defines for the extent of the target arrangement as seen from the substrate. Additionally, such medium-throw setup allows the implementation of the inductively coupled plasma between the target arrangement and the substrate.
In a good embodiment of the method according to the invention, which may be combined with any of the preaddressed method embodiments and such embodiments still to be addressed, unless in contradiction, the total pressure in the common vacuum process chamber during sputter-depositing of step a) and during sputter-depositing of step c) is selected to be higher than a total pressure selected in the one common vacuum process chamber during the etching of step b) by a factor of at least 2 to 30, preferably by a factor of at least 10.
In a further good embodiment of the method according to the invention, which may be combined with any of the preaddressed method embodiments and such embodiments still to be addressed, unless in contradiction, the target arrangement is selected to comprise more than one target. By this and respective control of the more than one of the addressed targets it becomes possible to optimally control sputter-deposition distribution. Thereby, in a good embodiment of the just addressed embodiment the addressed more than one targets are provided of different materials and the stoichiometry of the sputter-deposited material is controlled by individually controlling the sputtering rates of the addressed more than one targets.
In a further good embodiment of the method according to the invention, which may be combined with any of the preaddressed method embodiments and such embodiments still to be addressed, unless in contradiction, at least one target of the target arrangement, which may comprise one or more than one target, is tilted with respect to a substrate plane along which the one or more than one substrate reside for processing.
In a further good embodiment of the method according to the invention, which may be combined with any of the preaddressed method embodiments and such embodiments still to be addressed, unless in contradiction, the total pressure pb applied in step b) is selected to be
10−4 mbar≦pb≦2·10−3 mbar.
In a good embodiment there is selected
10−4 mbar≦pb≦10−3 mbar,
and further in a good embodiment as today practiced
5·10−4 mbar≦pb≦2·10−3 mbar.
In a further good embodiment of the method according to the invention, which may be combined with any of the preaddressed method embodiments and such embodiments still to be addressed, unless in contradiction, the method comprises performing step a) and step c) at a total pressure pa, pc respectively in the common vacuum process chamber of
5·10−3 mbar≦pa≦5·10−2 mbar
5·10−3 mbar≦pc≦5·10−2 mbar, or of
10−2 mbar≦pa≦10−1 mbar,
10−2 mbar≦pc≦10−1 mbar,
as practiced today.
In a further good embodiment of the method according to the invention, which may be combined with any of the preaddressed method embodiments and such embodiments still to be addressed, unless in contradiction, the inductively coupled plasma is generated by means of an electric coil arrangement with at least one electric coil wound around at least a part of the inner volume of said one common vacuum process chamber and preferably operating the coil with an electric current at a frequency fi for which there is valid:
400 kHz≦fi≦27 MHz,
thereby as practiced today of
400 kHz≦fi≦450 kHz.
In a further good embodiment of the method according to the invention, which may be combined with any of the preaddressed method embodiments and such embodiments still to be addressed, unless in contradiction, the inductively coupled plasma is generated by means of an electric coil arrangement with at least one electric coil wound around at least a part of the inner volume of the one common vacuum process chamber, whereby the addressed electric coil is also operated during at least one of the steps a) and c) for controlling thickness distribution of the sputter-deposited covering.
In a further good embodiment of the method according to the invention, which may be combined with any of the preaddressed method embodiments and such embodiments still to be addressed, unless in contradiction, Rf biasing is applied at a voltage ubias for which there is valid:
35 V≦ubias≦100 V.
In a further good embodiment of the method according to the invention, which may be combined with any of the preaddressed method embodiments and such embodiments still to be addressed, unless in contradiction, before performing step a) there is applied a seed layer in the addressed via. Preferably the thickness of such seed layer is selected to be between 0.5 nm and 5 nm, both limits included.
By such a seed, also called wetting layer, the risk of overhangs being formed by the sputter-depositing steps a) is further reduced. The addressed seed layer avoids the formation of such overhangs and helps to distribute the material. The sputter-deposited material coagulates with a high contact angle upon such seed layer resulting in a reduced adhesion and in a reduced risk of void formation inside the via. By such seed layer the adhesion of sputter-deposited material is thus improved and completely filling the via is facilitated.
In a further good embodiment of the method according to the invention, which may be combined with any of such preaddressed method embodiments and such embodiments still to be addressed, unless in contradiction, the seed layer is of W or of Ta2O5. Thereby, preferably W is applied by sputtering and Ta2O5 by reactive sputtering. These seed layer materials are preferably applied in combination with GeSbTe as covering material.
In a further good embodiment of an embodiment in which a seed layer is applied as was addressed above, the seed layer is applied within the addressed one common vacuum process chamber or in a separate vacuum process chamber.
In a further good embodiment of the method according to the invention, which may be combined with any of the preaddressed method embodiments and such embodiments still to be addressed, unless in contradiction, the substrate is rotated or oscillated during at least one of the addressed steps a), b) c).
So as to operate the method according to the invention in all of the embodiment addressed above, there is proposed a substrate via-filling vacuum system which comprises a vacuum process chamber with at least one substrate holder therein. The vacuum process chamber comprises a sputtering target arrangement comprising one or more than one targets, the material of the one target or the materials of the more than one targets in combination being of all elements of one material out of the following material group:
GeSbTe, AgInSbTe, InSe, SbSe, SbTe, InSbTe, GeSbSe, GeSbTeSe, AgInSbSeTe,
thereby especially of GeSbTe (GST). Thus and e.g. with an eye on GST, in the case of more than one target one target may be e.g. of Ge, one other target e.g. of Sb and a third target then of Te.
The process chamber further comprises an electric coil arrangement with at least one electric coil which is wound around at least a part of the inner volume of the vacuum process chamber. The system further comprises
The process control unit is thereby adapted to control
at the end of the first timespan
In other words, the substrate via filling vacuum system according to the invention has, at one common vacuum process chamber, a sputtering source arrangement for sputtering or co-sputtering the desired chalcogenide glass material. It further comprises an electric coil arrangement by which an inductively coupled plasma may be generated in at least a part of the inner volume of the vacuum process chamber and comprises further a first Rf power supply to supply the coil arrangement, a second Rf power supply arrangement to bias the substrate support and a continuous or pulsed DC power supply arrangement to supply the target arrangement. By means of the process control unit during a first timespan the system is controlled to establish DC sputtering. Subsequent to the first timespan and during a second predetermined timespan the process control unit disables sputtering and enables operation of the inductively coupled plasma, thereby the operation of the substrate holder at an Rf electric bias potential.
In a good embodiment of the system according to the invention, which may be combined with any system embodiment still to be addressed, unless in contradiction, during establishing by the process control unit the supply operational connection of the DC power supply arrangement to the sputtering target arrangement and thus during the first predetermined timespan, no signal supply source is operationally connected to the substrate holder. Thus, no external biasing source is connected to the addressed substrate holder, especially not an Rf biasing source.
In a good embodiment of the system according to the invention, which may be combined with any system embodiment addressed and still to be addressed, unless in contradiction, the process control unit is adapted to control the second predetermined timespan so as to initiate as the first predetermined timespan terminates. Thus, the process control unit is in fact adapted to control sputtering timespan, the first predetermined timespan, to continuously transit into the “etching” timespan, the second predetermined timespan, in which Rf bias and inductively coupled plasma are operated.
In a good embodiment of the system according to the invention, which may be combined with any preaddressed system embodiment and system embodiments still to be addressed, unless in contradiction, the sputtering target arrangement comprises more than one target and the process control unit is adapted to individually control the sputter rate of said more than one targets.
The sputter rate may thereby be controlled preferably by respectively adjusting the electric power applied to the respective targets, i.e. the continuous or pulsed DC power supplied and/or by the strength of respective magnetron magnet fields.
In a good embodiment of the just addressed system embodiment at least some of the more than one targets are of different materials.
In a good embodiment of the system according to the invention, which may be combined with any preaddressed system embodiment and system embodiments still to be addressed, unless in contradiction, a medium throw setup of the one process chamber is realized as was discussed in context with the method according to the invention in that the substrate holder is tailored to define a substrate plane within the vacuum process chamber. The vacuum process chamber comprises a substantially plane or a dome-shaped cover part facing the substrate plane. The sputtering target arrangement is mounted along the addressed cover part. The cover part transits into lateral walls of the vacuum process chamber along a substantially circular area about a central axis of the vacuum process chamber. The circular areas defines, with respect to the addressed central axis, an inner radius Ri and an outer radius Ra. The addressed circular area further resides substantially in a plane which is called “transiting plane” and which is substantially parallel to the substrate plane. So as to establish the addressed medium-throw setup a spacing d between the substrate plane and the transiting plane with respect to the inner radius Ri of the substantially circular area is selected to be
0.7≦Ri/d≦1.6
or
1≦Ri/d≦1.6.
In a good embodiment of the system according to the invention, which may be combined with any preaddressed system embodiment and system embodiments still to be addressed, unless in contradiction, the process control unit is adapted to control pressure in the vacuum process chamber during the second predetermined timespan to be smaller than the pressure in the vacuum process chamber during the first timespan by a factor of at least 2 to 30, or of at least 10.
In a good embodiment of the system according to the invention, which may be combined with any preaddressed system embodiment and system embodiments still to be addressed, unless in contradiction, the substrate holder defines for a substrate plane and the or at least one target of the sputtering target arrangement is tilted with respect to an axis perpendicular to the substrate plane by an angle of less than 90°.
In a further good embodiment of the system according to the invention, which may be combined with any preaddressed system embodiment and system embodiments still to be addressed, unless in contradiction, the electric coil arrangement comprises at least one electric coil and further comprises a tubular body of a dielectric material, preferably of a ceramic material. The outer surface of the tubular body faces the at least one electric coil and the inner surface of the tubular body faces the part of the inner volume of the vacuum process chamber about which the at least one electric coil is wound. Thus, there is provided a tubular body between the at least one electric coil and the addressed part of the inner volume of the process chamber.
In a good embodiment of the just addressed embodiment the vacuum process chamber has an encapsulating wall and the tubular body is a part of the encapsulating wall. Thus, the addressed at least one electric coil does not reside within the inner volume of the vacuum process chamber, but is separate therefrom by the addressed tubular body. Thereby, the addressed at least one electric coil may be integrated into the encapsulating wall of the vacuum process chamber at that locus where the tubular body as well forms part of the addressed encapsulating wall or the addressed electric coil may reside separate from the encapsulating wall, i.e. in the surrounding of the addressed vacuum process chamber.
In a further good embodiment of the system which comprises the addressed tubular body there is provided a slotted tubular shield along the inner surface of the tubular body, whereby the slots or slits of the addressed shield, a multitude thereof being provided, are preferably directed in a direction at least substantially parallel to a central axis of the tubular shield.
In a further good embodiment of the system according to the invention, which may be combined with any system embodiment already addressed and system embodiment still to be addressed, the first Rf power supply source is adapted to generate an Rf power at a frequency fi of
400 kHz≦fi≦27 MHz,
thereby preferably of
400 kHz≦fi≦450 kHz.
In a further good embodiment of the system according to the invention, which may be combined with any system embodiment already addressed and still to be addressed, unless in contradiction, the second Rf power supply arrangement is adapted to generate an Rf voltage ubias of:
35 V≦ubias≦100 V.
In a further good embodiment of the system according to the invention, which may be combined with any system embodiment already addressed and still to be addressed, unless in contradiction, the process control unit is adapted to maintain an operational connection of the electric coil arrangement to an Rf power supply arrangement during the first predetermined timespan.
In a further good embodiment of the system according to the invention, which may be combined with any system embodiment already addressed and still to be addressed, unless in contradiction, the system further comprises a sputtering source for a seed layer material, preferably of W or of Ta2O5. The further sputtering source is provided either within the vacuum process chamber or in a further process chamber remote from the addressed vacuum process chamber.
In a further good embodiment of the system according to the invention, which may be combined with any system embodiment already addressed and still to be addressed, unless in contradiction, the vacuum process chamber is substantially symmetric with respect to a central axis. The at least one electric coil is provided with the coil axis coaxial to the addressed central axis or intersecting said central axis.
The invention shall now be further explained and exemplified with the help of figures. The figures show:
Straight ahead deposition of chalcogenide glass material exhibiting a thermally driven amorphous/crystalline phase-change as of GeSbTe (GST) into vias with an aspect ratio 1:1 as of a via 10 in
For properly and completely filling the via 10 with covering material it is necessary to remove such overhanging material.
One way to do such removing is to apply Rf bias on the substrate to be coated. As a substrate bias usually Rf bias of 13.56 MHz is applied. Thereby, there are two ways to apply Rf substrate bias: Either such Rf bias is permanently applied during deposition of the covering material or such Rf bias is applied intermittent to the material deposition step in a so-called dep-etch process step. It is this latter approach which is taken by the present invention.
Thereby, material—e.g. GST-deposition, is performed without bias, especially without Rf bias, during a first predetermined timespan. Subsequently an Rf bias etch step during a subsequent predetermined timespan is performed. This etching step is followed by a material deposition step. Usually, the first and the last steps, i.e. the deposition steps, are performed by PVD-sputtering and in between there is operated the addressed ICP etch step. The ICP etching step under Rf bias of the substrate may be performed by using a shutter between a target arrangement to perform the material deposition upon the substrate and the substrate, which technique is principally known as under-shutter etch mode.
It is customary to perform the etching step with Rf substrate bias under high voltages of several hundred Volts and at a relatively high pressure in the respective processing chamber in the range of 10−2 mbar, which shows up to be disadvantageous. These high voltages lead to removal of the material from the via bottom covering 20 (see
The inventors of the present invention have found in simulation of etching on vias that low voltages in the range of 35 to 100 V of Rf biasing the substrate are optimal for properly removing overhanging covering material. Thus, they have found how to practice the etching in opposition of customary approaches. This is due to the fact that the sputter yield and thus, in etching, the etching yield is a function of the angle of incidence which depends on etching ion energy. This effect is plotted in
As shown in the
As further schematically shown in
In the sputter deposition step, in which material is sputtered from target 60 and deposited upon substrate 52 and in the respective via, e.g. resulting in a covering profile as depicted in
During this sputter-deposition timespan τSD the induction coil 40 is operationally disconnected from Rf supply source 44, although it might be advantageous to operate the induction coil 40 also during the sputter-deposition step, i.e. during timespan τSD, to control deposition distribution of material sputtered off the target 60 upon the substrate 52.
It has to be noted that embodiments of processing chambers 50a, 50b, 50c as depicted in the
The efficiency of the ICP concept to etch-remove overhanging material is per se known, and published in Appl. Phys. A, DOI 10.1007/s00339-012-7463-8 mentioned above. Thereby, as was addressed, the substrate was transported from a material deposition chamber to an ICP etching chamber and back to the deposition chamber several times. The disadvantage of such process flow is that many transport steps are involved without breaking the vacuum, which transport steps may easily contaminate the substrate or are prone to collect particles. The transport with repeated use of the same chamber as of the addressed article slows down overall processing and has therefore been recognized by the inventors of the present invention to be hardly a solution for industrial production.
According to the present invention the material deposition step or steps and the etching step or steps are performed in one common process chamber as evident from the
As was addressed, the solution of completely filling vias with an aspect ratio substantially of 1:1 with chalcogenide glass material exhibiting a thermally driven amorphous/crystalline phase-change especially of GST is to combine the sputtering step or module for material deposition into the via on one hand with the low voltage ICP sputter-etching step or module working at a pressure of less than 10−3 mbar in a common process chamber, on the other hand thereby, in a good embodiment the vacuum processing chamber, wherein both sputter-deposition as well as ICP etching is performed, is dimensioned as a medium-throw setup chamber.
According to the chamber embodiment shown in the
The target arrangement of one target 60 or of more than one target 60a, 60b, e.g. as of
The cover part, being plane or dome-shaped, transits into the lateral wall of the common vacuum process chamber along a substantially circular area as exemplified by area 70 in the
1≦Ri/d≦1.6.
E.g. for the chamber embodiment of
As was addressed in context with
Since especially by the sputter-deposition process a conductive layer material is produced, the ceramic tube 44 has to be protected. This is performed by a slotted shield 44 which has slots directed in axial direction with respect to the axis of the coil 42. By this it is prevented that a closed loop of conductive material is formed on the ceramic tube 42, which would shield the inductive coupling from the coil 42 into the vacuum process chambers 50 to 50c.
The overall process of filling vias according to the invention consists of a number of n cycles, where n is in the range of 1 to 10. The first cycle consists of a deposition, an ICP etching and a deposition step. Subsequent cycles consist of an ICP etching and a deposition step. As was already addressed, the sputter-deposition step is performed by DC sputtering, which may include DC pulsed sputtering and is run at a higher pressure than the ICP etching step. This is shown in
With an eye on
As has been addressed in context with
In many cases it may be an advantage to use a shutter 46 as schematically shown in the embodiment of
In the embodiment of
There are several advantages to use more than one sputtering source and thus more than one target:
The induction coil 40 with the ceramic tubular body 42 and shield 44 may be implemented around the whole chamber diameter as in the embodiments of
For further reducing the risk that a void within the material covering of the via becomes closed towards the surrounding as e.g. shown in
As a material for such a seed or wetting layer, sputtered W or reactively sputtered Ta2O5 may be used, especially if the material to be deposited for filling the via is GST. Thereby, in a today preferred embodiment Ta2O5 is preferred as seed layer material since it has been shown to provide an excellent adhesion and it suppresses heat diffusion from GST material. A low heat transfer improves the performance of the phase transition device as is reported in Matsui et al. “Ta2O5 Interfacial Layer between GST and W Plug enabling Low Power Operation of Phase Change Memories”, Electron Devices Meeting, 2006. IEDM '06. International, vol. No., pp. 1, 4, 11-13, Dec. 2006, doi: 10.1109/IEDM.2006.346908.
The seed layer can be deposited in a separate vacuum processing chamber prior to introducing the resulting substrate with applied wetting layer to the one vacuum process chamber for sputter-deposition and ICP etching. Such seed layer is deposited with a thickness in the range of 0.5 nm to 5 nm (both limits included), depending on the quality of the via.
If a multi-source setup is used, i.e. with more than one sputtering target, an additional PVD source can be applied in the one common vacuum process chamber according to the invention so as to deposit the seed layer before material sputter-deposition is initiated. Such a multi-source layout is most schematically shown in
Just as examples repeating some aspects of the present invention:
Filing Document | Filing Date | Country | Kind |
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PCT/EP2014/060620 | 5/23/2014 | WO | 00 |
Number | Date | Country | |
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61826592 | May 2013 | US |