Claims
- 1. A method for forming an integrated circuit comprising:
- forming a insulation layer over a surface of a semiconducting surface of a body;
- planarizing said insulation layer;
- forming a metallization layer over said insulation layer;
- patterning said metallization layer to form a plurality of metal signal lines;
- forming a first conformal interlevel dielectric over said metallization layer and over said insulation layer so as to form sealed voids in said first conformal interlevel dielectric between at least some adjacent metal signal lines;
- removing an upper portion of said first conformal interlevel dielectric to achieve a planar top surface, thereby exposing a first group of voids at the planar top surface and maintaining a second group of voids sealed at a depth below the planar top surface;
- depositing a first flowable dielectric on the planar top surface of said first conformal interlevel dielectric filling the first group of voids; and,
- forming a second conformal interlevel dielectric over said first flowable dielectric.
- 2. The method of claim 1, wherein said insulation layer comprises an oxide.
- 3. The method of claim 2, wherein said oxide is doped.
- 4. The method of claim 1, wherein said planarizing step comprises chemical mechanical polishing.
- 5. The method of claim 1, wherein said planarizing step comprises sacrificial flowable dielectric etchback.
- 6. The method of claim 1, wherein said planarizing step comprises resist etchback.
- 7. The method of claim 1, wherein said metallization layer comprises aluminum.
- 8. The method of claim 1, wherein said step of forming said first conformal interlevel dielectric comprises a chemical vapor deposition.
- 9. The method of claim 1, wherein said step of forming said first conformal interlevel dielectric comprises a high density plasma deposition.
- 10. The method of claim 1, wherein said first conformal interlevel dielectric comprises a fluorinated silicone dioxide.
- 11. The method of claim 1, wherein said first conformal interlevel dielectric is deposited such that said first conformal interlevel dielectric can be etched back such that a threshold thickness of said first conformal interlevel dielectric extends above each said sealed void.
- 12. The method of claim 1, further comprising performing an etchback of said first conformal interlevel dielectric, wherein said step of performing an etchback is performed before said step of depositing said first flowable dielectric.
- 13. The method of claim 12, wherein said first conformal interlevel dielectric extends above each one of said plurality of metal signal lines such that a threshold thickness of said first conformal interlevel dielectric extends above each said sealed void.
- 14. The method of claim 12, wherein said first conformal interlevel dielectric is etched back to a thickness between 0.5 .mu.m and 1.5 .mu.m above said metallization layer.
- 15. The method of claim 12, wherein said step of performing an etchback comprises a chemical mechanical polish etchback.
- 16. The method of claim 12, wherein said step of performing an etchback comprises a sacrificial flowable dielectric etchback.
- 17. The method of claim 12, wherein said step of performing an etchback comprises a resist etchback.
- 18. The method of claim 12, further comprising:
- depositing a second flowable dielectric;
- wherein said step of depositing a second flowable dielectric is performed after said step of forming said first conformal interlevel dielectric and before said step of performing said etchback of said first conformal interlevel dielectric; and,
- vacuum curing said second flowable dielectric.
- 19. The method of claim 18, wherein said etchback is performed such that said second flowable dielectric is etched back from above said first conformal interlevel dielectric.
- 20. The method of claim 18, wherein said step of performing said etchback further comprises an etchback having 1 to 1 selectivity of said first conformal interlevel dielectric and said second flowable dielectric.
- 21. The method of claim 18, further comprising:
- depositing a third flowable dielectric;
- wherein said step of depositing said third flowable dielectric is performed after said step of depositing said second flowable dielectric and before said step of performing said etchback of said first conformal interlevel dielectric;
- vacuum curing said third flowable dielectric; and,
- wherein said etchback is performed such that said third flowable dielectric is etched back from above said first conformal interlevel dielectric.
- 22. A method according to claim 12, wherein each said void formed in each one of said plurality of intermetal spacings having a width below a threshold width is sealed.
- 23. The method of claim 22, wherein each said void formed in each one of said plurality of intermetal spacings having a width of at least said threshold width contains a flowable dielectric.
- 24. The method of claim 23, wherein said flowable dielectric comprises a silicon dioxide.
- 25. A method according to claim 12, wherein said first conformal interlevel dielectric is etched back to a thickness such that all said voids are exposed.
- 26. The method of claim 1, further comprising performing an etchback of said first flowable dielectric, wherein said step of performing said etchback of said first flowable dielectric is after said step of depositing said first flowable dielectric, and before said step of forming said second conformal interlevel dielectric.
- 27. The method of claim 1, wherein a threshold combined thickness of said first conformal interlevel dielectric and said second conformal interlevel dielectric extends above each said sealed void.
- 28. The method of claim 1, wherein said second conformal interlevel dielectric extends approximately 0.8 .mu.m to 1.5 .mu.m above said metallization layer.
- 29. The method of claim 1, wherein said second conformal interlevel dielectric extends approximately 500 .ANG. to 5000 521 above said first conformal interlevel dielectric.
- 30. The method of claim 1, wherein said second conformal interlevel dielectric has a thickness such that said flowable dielectric exposed in a via, formed between an upper surface of said second conformal interlevel dielectric and one of said plurality of metal lines, is at most a threshold distance from an upper edge of said via.
- 31. The method of claim 1, wherein said step of depositing said second conformal interlevel dielectric comprises a high density plasma deposition method.
- 32. The method of claim 1, wherein said step of depositing said second conformal interlevel dielectric comprises a chemical vapor deposition.
- 33. The method of claim 1, wherein said second conformal interlevel dielectric is a fluorinated silicon dioxide.
Parent Case Info
This is a Division of application Ser. No. 08/534,669, filed Sep. 27, 1995 now U.S. Pat. No. 5,847,464.
US Referenced Citations (11)
Foreign Referenced Citations (1)
Number |
Date |
Country |
0 327 412 A1 |
Aug 1989 |
EPX |
Divisions (1)
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Number |
Date |
Country |
Parent |
534669 |
Sep 1995 |
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