Patent Application
20160268134
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2015-045977, filed Mar. 9, 2015, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device in which a nitride semiconductor is used.
Some uses of nitride semiconductors include high frequency electronic devices and power devices, as well as light-emitting diodes (LEDs) that are semiconductor light-emitting elements in a display device, illumination device, and the like.
A semiconductor device in which a nitride semiconductor is used has a stacked structure in which, for example, a plurality of nitride semiconductor layers including p-type nitride semiconductor layers and n-type nitride semiconductor layers are stacked one over the other on a silicon substrate. This stacked structure is formed by epitaxial growth of the nitride semiconductor layers. When the p-type nitride semiconductor layer is formed, the semiconductor device is taken out of a reactor and is heated, for example, in order to activate p-type impurities with which the nitride semiconductor layer is doped. Accordingly, regrowing of a further epitaxial layer is required when an n-type nitride semiconductor layer is to be formed on the p-type nitride semiconductor layer. During the regrowing, the main face of the exposed nitride semiconductor layer may become contaminated, and a favorable p-n junction may not be obtained at the interface of the two layers.
One embodiment provides a method for manufacturing a semiconductor device that enables forming of two nitride semiconductor layers of different conductivity types which have a favorable junction and favorable junction characteristics.
In general, according to one embodiment, a method for manufacturing a semiconductor device includes: forming, on a first substrate, a first conductivity type first nitride semiconductor layer containing gallium nitride, wherein the main face of the first nitride semiconductor layer on a side thereof opposite to the first substrate has a (0001) face, forming, on a second substrate, a second conductivity type second nitride semiconductor layer containing gallium nitride, and a main face of the second nitride semiconductor layer on a side thereof opposite to the second substrate has a (000-1) face, and bonding the first nitride semiconductor layer and the second nitride semiconductor together by heating them in a state where the first nitride semiconductor layer faces and is located against the second nitride semiconductor layer.
Embodiments will be described hereinafter with reference to the drawings. Since the drawings are schematically or conceptually illustrated, dimensions and proportions in each drawing may not necessarily be the same as the dimensions and proportions of an actual device. One or more embodiments described below merely illustrate devices and methods in order to implement the technical idea of the invention. Therefore, the technical idea of the invention is not specified by the shape, the structure, and the disposition of components in the embodiments. In the description below, configurations having the same function and configuration are given the same reference sign, and a duplicate description will be provided for those configurations only when necessary.
A description will be provided for a method of manufacturing a semiconductor device 1 according to a first embodiment with reference to the drawings.
A semiconductor device 1 provided with a p-type nitride semiconductor layer 13 as the uppermost layer on a substrate is formed as illustrated in
Next, a buffer layer 11 is formed on the substrate 10 using MOCVD. The buffer layer 11 includes a nitride semiconductor and the like. For example, the buffer layer 11 is formed of aluminum nitride (AlN). The buffer layer has the functions of alleviating strain that is caused by the difference in lattice constant between a nitride semiconductor layer formed on the buffer layer and the substrate and of controlling the crystallinity of the nitride semiconductor layer formed on the buffer layer. The buffer layer also has a function of suppressing a chemical reaction between the elements (for example, gallium (Ga)) that are contained in the nitride semiconductor layer formed on the buffer layer and the elements (for example, silicon (Si)) in the substrate. The buffer layer 11 may not need to be provided depending on the composition of the substrate used.
Next, an n+-type nitride semiconductor layer 12 doped with a high-concentration n-type dopant is formed on the buffer layer 11 using MOCVD. The nitride semiconductor layer 12 is formed of, for example, gallium nitride (GaN). Silicon (Si), for example, is used as the n-type dopant.
Next, a nitride semiconductor layer 13 doped with a p-type dopant is formed on the n+-type GaN layer 12 by using MOCVD. The nitride semiconductor layer 13 is formed of, for example, GaN. Magnesium (Mg), for example, is used as the p-type dopant.
GaN has the crystal structure of a hexagonal crystal system. Since it has lattice polarities in the c-axis direction, GaN has two c faces consisting of a (0001) face and a (000-1) face. The (0001) face and the (000-1) face may be referred respectively to as a +c face and a −c face. The (0001) face of GaN is a gallium face (Ga face) in which gallium atoms are disposed. The (000-1) face of GaN is a nitrogen face (N face) in which nitrogen atoms are disposed. In the present embodiment, the GaN layer 13 is formed so that the main face, i.e., the face not facing the underlying substrate, of the GaN layer 13 is the Ga face. The crystalline structure of the GaN layer 13 is controlled by the n+-type GaN layer 12 below the GaN layer 13 (or a layer further below). The n+-type GaN layer 12 is formed so that the main face of the n+-type GaN layer 12 is the Ga face. Accordingly, the GaN layer 13 that is grown on the n+-type GaN layer 12 is formed so that the main face of the GaN layer 13 is the Ga face.
Next, the semiconductor device 1 is heated, for example, at 500° C. for five minutes in a nitrogen atmosphere, and the p-type impurity in the GaN layer 13 is activated. Accordingly, the p-type GaN layer 13 is formed. The dopant concentration (or the carrier concentration) in the p-type GaN layer 13 can be arbitrarily set based on the quantity of p-type dopants incorporated therein during deposition of the layer.
Next, a semiconductor device 2 provided with an n−-type nitride semiconductor layer 23 in the uppermost layer is formed as illustrated in
Next, an n+-type nitride semiconductor layer 22 doped with a high-concentration n-type impurity is formed on the buffer layer 21 using MOCVD. The nitride semiconductor layer 22 is formed of, for example, GaN.
Next, the n−-type nitride semiconductor layer 23 doped with a low-concentration n-type impurity is formed on the n+-type GaN layer 22 using MOCVD. The nitride semiconductor layer 23 is formed of, for example, GaN. A GaN layer is n−-type when epitaxially grown in an undoped state, i.e., without the purposeful addition of dopant additives. Thus, the nitride semiconductor layer 23 may not be intentionally doped with an n-type impurity when a GaN layer is used as the nitride semiconductor layer 23. The impurity concentration in the GaN layer 23 may be adjusted by doping the GaN layer 23 with an n-type impurity. The undoped state means that a semiconductor is not intentionally doped with impurities. A layer having an amount of unintentionally incorporated impurities that may be introduced during, for example, manufacturing, is considered to be in the undoped state.
The GaN layer 23 is formed so that the main face (top face) of the GaN layer 23 is the N face. The crystal structure of the GaN layer 23 is controlled by the n+-type GaN layer 22 below the GaN layer 23 (or a layer further below). The n+-type GaN layer 22 is formed so that the main face of the n+-type GaN layer 22 is the N face. Accordingly, the n−-type GaN layer 23 that is grown on the n+-type GaN layer 22 is formed so that the main face of the n−-type GaN layer 23 is the N face.
Next, as illustrated in
Next, the p-type GaN layer 13 and the n−-type GaN layer 23 are bonded together, for example, by heating the stacked structure at 500° C. for 60 minutes (step S103). Since the main face of the p-type GaN layer 13 is the Ga face, and the main face of the n−-type GaN layer 23 is the N face, a favorable junction is obtained at the interface between the p-type GaN layer 13 and the n−-type GaN layer 23 because GaN can form at the junction. The bonding is desirably performed in a vacuum state. Accordingly, discontinuities in the interface between the p-type GaN layer 13 and the n−-type GaN layer 23 can be reduced, and thus a favorable junction obtained. The top face of the p-type GaN layer 13 and the top face of the n−-type GaN layer 23 are desirably cleaned before the bonding. Accordingly, impurities included in the interface between the p-type GaN layer 13 and the n−-type GaN layer 23 can be reduced.
Next, the substrate 20 and the buffer layer 21 are removed as illustrated in
The configuration of the plurality of nitride semiconductor layers with which the semiconductor device 1 is provided is set depending on the types of the finally manufactured semiconductor element. For example, when an n+-type GaN layer 22 on the n−-type GaN layer 23 is not necessary, the n+-type GaN layer 22 is not formed, and the n−-type GaN layer 23 is formed on the buffer layer 21 in the step S101. As such, the configuration of the plurality of nitride semiconductor layers with which the semiconductor device 1 is provided can be arbitrarily designed.
Effect
In the first embodiment, as described above in detail, the semiconductor device 1 provided with the p-type nitride semiconductor layer (p-type GaN layer) 13 in the uppermost layer and the semiconductor device 2 provided with the n−-type nitride semiconductor layer (n−-type GaN layer) 23 in the uppermost layer are formed. The p-type GaN layer 13 is formed so that the main face of the p-type GaN layer 13 is the Ga face. The n−-type GaN layer 23 is formed so that the main face of the n−-type GaN layer 23 is the N face. The p-type GaN layer 13 and the n−-type GaN layer 23 are bonded together by heating while the p-type GaN layer 13 faces and contacts the n−-type GaN layer 23.
According to the first embodiment, since the Ga face of the p-type GaN layer 13 comes in contact with the N face of the n−-type GaN layer 23, the p-type GaN layer 13 and the n−-type GaN layer 23 can be bonded together. In addition, since the Ga face of the p-type GaN layer 13 and the N face of the n−-type GaN layer 23 are bonded together, a stacked structure of the p-type GaN layer 13 and the n−-type GaN layer 23 having a favorable junction surface can be formed.
The stacked structure of the p-type GaN layer 13 and the n−-type GaN layer 23 can be formed through bonding. In addition, a p-type GaN layer as an intermediate layer can be formed within the plurality of stacked nitride semiconductor layers.
The p-type dopant included in the p-type GaN layer 13 can be activated through, for example, heating before bonding. Accordingly, a p-type GaN layer 13 having favorable characteristics can be formed. When an n-type GaN layer is present on a GaN layer that is doped with a p-type impurity (for example, magnesium (Mg)), dehydrogenation of the Mg doped GaN does not proceed, and the GaN layer may not be p-type. In addition, controlling the impurity profile in the stacked structure is difficult because magnesium (Mg) as a dopant is likely to be diffused and segregated during crystal growth. However, in the present embodiment, such a problem can be avoided.
In general, when an n−-type GaN layer is formed on a p-type GaN layer through epitaxial growth after an anneal or heating step, or after exposure of the substrate to an environment outside of the epitaxial growth chamber, the junction surface is contaminated by impurities such as silicon (Si), oxygen, and carbon, and a favorable junction is not obtained. Meanwhile, in the present embodiment, a p-n junction between a p-type GaN layer and an n−-type GaN layer can be formed without the need for epitaxial growth following the anneal or heating step. The amount of impurities in the interface between the p-type GaN layer 13 and the n−-type GaN layer 23 can be further reduced by bonding the p-type GaN layer 13 and the n−-type GaN layer 23 in a vacuum state after the top faces of the p-type GaN layer 13 and the n−-type GaN layer 23 are cleaned. Accordingly, a favorable p-n junction can be formed.
A semiconductor device 1 provided with the p-type nitride semiconductor layer 13 partially disposed on the n+-type nitride semiconductor layer 12 and a semiconductor device 2 provided with the n−-type nitride semiconductor layer 23 partially disposed on the n+-type nitride semiconductor layer 22 are formed in a second embodiment. Then, a face of the p-type nitride semiconductor layer 13 is brought into contact with a face of the n−-type nitride semiconductor layer 23, and the p-type nitride semiconductor layer 13 and the n−-type nitride semiconductor layer 23 are bonded together in the in-plane direction.
A description will be provided for a method for manufacturing the semiconductor device 1 according to the second embodiment with reference to the drawings.
The semiconductor device 1 provided with the p-type GaN layer 13 in the uppermost layer is formed in the same manner as the first embodiment (step S200). The p-type GaN layer 13 is formed so that the main face of the p-type GaN layer 13 is the Ga face. The n+-type GaN layer 12 is also formed so that the main face of the n+-type GaN layer 12 is the Ga face.
Next, the p-type GaN layer 13 is processed (step S201). That is to say, a resist layer (patterned mask layer) 14 that partially covers the main face of the p-type GaN layer 13 is formed by photolithography as illustrated in
Next, the semiconductor device 2 provided with the n−-type GaN layer 23 in the uppermost layer is formed in the same manner as the first embodiment (step S202). The n−-type GaN layer 23 is formed so that the main face of the n−-type GaN layer 23 is the N face. The n+-type GaN layer 22 is also formed so that the main face of the n+-type GaN layer 22 is the N face. Furthermore, the thickness of the n−-type GaN layer 23 is set to be approximately the same as the thickness of the p-type GaN layer 13.
Next, the n−-type GaN layer 23 is processed (step S203). That is to say, a resist layer (patterned mask layer) 24 that covers a partial area of the main face of the n−-type GaN layer 23 is formed by photolithography as illustrated in
When the p-type GaN layer 13 is processed in order to remain at the left on the n+-type GaN layer 12 as illustrated in
Next, the side face of the p-type GaN layer 13 is brought into contact with the side face of the n−-type GaN layer 23 as illustrated in
Next, the side face of the p-type GaN layer 13 and the side face of the n−-type GaN layer 23 are bonded together by heating (step S205), and the main surfaces of the n−-type GaN layer 23 and the n+-type GaN layer 22, as well as the n+-type GaN layer 22 and the p-type GaN layer 13, are bonded together. Since the p-type GaN layer 13 the Ga face of which is grown and the n−-type GaN layer 23 the N face of which is grown are bonded together in the in-plane direction at this time, a favorable junction surface is obtained in the interface between the p-type GaN layer 13 and the n−-type GaN layer 23. In addition, since the main face of the p-type GaN layer 13 is the Ga face, and the main face of the n+-type GaN layer 22 is the N face, a favorable junction surface is obtained in the interface between the p-type GaN layer 13 and the n+-type GaN layer 22. Similarly, since the main face of the n−-type GaN layer 23 is the N face, and the main face of the n+-type GaN layer 12 is the Ga face, a favorable junction surface is obtained in the interface between the n−-type GaN layer 23 and the n+-type GaN layer 12.
Next, the substrate 20 and the buffer layer 21 are removed as illustrated in
Effect
According to the second embodiment, as described above in detail, the side face of the p-type GaN layer 13 and the side face of the n−-type GaN layer 23 can be bonded together through bonding. In addition, the n+-type GaN layer 22 can be formed on the p-type GaN layer 13. Other effects are the same as the effects of the first embodiment.
The configuration in
In a third embodiment, a description will be provided for a configuration example of the semiconductor device in which the p-n junction that is formed according to the first and the second embodiments is used. Two examples (first and second examples) will be described hereinafter.
A first example is a configuration example of a vertical power metal oxide semiconductor field-effect transistor (MOSFET) that is the semiconductor device to which the p-n junction in the second embodiment is applied.
The semiconductor device 1 is provided with the substrate 10, the buffer layer 11, the n+-type drain layer 12, the p-type base layer 13, the n−-type drift layer 23, an n+-type source region 30, a gate insulating film 31, a gate electrode 32, a source electrode 33, and a drain electrode 34.
The drain layer 12 is disposed on the buffer layer 11. The drain layer 12 is an n+-type nitride semiconductor layer. In the present example, the drain layer 12 is an n+-type GaN layer. The drain layer 12 is electrically connected to the drain electrode 34. The drain electrode 34 is disposed on the bottom face of the substrate 10 and comes in contact with the drain layer 12 through an opening portion that is disposed through the substrate 10 and the buffer layer 11.
The base layer 13 and the drift layer 23 are disposed on the drain layer 12. The base layer 13 and the drift layer 23 are bonded together in the in-plane direction in the same manner as the second embodiment. The base layer 13 is a p-type nitride semiconductor layer. In the present example, the base layer 13 is a p-type GaN layer. The drift layer 23 is an n−-type nitride semiconductor layer. In the present working example, the drift layer 23 is an n−-type GaN layer.
The source region 30 is disposed in the base layer 13 and includes an n+-type semiconductor region. The source region 30 is formed by implanting ions of an n-type impurity into the base layer 13. The source electrode 33 is disposed on the source region 30.
The gate insulating film 31 is disposed on the base layer 13 in order to be in contact with the source region 30 and the drift layer. The gate electrode is disposed on the gate insulating film 31.
The semiconductor device (vertical power MOSFET) 1 according to the first example is configured as above.
A second example is a configuration example of a bipolar transistor that is the semiconductor device to which the p-n junction in the first embodiment is applied.
The semiconductor device 1 is provided with the substrate 10, the buffer layer 11, the n+-type collector layer 12, the p-type base layer 13, the n−-type emitter layer 23, the n+-type contact layer 22, a base electrode 40, an emitter electrode 41, and a collector electrode 42.
The collector layer 12 is disposed on the buffer layer 11. The collector layer 12 is an n+-type nitride semiconductor layer. In the present example, the collector layer 12 is an n+-type GaN layer. The collector layer 12 is electrically connected to the collector electrode 42. The collector electrode 42 is disposed on the bottom face of the substrate 10 and comes in contact with the collector layer 12 through an opening portion that is disposed in the substrate 10 and the buffer layer 11.
The base layer 13 is disposed on the collector layer 12. The base layer 13 is a p-type nitride semiconductor layer. In the present example, the base layer 13 is a p-type GaN layer.
The emitter layer 23 and the base electrode 40 are disposed on the base layer 13 at an interval therebetween. The emitter layer 23 is an n−-type nitride semiconductor layer. In the present example, the emitter layer 23 is an n−-type GaN layer.
The contact layer 22 is disposed on the emitter layer 23. The contact layer 22 is an n+-type nitride semiconductor layer. In the present example, the contact layer 22 is an n+-type GaN layer. The emitter electrode 41 is disposed on the contact layer 22.
The semiconductor device (bipolar transistor) 1 according to the second example is configured as above.
According to the third embodiment, as described in detail so far, various semiconductor devices can be configured by using the p-n junction that is described in the first and the second embodiments. In addition to the semiconductor devices illustrated in the third embodiment, various semiconductor devices can be configured by applying the p-n junction that is described in the first and the second embodiments.
In each embodiment above, a p-type GaN layer the Ga face of which is exposed as the main face and an n−-type GaN layer the N face of which is exposed as the main face are bonded together. However, not limited to this configuration, an n−-type GaN layer the Ga face of which is exposed as the main face and a p-type GaN layer the N face of which is exposed as the main face may be bonded together.
While MOCVD is used for depositing in each embodiment above, depositing is not limited to MOCVD. Other deposition methods such as molecular beam epitaxy (MBE) may also be used.
In the present specification, the term “nitride semiconductor” includes semiconductors having all possible compositions obtained from a chemical formula InxAlyGa(1-x-y)N (where 0≦x<1, 0≦y<1, and 0≦x+y<1) by changing the composition ratio of x and y within each range thereof. The term “nitride semiconductor” also includes semiconductors that further include Group V elements other than nitrogen (N), semiconductors that further include various elements which are added in order to control various characteristics such as a conductivity type, and semiconductors that further include various elements which are contained unintentionally in the above chemical formula.
In the present specification, the expression “stacked layers” includes, in addition to a case where layers are stacked in contact with each other, a case where layers are stacked while other layers are inserted between the layers. In addition, the expression “disposed on” includes, in addition to a case where one layer is disposed on another in direct contact, a case where one layer is disposed on another while other layers are inserted between the layers.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015-045977 | Mar 2015 | JP | national |
