Patent Application
20050263903
The present invention is directed to the formation of structural features on a substrate, and is more particularly directed to formation of a transistor on a flexible polymeric substrate.
Conventional photolithographic patterning techniques used in patterning wafers tends to be time consuming and costly. A significant portion of the cost and time associated with conventional photolithography is the development and fabrication of a mask. Another significant portion of the costs relate to investment costs, for example, capital equipment (e.g. a mask aligner) and higher material costs especially for photomasks and photoresists. Other significant costs contributing to the total costs of using photolithography as a patterning technique are associated with material handling, for example, material collection and disposal for waste solvents and photoresist.
Recent developments in integrated circuit fabrication techniques have reduced or overcome the burdens of long lead times and fabrication costs associated with the use of conventional masks. Such developments include electrophotographic imaging techniques for pattern formation, contact hole opening, and device isolation on a substrate. Electrophotographic imaging techniques use an image forming apparatus to apply electrophotographic imaging compounds, such as dry toner, to a substrate. The application of the electrophotographic imaging compounds to the substrate forms a mask suitable for use in forming structural patterns or features of an integrated circuit. As with most electrophotographic imaging techniques the desired pattern is first created on an electronic device, such as a computer and when completed, is transferred to the image forming apparatus for imaging on a selected medium or substrate. Masks of electrophotographic imaging compounds toner have been applied to glass substrates, polymeric substrates, both flexible and in rigid polymeric with modest success.
One burden of forming a mask with an electrophotographic imaging compound on a polymeric substrate is the adhesion of an initial conductive layer in a stack-up to a surface of the polymeric substrate. More specifically, the initial conductive layer in contact with the polymeric substrate tends to delaminate therefrom. This fact is particularly burdensome when the polymeric substrate is a flexible polymeric substrate.
The delamination of the initial conductive layer in contact with the surface of the polymeric substrate causes entire portions of stack up to lift from the substrate introducing quality and reliability issues in electronic goods. There accordingly exists a need in the art for improving the adhesion of an initial conductive layer in a stack-up of an integrated circuit or an electronic circuit to a polymeric substrate.
The present invention addresses the above described limitations of forming an integrated circuit or an electronic circuit on a polymeric substrate. A method and electronic circuit is described herein that provides an approach to form an adhesion layer in contact with a surface of the polymeric substrate and a surface of a first conductive layer to improve the adhesion of the first conductive layer of the electronic circuit or integrated circuit to the polymeric substrate.
In one illustrative embodiment of the present invention, a method for forming a conductive element on a first surface of a substrate is disclosed. The method includes steps of forming an adhesion layer on a portion of the first surface of the substrate and forming the conductive element on the adhesion layer. The method can further include a step of forming a mask of an electrophotographic imaging compound on the first surface of the substrate and heating the substrate with the mask formed thereon to an elevated temperature for a selected period of time.
The method can further include a step of removing at least a portion of the mask from the first surface of the substrate. In one aspect of the present invention, a stiffener is provided and the substrate is affixed thereto to stiffen the substrate during the step of forming the mask on the selected surface of the substrate and if desired to stiffen the substrate during the formation of the adhesion layer, and if desired during formation of the conductive element on the adhesion layer.
The method can also include steps to form a double sided electronic circuit. By performance of the steps of forming, an adhesion layer on a portion of a second surface of the substrate and forming a conductive element on the adhesion layer formed on the second surface of the substrate the present invention is well suited for use in producing double sided electronic circuits.
The method disclosed herein can further include a step of forming a dielectric layer on a portion of the first surface of the substrate. The dielectric layer can include silicon nitride (SiNx), silicon nitride (Si3N4), silicon dioxide (SiO2) or another suitable material for use as a dielectric layer. Suitable methods for forming the adhesion layer include, but are not limited to electron deposition, thermal deposition, sputtering, plasma deposition, plating, either with an electrode or in an electrodeless manner, spraying, or other suitable technique. A substrate suitable for use with the method of the present invention can be rigid or flexible and can include materials such as one or more polymers, glass, silicon, lignocellulosic, fabric or other conventional substrate material such as gallium arsenide (GaAs) and variations thereof.
In another illustrative embodiment of the present invention, an electronic circuit is disclosed. The electronic circuit includes a substrate, an adhesion layer in contact with a portion of a first surface of the substrate, and a conductive path in contact with a portion of the adhesion layer. The conductive path couples a portion of a first electronic device of the electronic circuit to a second portion of a second electronic device of the electronic circuit.
The electronic circuit can further include a dielectric layer in contact with a portion of the substrate and a portion of the adhesion layer. Further, the electronic circuit can be a double sided electronic circuit with an adhesion layer in contact with a portion of a second surface of a polymeric substrate and a conductive path in contact with a portion of the adhesion layer in contact with the portion of the second surface of the substrate. The conductive path couples a portion of a third electronic device of the electronic circuit to a fourth electronic device of the electronic circuit.
In one illustrative embodiment of the present invention a method for forming a transistor on a flexible substrate is disclosed. The method includes the steps of imaging the flexible substrate with an image forming apparatus to form a plurality of masks and forming a gate, a drain, and a source of the transistor on the flexible substrate according to the features defined by the plurality of masks. Each of the masks define one or more features of the transistor.
The method can further include a step of forming a first insulator layer on a first surface of the flexible substrate. The method can further include an additional step of forming a second insulator layer on a second surface of the flexible substrate. Further, the method can include a step of removing at least a portion of each of the masks to expose desired features of the transistor.
The method can further include the steps of affixing the substrate to a stiffener and forming a plurality of metallized layers on the flexible substrate to form a plurality of contact regions.
In another illustrative embodiment of the present invention, a method for forming an array of transistors is disclosed. Performance of the method forms a first metallized layer on a portion of a first surface of a flexible substrate. Further performance of the method forms a first dielectric layer on a portion of the first surface of the flexible substrate and on a plurality of surfaces of the first metallized layer. Still further, performance of the method forms a first conductor layer on a surface of the first dielectric layer and forms a second conductive layer on a portion of a surface of the first conductive layer. Further performance of the method forms a second metallized layer on portions of the second conductive layer.
The method can further include the steps of forming a first insulator layer on a first surface of the flexible substrate and forming a second insulator layer on a second surface of the flexible substrate.
In one embodiment of the present invention, a method for forming a conductive element on a lignocellulosic substrate is disclosed. The method includes steps of forming a mask of an electrophotographic compound on a lignocellulosic substrate defining a conductive element and forming the conductive element on the lignocellulosic substrate as defined by the mask. The method can further include the step of forming an adhesion layer on the lignocellulosic substrate as defmed by the mask.
In another embodiment of the present invention, an electronic circuit is disclosed. The electronic circuit includes a lignocellulosic substrate, an adhesion layer in contact with a portion of the first surface of the lignocellulosic substrate, and a conductive path in contact with a portion of the adhesion layer. The conductive path couples a portion of a first electronic device of the electronic circuit to a portion of a second electronic device of the electronic circuit.
In another embodiment of the present invention, an electronic display is disclosed. The electronic display includes an electrophotographically imaged backplane formed on a lignocellulosic substrate, an electrophoretic display medium coupled to the electrophotographically imaged backplane, and a common electrode coupled to the electrophoretic display medium.
The foregoing and other objects, features and advantages of the invention will be apparent from the following description and apparent from the accompanying drawings, in which like reference characters refer to the same parts throughout the different views. The drawings illustrate principals of the invention and, although not to scale, show relative dimensions.
The present invention is directed to an electronic circuit having an adhesion layer in contact with a surface of a substrate and a surface of a conductive element and to a method for forming the adhesion layer and the conductive element on the substrate. The formation of the adhesion layer is accomplished by imaging a mask of an electrophotographic imaging compound onto a substrate using an image forming apparatus, and forming the adhesion layer on the mask and the substrate, and, in turn, forming the conductive element on the adhesion layer. The mask provides the desired structural pattern for the resulting conductive element. The adhesion layer is formed from a material, for example, titanium (Ti), chromium (Cr), nickel (Ni), aluminum (Al), copper (Cu), silicon dioxide (SiO2), silicon nitrate (SiNx), or other suitable material or compound having properties or a structure well suited for adhering to a surface of a selected substrate type. In this manner, the conductive element adheres to the adhesion layer, which, in turn adheres to the surface of the substrate to provide an approach that improves the lamination of a conductive element to a substrate surface in an electronic circuit.
Before proceeding with the remainder of the detailed description, it is first helpful to define a few terms used throughout the disclosure.
As used herein, the term “image forming apparatus” refers to an apparatus or device for depositing on a medium an electrophotographic imaging compound.
Examples of an image forming apparatus include, but are not limited to, a laser printer, a xerographic imaging device, a facsimile machine, and other like apparatuses or devices that form an image on a medium using electrophotographic imaging compounds.
As used herein, the term “conductive element” refers to a conductive path, a portion of a conductive path, an electronic device, or a portion of an electronic device, formed from a conductive or semiconductive material or compound. The conductive path or portion of a conductive path provides a transmission medium capable of transmitting an analog signal, a digital signal, or a power signal alone or as part of a power grid, or as a conductive path to ground or a portion of a ground plane.
As used herein, the term “electronic device” refers a transistor, a portion of a transistor such as a gate, drain or source, an inductor, a capacitor, or a resistor.
As used herein, the term “organic solvent” includes any non-aqueous solution chosen from the ketone group, such as acetone, methylisobutyl ketone; the aromatic solvent group, such as toluene, xylene; the ester group, such as ethyl acetate, methoxyproply acetate; the ether group, such as diethyl ether; and other solvents such as dimethyl formamide, N-methylpyrolidone, or gamma-butyrolactone.
As used herein, the term “substrate” refers to a rigid substrate with little or no ability to flex in any number of dimensions or to a substrate having properties that allow the substrate to flex (i.e. conformable) in a plurality of dimensions. Examples of substrates include, but are not limited to, silicon substrates, glass substrates, glass foil substrates, polymeric substrates, gallium arsenide substrates, indium phosphate, and other like substrates. Examples of electrophotographic patterning on glass foil are discussed in detail in U.S. Pat. No. 6,080,606, entitled “Electrophotographic Patterning of Thin Film Circuits”, the contents of which are incorporated herein by reference.
As used herein, the term “polymeric substrate” or “flexible polymeric substrate” includes such polymers as polyimides, polyvinyls, polybenzimideazoles, polyesters, polyacrylates, polyamides, polybenzimidazole, celluloid, or other polymers suitable for use in the fabrication of an electronic circuit.
As used herein, the term “material source” includes such material sources as electron beam systems, thermal evaporation systems, chemical vapor deposition tools, enhanced chemical vapor deposition tools, sputtering systems, spray systems, platting systems including electrode platting systems and electrodeless plating systems and other like systems capable of depositing one or more selected materials of compounds on a substrate.
The electronic device 12 includes a processor 18 for executing various instructions and programs, and controlling various hardware and software components. The electronic device 12 also includes a display device 20 for use in rendering textual and graphical images, a storage device 22 for storing various items such as data, information, and programs. A keyboard 24 and a pointing device 26 are also included with the electronic device 12. The pointing device 26 includes such devices as a mouse, track ball, or light pen. Those skilled in the art will recognize that the pointing device 26 can be incorporated with the display device 22 to provide the electronic device 12 with a touch screen that allows the user to interact with the electronic device 12 with a stylist or with other means such as a user's finger.
The storage device 22 includes an application 28 for use in creating and developing masks having a desired graphical or structural pattern. One suitable application for use in creating or developing a mask in accordance with the illustrative embodiment of the present invention is Adobe® PostScript® available from Adobe Systems Incorporated, of San Jose, Calif. Nevertheless, those skilled in the art will recognize that other suitable applications are available for use in creating or developing a mask in accordance with the illustrative embodiment of the present invention for example, other such applications can include, but are not limited to, CorelDRAW® available from Corel Corporation of Ottawa, Canada; and Adobe® Photoshop® available from Adobe Systems Incorporated, of San Jose, Calif. Those skilled in the art will recognize that the electronic device 12 includes other software such as, various user interfaces and other programs, such as one or more OS programs, compilers, drivers, and various other program applications developed in a variety of programming environments for controlling system software and hardware components.
In step 64, image forming apparatus 14A or 14B forms on the substrate 40 the mask 42. The image forming apparatus 14A or 14B receives the image of the mask 42 from the application 28. The formation of the mask 42 in step 64 can occur on a clean substrate 40 free of a dielectric layer or on the substrate 40 with a dielectric layer.
In step 66, the substrate 40 and the mask 42 are heated to an elevated temperature, for example in an oven. The elevated temperature is between about 100° C. and about 150° C. The period of heating the substrate 40 and the mask 42 can range between about 1 second and about 2000 seconds.
In step 68, the adhesion layer 48 is formed. Formation of the adhesion layer 48 takes place in the vacuum chamber 30 using the material source 34. Material source 34 deposits on a surface of the substrate 40 and the mask 42 a selected material or compound to form the adhesion layer 48. Such suitable material sources include, but are not limited to sputterers, spraying apparatuses, electron beam evaporators, thermal evaporators, electrode platters, and electrodeless platters. The material or compound selected to form the adhesion layer 48 can be a conductive or semiconductive material. Suitable materials for use as the adhesion layer 48 include, but are not limited chromium (Cr), nickel (Ni), titanium (Ti), aluminum (Al), copper (Cu), silicon dioxide (SiO2), and silicon nitride (SiNx). Suitable thicknesses of the adhesion layer 48 can range between about 50 Angstroms to about 100 Angstroms or about 5 nanometers to about 10 nanometers. Those skilled in the art will appreciate that the material composition of the adhesion layer 48 can have the same chemical composition as a dielectric layer used to precoat a surface of substrate 40.
In step 70, the conductive element 50 is formed in the vacuum chamber 30 using the material source 34 as the workpiece holder 32 holds the substrate 40. Material source 34 deposits on a surface of the adhesion layer 48 a selected material or compound to form the conductive element 50. Such suitable material sources include, but are not limited to sputterers, spraying apparatuses, electron beam evaporators, thermal evaporators, chemical vapor deposition tools, enhanced chemical vapor deposition tools, electrode platters, and electrodeless platters. The material or compound selected to form the conductive element 50 can be a conductive or semiconductive material. Suitable materials for use as the conductive element 50 include, but are not limited chromium (Cr), nickel (Ni), copper (Cu), aluminum (Al), titanium (Ti), gold (Au), copper (Cu), silicon dioxide (SiO2), or other material or compound. Suitable thicknesses of the conductive element 50 can range between about 50 Angstroms to about 1000 Angstroms or about 5 nanometers to about 100 nanometers.
In step 72, the substrate 40 is cleaned using a suitable cleaning technique to remove mask 42 from the substrate 40. Those skilled in the art will recognize there exist a number of suitable cleaning techniques to remove the mask 42 at any time after the formation of the conductive element 50. Moreover, those skilled in the art will recognize that the suitable cleaning techniques may be combined in a number of manners to facilitate the cleaning process. Examples of cleaning techniques include, but are not limited to, ultrasonic cleaning, rubbing with a swab, pulse jet sprays. Any or all of these techniques can be used alone or in combination with solvents such as 1,1,1-trichloroethane (TCE), solvents from the ketone group, such as acetone, methylisobutyl ketone; the aromatic solvent group such as toluene, xylene; the ester group, such as ethyl acetate, methoxypropyl acetate; ether group such as diethyl ether, and other commonly used solvents such as dimethyl formamide, N-methylpyrolidone, or gamma-butyrolactone.
In step 78, the computer system 10 images the mask 42 on the first surface 44 of substrate 40 using the image forming apparatus 14A or 14B. In step 80, the computer system 10 forms mask 42 on the second surface 46 of substrate 40 using the image forming apparatus 14A or 14B. Those skilled in the art will appreciate that the mask formed on the first surface 44 of the substrate 40 can define one or more structural features distinct from the mask formed on the second surface 46 of the substrate 40 and vice versa.
In step 82, the substrate 40 and the mask 42 are heated to an elevated temperature for a selected period of time. In step 84, the adhesion layer 48 is formed on the first surface 44 of the substrate 40. In step 86, the conductive element 50 is formed on the adhesion layer 48 of the first surface 44 of the substrate 40. In step 88, the adhesion layer 48 is formed on the second surface 46 of the substrate 40. In step 90, the conductive element 50 is formed on the adhesion layer 48 of the second surface of the substrate 40. In step 92, the processed substrate 40 is cleaned to remove the mask from the first surface 44, the second surface 46, or both.
The adhesion layer 48 enables the fabrication of structures that are otherwise unfeasible to fabricate due to delamination of a conductive layer from a substrate. For example, gold and aluminum have poor adhesion properties and delaminate readily from polymeric surfaces. In accordance with the teachings of the present invention, gold can be deposited on polyester without delamination using an adhesion layer of titanium. The present invention provides an adhesion layer that offers a connective structure between the substrate and the conductive layer. This adhesion layer can also be beneficial in improving electrical properties. For example, chromium deposited directly on a polyimide such as “Kapton® E” using Electron-beam deposition has poor electrical conductivity, whereas Electron-beam deposition of chromium over an adhesive layer of titanium results in improved conductivity. The adhesion layer can also prevent the propagation of cracks in the substrate, an insulating layer in contact with the substrate, and a conductive layer in contact with the insulating layer, or the substrate, or both, during bending, to result in an improvement in the length of a life cycle for flexible circuits.
To illustrate the flexibility and the processing of a substrate according to the teachings of the present invention, seven examples are discussed below in detail.
A conductive pattern is fabricated on substrate 40 according the teachings of the present invention. Substrate 40 is polyimide (Kapton® E) film having thickness of about 51 μm. The polyimide film is removably attached to an 8½×11 sheet of paper (stiffener) by means of mounting tape. A negative electrophotographic imaging compound pattern is imaged on the polyimide film attached to the sheet of paper as stiffener using a laser printer, for example a Hewlett Packard LaserJet 5P, available from Hewlett Packard of Palo Alto, Calif. The sheet of paper is removed and the electrophotographic imaging compound and the polyimide film are baked in air for about one minute at a temperature of about 120° C. About a 10 nm thick layer of chromium (Cr) is deposited by Electron-beam evaporation on the polyimide film and the electrophotographic imaging compound under vacuum to form an adhesion layer. A layer of titanium (Ti) follows the layer of Cr. The Ti has a thickness of about 100 nm is deposited by Electron-beam evaporation. The polyimide film with the layers of Cr and Ti is placed in an ultrasonic toluene bath and agitated for 1 minute. The ultrasonic bath is repeated once and the polyimide film is washed with 1,1,1 trichloroethane to quantitatively remove electrophotographic imaging compound and overlying metal layers.
Using a substrate 40 of polyimide (Kapton® E) film having a thickness of about 51 μm a conductive pattern is fabricated thereon. The polyimide film is temporarily attached to a sheet of 8½×11 paper (stiffener) by means of mounting tape. A negative electrophotographic imaging compound pattern is imaged on the polyimide film using a laser printer for example a Hewlett Packard LaserJet 5P, available from Hewlett Packard of Palo Alto, Calif. The sheet of paper is removed from the polyimide film and the electrophotographic imaging compound and the polyimide film are baked in air for about 1 minute at about 120° C. About a 10 nm thick layer of Ti is deposited by Electron-beam evaporation on the polyimide film and the electrophotographic imaging compound under vacuum to form an adhesion layer. Next, about a 100 nm thick layer of gold (Au) is deposited by Electron-beam evaporation on the layer of Ti under vacuum. The polyimide film with the layers of Ti and Au is rubbed with a foam swab in a 1,1,1 trichloroethane/acetone bath to remove the electrophotographic imaging compound and overlying metal layers. The cleaning process is repeated once and the polyimide film is washed with acetone and dried to yield a photographic quality image on polyimide film.
Using an overhead transparency or a piece of polyester film having a thickness of about 5 mil for substrate 40, a conductive pattern is fabricated as shown in
Using a substrate 40 of polyimide (Kapton® E) film having a thickness of about 51 μm a conductive pattern is fabricated thereon. The polyimide film is temporarily attached to a sheet of 8½×11 paper (stiffener) by means of mounting tape. A negative electrophotographic imaging compound pattern is imaged on the polyimide film using a laser printer, for example a Lexmark Optra S 1255, available from Lexmark International, Inc. of Lexington, Ky. Next, a first layer silicon dioxide (SiO2) is deposited on the polyimide film and the electrophotographic imaging compound under vacuum using a sputterer to form an adhesion layer. A second layer of SiO2 is deposited over the first layer of SiO2 under vacuum using a sputterer. Each layer of SiO2 has a thickness of about 50 nm. One suitable sputterer for use with the teachings of the present invention is available from AJA International, Inc. of Scituate, Mass. To clean the workpiece, the polyimide film with the two layers of SiO2 is placed in an ultrasonic toluene bath and agitated for about one minute. The workpiece is then lightly rubbed with swabs in a 1,1,1-trichloroethane bath. This light rubbing process is repeated once with new solvent and the workpiece is washed with 1,1,1-trichloroethane in order to quantitatively remove electrophotographic imaging compound and overlying SiO2 layers.
Using a substrate 40 of polyimide (Kapton® E) film having a thickness of about 51 μm a metallized pattern is fabricated thereon. Before imaging the polyimide film with electrophotographic imaging compound, the polyimide film is coated with SiNx on a top surface and a bottom surface, as illustrated in
Using a substrate 40 of polyimide (Kapton® E) film having a thickness of about 51 μm a conductive pattern is fabricated thereon. The polyimide film is temporarily attached to a sheet of 8½×11 paper (stiffener) by means of mounting tape. A negative electrophotographic imaging compound pattern is imaged on the polyimide film using a laser printer for example a Hewlett Packard LaserJet 5P, available from Hewlett Packard of Palo Alto, Calif. The sheet of paper is removed from the polyimide film and the electrophotographic imaging compound and the polyimide film are baked in air for about 1 minute at about 120° C. Next, a layer of Cr is deposited by thermal evaporation on a portion of the polyimide film and the electrophotographic imaging compound pattern under vacuum to form an adhesion layer. The layer of Cr has a thickness of about 110 nm. The polyimide film is then rubbed with a foam swab in a 1,1,1 trichloroethane/acetone bath to remove the electrophotographic imaging compound and overlying metal layers. This process is repeated once and the polyimide film is washed with acetone and dried to yield a photographic quality image on polyimide.
Using a substrate 40 formed from a 3″×3″ piece polyimide (Kapton® E) film having a thickness of about 51 μm thick a conductive pattern is fabricated thereon. In a center portion of the polyimide film a hole was punched with a punching means, such as a needle, awl, drill or other like punching means to create a via. See
Next, a layer of Cr is deposited by Electron-beam evaporation under vacuum on the electrophotographic imaging compound pattern and the front side of the polyimide film to form an adhesion layer. The layer of Cr has a thickness of about 10 nm thick. The layer of Cr is followed by a layer of Ti deposited by Electron-beam evaporation under vacuum. The layer of Ti has a thickness of about 100 nm. The polyimide film with the deposited layers is placed in an ultrasonic toluene bath and agitated for about one minute to remove the electrophotographic imaging compound. The polyimide film is then lightly rubbed with swabs in a 1,1,1 trichloroethane bath. This light rubbing process is repeated once with new solvent and the polyimide film is washed with 1,1,1 trichloroethane to quantitatively remove electrophotographic imaging compound and overlying metal layers from the front surface of the polyimide film.
The polyimide film is turned over and again temporarily attached again to a sheet of paper (stiffener). An electrophotographic imaging compound pattern is imaged on the bottom side of the polyimide using the laser printer. Next, a layer of Cr is deposited by Electron-beam evaporation under vacuum on the electrophotographic imaging compound pattern and the bottom side of the polyimide film to form an adhesion layer on the bottom side. The layer of Cr has a thickness of about 10 nm thick. The layer of Cr is followed by a layer of Ti deposited by Electron-beam evaporation under vacuum. The layer of Ti has a thickness of about 100 nm. The polyimide film is placed in an ultrasonic toluene bath and agitated for about one minute. The polyimide film is lightly rubbed with swabs in 1,1,1 trichloroethane bath. This light rubbing process is repeated once with new solvent and the polyimide film is washed with 1,1,1 trichloroethane to quantitatively remove the electrophotographic imaging compound on the overlying metal layers. Less than 100 Ω resistance was measured between the upper metallization pattern and the lower metallization pattern.
According to one practice, a microcup® is filled with electrically charged white particles in a black or colored dye. Electrodes can be disposed on, cover, or both opposite sides of the media for use in applying a voltage potential difference across the electronic ink to cause particles within the microcapsules to migrate toward one of the electrodes. This migration can change the color of the microcup, and hence the pixel location, as viewed by an individual. One example of an electronic display 140 and other examples of display media 130 are discussed in detail in U.S. Pat. No. 6,753,830, entitled “Smart Electronic Label Employing Electronic Ink”, the contents of which are incorporated hereby incorporated by reference. Another example of an electronic display 140 and other examples of display media 130 are discussed in detail in U.S. Provisional Application Ser. No. 60/550,091, filed Mar. 1, 2004, the contents of which are hereby incorporated by reference.
Those skilled in the art will recognize the term microcup® refers to one or more electrophoretic display cells having a structure as disclosed in U.S. Pat. No. 6,753,067, entitled “Microcup Compositions Having Improved Flexure Resistance And Release Properties”, the contents of which are hereby incorporated by reference.
The electrophotographic imaging techniques disclosed herein are well suited for use in forming a thin film transistor array on a flexible polymeric substrate, such as a flexible polyimide substrate. Those skilled in the art will appreciate that the formation of the thin film transistor array can be performed with or without the use of the adhesion layer discussed above in relation to
A second surface of the gate insulator layer 218 contacts a first layer of the channel layer 220. A first portion of a second surface of the channel 220 contacts a first surface of the source 222. A second portion of the second surface of the channel 222 contacts a first surface of the drain 226. A second surface of the source 222 contacts a first surface of the metallized source contact 224. A second surface of the drain 226 contacts a first surface of the metallized drain contact 228.
Formation of the transistor 200 is discussed in more detail with relation to
One suitable material for the flexible polymeric substrate 210 is Kapton® E having a thickness of about 51 μm. Other suitable materials include high performance polymers such as polybenzimidazole, polyethylene naphthalate, polyethylene terephthalate, or lignocelluloses. The first insulator layer 212 and second insulator layer 214 form barrier layers or subbing layers to isolate the flexible polymeric substrate 210 from the remainder of the transistor 200. The first insulator layer 212 and the second insulator layer 214 provide a moisture barrier for the flexible polymeric substrate 210 and assist in providing dimensional stability and a base with good adhesion properties during manufacture of the transistor 200 or an array of transistors 200 on the flexible polymeric substrate 210. The first insulator layer 212 and the second insulator layer 214 are each formable using silicon nitride (SiNx). A suitable thickness for the first insulator layer 212 formed of SiNx is about 500 nm. In similar fashion, a suitable thickness for the second insulator layer 214 formed of SiNx is about 500 nm. The of each insulator layer 212, 214 can have a thickness that ranges from about 50 nm to 2000 nm.
The gate insulator layer 218 is formable from SiNx having a thickness of between about 20 nm and about 1000 nm. In one embodiment of the present invention the gate insulator layer 218 is formed from SiNx with a thickness of about 360 nm.
The channel layer 220 is formable using amorphous silicon (a-Si) with a thickness of between about 100 nm and about 400 nm. One type of amorphous silicon suitable for forming the channel layer 220 is undoped hydrogenated amorphous silicon (a-Si:H) having a thickness of about 200 nm.
The source layer 222 and the drain layer 226 are formable using an n-type amorphous silicon (n+) a-Si with a thickness of between about 2.5 nm and about 100 nm. In one embodiment of the present invention the source layer 222 and the drain layer 226 are formed from an n-type phosphorous doped hydrogenated amorphous silicon (n+) a-Si:H having a thickness of about 50 nm.
The metallized gate contact layer 216, the metallized source contact layer 224 and the metallized drain contact layer 228 are formable using metals such as chromium (Cr), titanium (Ti), gold (Au), nickel (Ni), aluminum (Al), copper (Cu), silver (Ag), or other suitable material or compound having properties or a structure well suited for a contact layer. Suitable thicknesses of the metallized layers 216, 224, and 228 range between about 10 nm and about 120 nm. The metallized layer 216 can consist of several layers as illustrated in
The gate insulator layer 218 is formable from SiNx having a thickness of between about 20 nm and about 1000 nm. In one embodiment of the present invention the gate insulator layer 218 is formed from SiNx with a thickness of about 360 nm.
The channel layer 220 is formable using amorphous silicon (a-Si) with a thickness of between about 100 nm and about 400 nm. One type of amorphous silicon suitable for forming the channel layer 220 is undoped hydrogenated amorphous silicon (a-Si:H) having a thickness of about 200 nm.
The source layer 222 and the drain layer 226 are formable using an n-type amorphous silicon (n+) a-Si with a thickness of between about 2.5 nm and about 100 nm. In one embodiment of the present invention the source layer 222 and the drain layer 226 are formed from an n-type phosphorous doped hydrogenated amorphous silicon (n+) a-Si:H having a thickness of about 50 nm.
The metallized gate contact layer 216, the metallized source contact layer 224 and the metallized drain contact layer 228 are formable using metals such as chromium (Cr), titanium (Ti), gold (Au), nickel (Ni), aluminum (Al), copper (Cu), silver (Ag), or other suitable material or compound having properties or a structure well suited for a contact layer. Suitable thicknesses of the metallized layers 216, 224, and 228 range between about 10 nm and about 120 nm. The metallized layer 216 can consist of several layers. In a preferred embodiment, the metallized layer 216 consists of three layers: a 10 nm Cr layer followed by 100 nm Ti, and finally 10 nm of Cr. In this example the bottom layer of Cr is serving as an adhesion layer to the insulator layer 214. Such an adhesion layer is discussed above in relation to
In step 300, the flexible polymeric substrate 210 is prepared by completing of one or more cleaning operations, completing a PECVD operation to form the first and second insulator layers 212 and 214, respectively, and if necessary completing an operation to dimension the flexible polymeric substrate 210 to a desired dimensionality. Those skilled in the art will appreciate that the one or more cleaning operations can include cleaning with acetone or other suitable cleaning compound followed by a drying operation. Furthermore, those skilled in the art will appreciate that the cleaning operation can include a step or steps to etch one or more surfaces of the flexible polymeric substrate 210 to attain a desired surface texture or surface topology.
If necessary, in step 300, the flexible polymeric substrate 210 is aligned and temporarily affixed to a stiffener element to support the flexible polymeric substrate 210 during formation of a mask on a surface of the substrate by the image forming apparatus 14A or 14B. One suitable stiffener includes a paper medium having a suitable stiffness and predefined alignment marks for aligning the flexible polymeric substrate 210 with the stiffener. Other mediums having a suitable stiffness for feeding into an image forming apparatus are well suited for us as a stiffener.
In step 302, the flexible polymeric substrate 210, with or without the stiffener element is fed into the image forming apparatus 14A or 14D, such as a Lexmark Optra S 1255 Laser Printer available from Lexmark International, Inc., of Lexington, Ky. The flexible polymeric substrate 210, with or without the first insulator layer 212 or the second insulator layer 214, is imaged with electrophotographic imaging compound by the image forming system 14A or 14B to form a negative first mask. The first mask defines the metallized gate contact layer 216.
In step 304, a 10 nm layer of Cr, a 100 nm layer of Ti, and 10 nm layer of Cr are deposited by electron beam evaporation under vacuum on the electrophotographic imaging compound pattern provided by the first mask 350 to form a first metallized layer. Those skilled in the art will appreciate that the first metallized layer is formable from a single metal. The total thickness of the first metallized layer can be between about 10 nm and about 2000 nm. In step 306, the flexible polymeric substrate 210, which includes the layers of metal and the first mask 350 formed of the electrophotographic imaging compound is placed in an ultrasonic toluene bath and agitated for about one minute. The ultrasonic bath is repeated as needed and the flexible polymeric substrate 210 is washed with 1,1,1-trichloroethane to quantitatively remove selected portions of the electrophotographic imaging compound and overlying metal layers. Removal of the electrophotographic imaging compound and overlying metal layers reveals the metallized gate contact 216.
Those skilled in the art will recognize there exist a number of suitable cleaning techniques to remove the mask of electrophotographic imaging compound and the selected overlying layer or layers of metal after the formation of the first metallized layer. Examples of cleaning techniques include, but are not limited to, ultrasonic cleaning, rubbing with a swab, and pulse jet sprays. Furthermore, any or all of these techniques can be used alone or in combination with solvents such as 1,1,1-trichloroethane (TCE), solvents from the ketone group, such as acetone, and the like.
In step 308, the flexible polymeric substrate 210 undergoes a deposition process to form the gate insulator layer 218, the channel layer 216, the source 222, and the drain 226. For example, the flexible polymeric substrate 210 is placed in a suitable work piece holder associated with a PECVD system and coated with a layer of SiNx having a thickness of about 360 nm to form the gate insulator layer 218; coated with a layer of undoped a-Si:H having a thickness of about 200 nm to form the channel layer 220; and coated with a layer of phosphorous doped n-type hydrogenated amorphous silicon ((n+)a-Si:H) having a thickness of about 50 nm to form a conductive layer for the source 222 and the drain 226. Those skilled in the art will appreciate that the layer thicknesses are not meant to be limiting of the present invention and other suitable thicknesses are well within the scope of the present invention. For example, the SiNx layer can range in thickness from between about 20 nm and about 1000 nm, the a-Si:H layer can range in thickness from between about 100 nm and about 400 nm, and the (n+) Si:H layer can range in thickness from between about 2.5 nm and about 100 nm.
In step 310, a second mask of electrophotographic imaging compound is formed on the flexible polymeric substrate 210 and the various layers already formed thereon. That is, if necessary, the flexible polymeric substrate 210 is temporarily attached and aligned to a stiffener element, for example, a paper medium with predefined alignment marks for aligning the flexible polymeric substrate thereto or temporarily affixed to another suitable medium with predefined alignment markings. The flexible polymeric substrate 210 and the various layers already formed thereon is imaged by the imaged forming apparatus 14A or 14B with electrophotographic imaging compound to form the second mask defining the metallized source contact 224 and the metallized drain contact 228.
In step 312, a second metallized layer is formed. That is, the flexible polymeric substrate 210 and the various layers formed thereon is placed in an electron beam metal evaporator, such as the system discussed in relation to
In step 314, the flexible polymeric substrate 210 with the second metallized layer formed thereon is processed to remove selected portions of the second mask and overlying metal layer or layers. To remove selected portions of the second mask and overlying metallized layer or layers the flexible polymeric substrate 210 is placed in an ultrasonic toluene bath and agitated for about 1 minute. The ultrasonic bath is repeated at least once and the flexible polymeric substrate 210 is washed with TCE to quantitatively remove selected portions of the electrophotographic imaging compound forming the second mask and overlying metal layers to reveal the metallized source contact 224 and the metallized drain contact 228.
After drying, the flexible polymeric substrate 210 and the various layers formed thereon are etched in step 316. In step 316, the flexible polymeric substrate 210 with the various layers formed thereon is placed in a plasma etcher, such as the Plasma-Therm 790 System VII to remove a portion of the (n+) a-Si:H layer formed on the channel layer 220 to expose a portion of the channel layer 220 and form the source 222 and the drain 226. Those skilled in the art will appreciate that the metallized source contact 224 and the metallized drain contact 228 act like a mask in step 316 defining the source 222 and the drain 226 by the protecting the underlying (n+) a-Si:H from being etched. Suitable etching conditions are 150 mbar, 16 standard cubic centimeters/minute CF4, and 0.12 watts per centimeter squared for a total of about 7 minutes.
In step 318, a third mask of electrophotographic imaging compound is formed on the flexible polymeric substrate 210 and the various layers formed thereon to define a transistor island or an array of transistor islands on the polymeric substrate 210.
In step 320, the flexible polymeric substrate 210 and the various layers formed thereon is etched to remove portions of the channel layer 220. A suitable methodology for etching the channel layer 220 includes a plasma etcher, such as the Plasma-Therm 790 System VII. Suitable etching conditions include, but are not limited to 150 mbar 16 standard cubic centimeters/minute CF4 and 0.12 watts per centimeter squared until a sufficient amount of the channel layer 220 is removed to a plurality of transistors electrically isolated from one another.
In step 322, the flexible polymeric substrate 210 is cleaned to remove the remaining electrophotographic imaging compound layer formed with the third mask 370. Suitable cleaning methodologies include toluene in an ultrasonic cleaning bath.
At this point in the process an array of transistors are defined on the flexible polymeric substrate 210 by the above defined steps.
In step 324, the flexible polymeric substrate 210 and the various layers formed thereon is coated with photoresist. The photoresist coated flexible polymeric substrate 210 is exposed to ultraviolet light using conventional photolithography using an exemplary mask 380 shown in
In accordance with steps 60 and 64 a negative electrophotographic imaging compound pattern consisting of a seven segment display is imaged on the lignocellulosic substrate 400 using the image forming system 14A or 14B, such as a laser printer. One suitable laser-printer is available from Lexmark International, of Lexington, Kentucky under the model Lexmark Optra S1255.
In accordance with step 68, a 10 nm layer of Ti is deposited by electron beam evaporation under vacuum on the electrophotographic imaging compound pattern to form an adhesion layer 420. In accordance with step 70, a conductive layer 430 of Au having a thickness of about 60 nm is deposited on the adhesion layer 420 using electron beam evaporation technology under vacuum.
The lignocellulosic substrate 400 is removed from the electron beam system and is cleaned in accordance with step 72 to remove mask 410 and the overlying adhesion layer 420 and conductive layer 430. One suitable cleaning technique is to place the lignocellulosic substrate 400 with the metal layers formed thereon in a bath of TCE and rubbed with a foam brush to remove the electrophotographic imaging compound and overlying unwanted metal layers. If necessary, the rubbing process is repeated with the same or additional solvent to insure removal of the electrophotographic imaging compound and unwanted metal layers. After cleaning, the lignocellulosic substrate 400 is allowed to dry.
Application of a voltage potential difference of about 50 volts DC across the electrophoretic display medium 460 causes selected particles within the microcups® to migrate toward the common electrode 470. The migration can change the color of a segment formed on the lignocellulosic substrate 400 as viewed by an individual through the common electrode 470.
It will thus be seen that the invention efficiently attains the objects set forth above, amongst those made apparent from the preceding discussion. Since certain changes may be made in the above constructions, for example, additional layers of compounds and materials can be formed in addition to the layers discussed herein, that is, backplanes or electronic devices having a three layer, four layer, a five layer, a six layer, a seven layer, an eight layer, a nine layer, ten layer, eleven layer, construction are well within the scope of the present invention. It is intended that all matter contained in the above description are shown in the accompanying drawings be interpreted as illustrative and not in a limiting sense.
It is also to be understood that the following claims are to cover all generic and specific features of the invention described herein, and all statements are of the scope of the invention which, as a matter of language, might be said to fall therebetween.
This application is a continuation in part U.S. Non-Provisional Application Ser. No. 10/931,154 filed Aug. 30, 2004, which claims priority to Provisional Application Ser. No. 60/498,983, filed Aug. 30, 2003, the contents of which are hereby incorporated by reference, and claims priority to Provisional Application Ser. No. 60/550,091, filed Mar. 1, 2004, the contents of which are hereby incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| 60498983 | Aug 2003 | US | |
| 60550091 | Mar 2004 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 10931154 | Aug 2004 | US |
| Child | 11070139 | Mar 2005 | US |
