FIELD OF THE INVENTION
The present invention is directed to a method for producing a micromechanical device including a substrate and a membrane.
BACKGROUND INFORMATION
A micromechanical device in which the components and the substrate material are thermally insulated from one another, the device being manufactured by a bulk micromechanical process, is described in an article by D. Moser and H. Baltes, “A high sensitivity CMOS gas flow sensor on a thin dielectric membrane,” and in the journal Sensors and Actuators A 37-38 (1993), pp. 33-37. A complex front- and back-side process is required for this method. The membrane needed for thermal insulation, on which temperature sensors and heaters are situated, for example, is produced via a bulk micromechanical process from the back side. The membrane is structured using a wet chemical etching process, for example, with the aid of KOH. In doing so, the entire substrate must be etched in the area of the membrane starting from the back side, which results in long process times. Since wet chemical etching solutions attack the functional layers on the front side, the wafer must be embedded in an etching box to protect the front during the etching process. This conventional method involving the back-side process is therefore very complex and costly.
SUMMARY
The method and device according to the present invention have the advantage over the related art that a method in which only front-side processes are needed is provided for manufacturing the membranes. A surface micromechanical process (SMM) may therefore be used for the method and device according to the present invention. Furthermore, the method and device according to the present invention make it possible to provide thermal insulation between components on or in the membrane and the substrate material. Such components in or on the membrane may include temperature sensors and/or heating elements; however, any component whose manufacture is integratable in the manufacturing process of the device is possible and conceivable according to the present invention. Thermal insulation is needed in thermal sensors such as thermocouples, chemical sensors, and air mass sensors, for example. The method and device according to the present invention have the advantage over the related art that only surface micromechanical processes, i.e., only front-side processes, are needed for manufacturing the device. This makes complex back-side processes such as KOH etching using an etching box for structuring the membrane unnecessary. Particles and scratches on the front of the wafer are minimized or avoided due to the omission of the back-side processes in which the wafer must be turned over and deposited on the front side. A surface micromechanical sacrificial layer method is used for producing the thermal insulation according to the present invention, and the method has high selectivity both with respect to thermally insulating materials such as oxides and nitrides and with respect to metals. Silicon may be used as the sacrificial layer in the method according to the present invention. The area of the sacrificial layer is initially deep structured according to the present invention via a first (anisotropic) etching step, e.g., a DRIE (deep reactive ion etching) process, and it is subsequently fully etched laterally in a second (isotropic) etching step using, e.g., a XeF2, ClF3, BrF3 process in such a way that a cavity is formed underneath the membrane. A membrane cavity area, i.e., the substrate area in which the membrane layer is unsupported and thus spans the cavity, is thus formed. According to the present invention, the membrane layer includes a thermally poorly conductive material, for example, silicon oxide or silicon nitride. The combined sacrificial etching layer process of the present invention makes it possible to produce thick sacrificial layers. The compatibility of the etching media used in the sacrificial layer etching with the customary materials used in the standard CMOS processes makes it possible, according to the present invention, for the manufacture of the device according to the present invention and the manufacture of an integrated circuit (IC) using CMOS technology to be performed in an integrated manner, i.e., single manufacturing process (including a plurality of steps).
It is advantageous that the holes in the membrane are sealed after the second etching step, e.g., using a cover layer or a cap. This makes it possible to protect the structures, for example, during a subsequent sawing process. According to the present invention, a PECVD oxide layer or a spin-on glass layer or a combination of different layers is conceivable here as a sealing layer. A cap as a cover is also conceivable as a seal for the holes. It is furthermore advantageous that a component to be thermally insulated from the substrate material is produced on or in the membrane before the first etching step. As a result, no further steps for producing a component are needed after the second etching step, and thus no problems occur due to the fact that, for example, after the two etching steps there are holes in the membrane into which the material to be applied to the membrane may penetrate and the material may attack or damage the membrane from its back side. It is furthermore advantageous that the membrane is well insulated from the substrate material. This is achieved according to the present invention by a relatively great depth of the cavity which is provided in the membrane area over the substrate material. This results, via different heat transport mechanisms, in reduced heat transport from the membrane to the substrate material and thus good thermal insulation. It is furthermore advantageous that a silicon substrate or a SOI/EOI substrate (silicon-on-insulator/epipoly-on-insulator substrate), which may be monocrystalline, is provided as the substrate material. An SOI/EOI substrate according to the present invention is usable in an advantageous manner due to the fact that the oxide layer of the SOI/EOI substrate is used as a vertical etch stop during sacrificial layer etching, which makes it possible to set a defined sacrificial layer thickness. A SOI/EOI substrate is based on a layer structure in which an oxide layer and subsequently a silicon layer are applied to a monocrystalline silicon substrate.
All in all, the method according to the present invention allows simple manufacture of a device according to the present invention, e.g., sensor elements, in which thermal insulation between temperature sensors and/or heating elements and the substrate material is needed. According to the present invention, only a few layers and photolitographic steps are needed for carrying out the method according to the present invention, so that the method is implementable in a simple and cost-effective manner.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a sectional view of a first example embodiment of the substrate material having a first part of a membrane layer.
FIG. 2 shows a sectional view of the first embodiment of the substrate material having a first part of the membrane layer and a component integrated in the membrane layer.
FIG. 3 shows a sectional view of the first embodiment of the substrate material having a membrane layer after a partially completed first etching step.
FIG. 4 shows a sectional view of the first embodiment of the substrate material having a membrane layer after a completed first etching step.
FIG. 5 shows a sectional view of the first embodiment of the substrate material having a membrane layer after completed first and second etching steps.
FIGS. 6 and 7 show sectional views of the first embodiment of the substrate material having a membrane layer after completed first and second etching steps, including first and second example embodiments of a seal for the holes in the membrane, respectively.
FIG. 8 shows a sectional view of a second example embodiment of the substrate material having a membrane layer after a completed first etching step.
FIG. 9 shows a sectional view of the second embodiment of the substrate material having a membrane layer after completed first and second etching steps.
DETAILED DESCRIPTION
FIG. 1 shows a sectional view of a first example embodiment of substrate material 10 having a first part 21 of a membrane layer. First part 21 of the membrane layer should be under tensile stress and have a certain thermal conductivity. According to the present invention, first part 21 of the membrane layer includes a first partial membrane layer 22, which is provided as an oxide layer, for example. According to the present invention, first partial membrane layer 22 is produced, for example, as a thermal oxide layer or as a PECVD oxide layer. According to the present invention, first part 21 of the membrane layer also includes a second partial membrane layer 24, which is provided as a nitride layer, for example. Second partial membrane layer 24 is produced according to the present invention as a PECVD nitride layer or as an LPCVD nitride layer, for example. However, in other example embodiments (not shown) of the present invention, first part 21 of the membrane layer may be provided in the form of a layer system composed of oxide layers/nitride layers. The thicknesses of first and second partial membrane layers 22, 24 are in the range of approximately 0.5 to 5 μm according to the present invention. In the first example embodiment, substrate material 10 includes a semiconductor material 12,e.g., a monocrystalline silicon material.
FIG. 2 shows a sectional view of the first embodiment of substrate material 10 having a first part 21 of membrane layer 20 and a component, not identified with a particular reference symbol, integrated in membrane layer 20. According to the present invention, the component is provided as a thermocouple or temperature sensor, for example, but it may be any component integratable into or onto a membrane. The thermocouple has, for example, a platinum resistor or a Si/Al or Si/Ge thermopile. To manufacture a thermopile as a thermocouple, a structured layer, provided as a polysilicon layer, for example, is applied to membrane 20, which includes a first domain 201 and optionally a second domain 202. First domain 201 forms a first resistor, which is also identified below with reference symbol 201. First and second domains 201, 202 may also be provided electrically fully insulated from one another, but structured from the same layer. Subsequent to the application of first resistor 201, an intermediate oxide layer 203 and a second resistor 204 made of aluminum or germanium according to the present invention are deposited and structured. A thermocouple composed of first and second resistors 201, 204 results from the contact (not identified with a reference symbol) between first and second resistors 201, 204. A cover oxide layer 205 is deposited on the thermocouple and structured. Bond pads 206 or, in general, contact surfaces 206, made, for example, of aluminum, are produced to contact the terminals of the thermocouple. This results in membrane layer 20 including first part 21 of the membrane layer and the “structure” of the component—the thermocouple in the present embodiment—on first part 21 of the membrane layer. In another embodiment of the present invention (not illustrated), however, membrane layer 20 could also be designed in such a way that the component is provided underneath first and second partial membrane layers 22, 24, for example. In any case, substrate material 10 is situated “underneath” membrane layer 20 according to the present invention. This is provided in all the following figures in the same basic way and will therefore not be described repeatedly. The basic design of the component as a thermocouple, for example, is also maintained in the following figures; therefore it is not described repeatedly.
FIG. 3 shows a sectional view of the first embodiment of substrate material 10 having a membrane layer 20 after a partially completed first etching step. To produce the cavity according to the present invention, vertical cutouts, i.e., holes, are made in membrane layer 20 at certain perforation points, identified in FIG. 3 with arrows and reference numbers 28, 29. For this purpose, perforation points 28 and 29 are defined by photoresist mask 26 illustrated with the aid of dashed lines only in FIG. 3 in such a way that photoresist mask 26 covers the entire membrane layer 20 except perforation points 28, 29. Subsequently, it is possible to produce holes 40 in membrane layer 20 using a wet chemical or dry chemical first etching step, i.e., to drive holes 40 through cover oxide layer 205, intermediate oxide layer 203, as well as first and second partial membrane layers 22, 24. For this purpose, the etching process for the first etching step is provided as an anisotropic process. Perforation points 28, 29 and thus also holes 40 are located at points of membrane layer 20 at which no parts of the components located on or in membrane layer 20 may be damaged by the production of holes 40. Therefore only one area of substrate 10 is provided as a sacrificial layer “underneath” a perforation point 28, 29, in the vertical direction, i.e., the direction in which holes 40 are produced in two-dimensional membrane layer 29. This is clearly visible for perforation points 28, because the corresponding holes 40 do not intersect the first or second resistor of the thermocouples identified with reference numbers 201 and 204 in FIG. 2. For perforation points denoted by reference numeral 29 this is illustrated by the side walls of the corresponding holes 40 illustrated using dotted lines. This should clarify the fact that holes 40 for perforation points 29 are not in the section plane illustrated (in which first and second resistors of the thermocouple are located), but in another section plane in which the component is not affected by holes 40.
FIG. 4 shows a sectional view of the first embodiment of substrate material 10 having a membrane layer 20 after a completed first etching step. The difference with respect to FIG. 3 is only that the first etching step has been completed, i.e., holes 40 have been made to a certain depth 44 in substrate material 10 starting from holes 40 in membrane layer 20 at perforation points 28, 29 (see the description of FIG. 3). For this purpose, an anisotropic etching process is used for deep patterning, a DRIE etching process, for example, as was used for the first part of the first etching step illustrated in FIG. 3. Depth 44 is illustrated in FIG. 4 by a double arrow underneath first and second partial membrane layers 22, 24 into substrate material 10. Depth 44 of holes 40 is between 2 μm and 200 μm underneath membrane layer 20. The depth of the sacrificial layer etching process is defined by the deep patterning. Holes 40, which are referred to hereinafter as perforation holes 40, may have a diameter between 0.5 μm and 500 μm. For applications in which the membrane should have as few holes 40 as possible (e.g., infrared detectors or mass flow sensors), holes 40 may be smaller than 10 μm. Applications requiring a highly structured membrane (e.g., thermal conductivity sensors for H2 detection, sensors based on free convection flow for inclination measurement), may have holes 40 larger than 100 μm.
FIG. 5 shows a sectional view of the first embodiment of substrate material 10 having a membrane layer 20 after completed first and second etching steps. Starting from the manufacturing stage of the device according to the present invention illustrated in FIG. 4, the trench structure defined by holes 40 and not visible in the area of membrane layer 20 is etched laterally in the area of the sacrificial layer, i.e., underneath membrane 20, using an isotropic semiconductor etching process as a second etching step. This is shown in FIG. 5 by four horizontal double arrows not provided with reference numbers. The access of the etching medium for the second etching step is illustrated in FIG. 5 by arrows 42 through holes 40. The etching process may be carried out using a XeF2, ClF3 or BrF3 process, for example. A cavity 30 is thus formed in membrane cavity area 210 between membrane layer 20 and the unetched part of substrate material 10, and unsupported membrane 20 over cavity 30 carrying or including the components is provided in the membrane area 21. Cavity 30 has a depth 31, which, according to the present invention, basically corresponds to depth 44 of the deep patterning of holes 40 underneath membrane layer 20, illustrated in FIG. 4. The thermocouples or generic components located on or in membrane 20 are thermally insulated from substrate material 10 by cavity 30.
FIGS. 6 and 7 show a sectional views of the first embodiment of substrate material 10 having a membrane layer 20 after a completed first and second etching steps, including first and second embodiments of a seal for the holes 40 in membrane 20, respectively. FIG. 6 shows a first embodiment of a seal for the holes 40 as a sealing layer 50. FIG. 7 shows a second embodiment of a seal for the holes 40 as a cap 52. Components or other structures on or in membrane 20, are thus protected, for example, during a subsequent sawing process for separating a plurality of devices of the present invention manufactured jointly on a substrate wafer. Sealing layer 50 may be designed as a PECVD oxide or as spin-on glass.
FIGS. 8 and 9 show sectional views of a second embodiment of substrate material 10 having a membrane layer 20. The embodiment after the first completed etching step is illustrated in FIG. 8. The embodiment after the first and second completed etching steps are illustrated in FIG. 9. In the second embodiment of substrate material 10, sequence of different layers are included in substrate material 10, for example, a silicon-silicon oxide-silicon sequence. In this case, for example, a (silicon) oxide layer 16 and then a silicon layer 15 are applied to a monocrystalline part 17 of substrate material 10. Silicon layer 15 may be provided either as a monocrystalline silicon layer 15 or as an “epitaxially applied” polycrystalline silicon layer 15 (known as epi-poly silicon layer 15). Accordingly, substrate material 10 is referred to as an SOI material in the first case and as an EOI material in the second case. The steps of the manufacturing process, however, are similar in the second embodiment of substrate material 10 to those described in FIGS. 1 through 7. One difference is that oxide layer 16 of substrate material 10 provides an etching stop when the first etching step is completed. As a result, holes 40 may not extend into substrate material 10 via the deep patterning method of the first etching step any deeper than to oxide layer 16, i.e., going all the way through silicon layer 15 as the sacrificial layer. End point recognition of the first etching step is thus possible. Deep patterning of holes 40 beyond membrane layer 20 extends over depth 44 into substrate 10, which corresponds to the layer thickness of silicon layer 15. Furthermore, depth 31 of cavity 30 corresponds to the thickness of silicon layer 15 of the substrate material.
Patent Application
20060226114
