Patent Grant
9484470
Power electronics are widely used in a variety of applications. Power electronic devices are commonly used in circuits to modify the form of electrical energy, for example, from AC to DC, from one voltage level to another, or in some other way. Such devices can operate over a wide range of power levels, from milliwatts in mobile devices to hundreds of megawatts in a high voltage power transmission system. Despite the progress made in power electronics, there is a need in the art for improved electronics systems and methods of operating the same.
The present invention relates generally to electronic devices. More specifically, the present invention relates to techniques for providing a P-i-N diode using III-nitride semiconductor materials with implanted region(s) to provide edge termination. Merely by way of example, the invention has been applied to methods and systems for manufacturing P-i-N diodes for high-voltage GaN-based devices. The methods and techniques can be applied to a variety of compound semiconductor systems such as vertical junction field-effect transistors (JFETs), thyristors, Schottky barrier diodes, PN diodes, bipolar transistors, and other devices.
According to one embodiment, a method for fabricating a III-nitride semiconductor device is provided. The method includes providing a III-nitride substrate of a first conductivity type and characterized by a first dopant concentration, and forming a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate. The first III-nitride epitaxial layer is characterized by a second dopant concentration less than the first dopant concentration. The method further includes forming a second III-nitride epitaxial layer of a second conductivity type coupled to the first III-nitride epitaxial layer, removing a portion of the second III-nitride epitaxial layer to expose a portion of the first III-nitride epitaxial layer, and implanting ions into an implanted region of the exposed portion of the first III-nitride epitaxial layer. The exposed portion of the first III-nitride epitaxial layer is adjacent to a remaining portion of the second III-nitride epitaxial layer. The method also includes forming a first metal structure coupled to the remaining portion of the second III-nitride epitaxial layer, and forming a second metal structure coupled to the III-nitride substrate. A charge density in the implanted region is substantially lower than a charge density in the first III-nitride epitaxial layer.
According to another embodiment, a method for fabricating a III-nitride semiconductor device is provided. The method includes providing a III-nitride substrate of a first conductivity type and characterized by a first dopant concentration, and forming a first III-nitride epitaxial layer of the first conductivity type coupled to the III-nitride substrate. The first III-nitride epitaxial layer is characterized by a second dopant concentration less than the first dopant concentration. The method also includes forming a second III-nitride epitaxial layer of a second conductivity type coupled to the first III-nitride epitaxial layer, and implanting ions into an implanted region comprising a first portion of the first III-nitride epitaxial layer and a first portion of the second III-nitride epitaxial layer. The method further includes forming a first metal structure coupled to a second portion of the second III-nitride epitaxial layer, and forming a second metal structure coupled to the III-nitride substrate.
According to yet another embodiment, a III-nitride semiconductor device is provided. The III-nitride semiconductor device includes an active region for supporting current flow during forward-biased operation of the III-nitride semiconductor device. The active region includes a first III-nitride epitaxial material having a first conductivity type, and a second III-nitride epitaxial material having a second conductivity type. The III-nitride semiconductor device further includes an edge-termination region physically adjacent to the active region and including an implanted region comprising a portion of the first III-nitride epitaxial material. The implanted region of the first III-nitride epitaxial material has a reduced electrical conductivity in relation to portions of the first III-nitride epitaxial material adjacent to the implanted region.
Numerous benefits are achieved by way of the present invention over conventional techniques. For example, some embodiments of the present invention reduce the electric field crowding at the periphery of vertical power devices, which can result in devices capable of operating at higher voltages than conventional devices. Additionally, some embodiments of the present invention increase the critical electric field at the periphery of vertical power devices, resulting in even higher operating voltages. Moreover, the present invention provides self-aligned edge termination regions that are simpler and cheaper to fabricate compared to prior-art devices.
Another advantage provided by embodiments of the present invention over conventional devices is based on the superior material properties of GaN-based materials. Embodiments of the present invention provide homoepitaxial GaN layers on bulk GaN substrates that are imbued with superior properties to other materials used for power electronic devices. High electron mobility, μ, is associated with a given background doping level, N, which results in low resistivity, ρ, since ρ=1/qμN.
The ability to obtain regions that can support high voltage with low resistance compared to similar device structures in other materials allows embodiments of the present invention to provide resistance properties and voltage capability of conventional devices, while using significantly less area for the GaN device. Capacitance, C, scales with area, approximated as C=∈A/t, so the smaller device will have less terminal-to-terminal capacitance. Lower capacitance leads to faster switching and less switching power loss.
These and other embodiments of the invention along with many of its advantages and features are described in more detail in conjunction with the text below and attached figures.
In the appended figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label.
The present invention relates generally to electronic devices. More specifically, the present invention relates to techniques for providing a P-i-N diode using III-nitride semiconductor materials with implanted region(s) to provide edge termination. Merely by way of example, the invention has been applied to methods and systems for manufacturing P-i-N diodes for high-voltage GaN-based devices. The methods and techniques can be applied to a variety of compound semiconductor systems such as vertical junction field-effect transistors (JFETs), thyristors, Schottky barrier diodes, PN diodes, bipolar transistors, and other devices.
GaN-based electronic and optoelectronic devices are undergoing rapid development, and generally are expected to outperform competitors in silicon (Si) and silicon carbide (SiC). Desirable properties associated with GaN and related alloys and heterostructures include high bandgap energy for visible and ultraviolet light emission, favorable transport properties (e.g., high electron mobility and saturation velocity), a high breakdown field, and high thermal conductivity. In particular, electron mobility, μ, is higher than competing materials for a given background doping level, N. This provides low resistivity, ρ, because resistivity is inversely proportional to electron mobility, as provided by equation (1):
where q is the elementary charge.
Another superior property provided by GaN materials, including homoepitaxial GaN layers on bulk GaN substrates, is high critical electric field for avalanche breakdown. A high critical electric field allows a larger voltage to be supported over smaller length, L, than a material with a lower critical electric field. A smaller length for current to flow together with low resistivity give rise to a lower resistance, R, than other materials, since resistance can be determined by equation (2):
where A is the cross-sectional area of the channel or current path.
In general, there is a tradeoff between the physical dimension needed to support high voltage in a device's off state and the ability to pass current through the same region with low resistance in the device's on state. A P-i-N diode is formed by a P-type semiconductor region in contact with an “intrinsic” semiconductor region in contact with an N-type semiconductor region. The “intrinsic” region may be truly intrinsic, i.e. not intentionally doped with P-type or N-type dopants, or it may simply be much more lightly doped with either P-type or N-type dopants compared to the N-type and P-type regions on either side of the intrinsic region. Such a diode may also be commonly referred to simply as a PN diode. It is well within the scope of this invention to substitute a lightly-doped drift region for the intrinsic region, and substitute a PN diode for the P-i-N diode.
As described herein, P-i-N diodes are capable of exceeding the majority carrier device figures of merit due to minority carrier injection into the intrinsic region in the on state. Therefore, the drift layer doping level can be made lower for a given thickness while still obtaining low resistance in the on state. The resistance becomes dependent on the carrier injection levels rather than the carriers provided by doping. The electric field provide will flatten, or be spread out across the drift region, as the doping is lowered and high breakdown can be maintained with a thinner drift layer. GaN layers grown on bulk GaN substrates have low defect density compared to layers grown on mismatched substrates and consequently can have large minority carrier lifetime in the intrinsic region compared to non-bulk GaN, enhancing the carrier injection effect for wider base region. The low defect density will also give rise to superior thermal conductivity. Despite these advantages, however, P-i-N diodes used in high-voltage applications can still suffer adverse effects due to edge field crowding. When properly employed, edge termination allows a semiconductor device to break down uniformly at its main junction rather than uncontrollably at its edge. According to embodiments of the present invention, edge termination structures are formed to alleviate edge field crowding by creating implanted regions at the edge of an active region of a GaN-based P-i-N diode, and similar devices.
Methods for the formation of isolation implanted regions in structures formed from GaN and related alloys and heterostructures can differ from those used in other semiconductors, such as Si and SiC. Furthermore, structures that would benefit from the incorporation of the implanted regions provided herein have rarely been manufactured using GaN and related alloys and heterostructures. For example, lasers can utilize structures formed from GaN-based materials, but because there is no reverse bias in such structures, there has been little need for the incorporation of edge-termination structures such as the implanted regions disclosed herein. On the other hand, now that various structures, including high-voltage P-i-N diodes and other semiconductor devices, can be formed on GaN and related alloys and heterostructures, the implanted regions provided herein can play a valuable role in ensuring the structures do not suffer from the adverse effects of edge field crowding.
The properties of the first GaN epitaxial layer 201 can also vary, depending on desired functionality. The first GaN epitaxial layer 201 can serve as an intrinsic region for the P-i-N diode, being substantially undoped or unintentionally doped, or may serve as the drift region of a PN diode and therefore can be a relatively low-doped material. For example, the first GaN epitaxial layer 201 can have an n− conductivity type, with dopant concentrations ranging from 1×1014 cm−3 to 1×1018 cm−3. Furthermore, the dopant concentration can be uniform, or can vary, for example, as a function of the thickness of the intrinsic region.
The thickness of the first GaN epitaxial layer 201 can also vary substantially, depending on the desired functionality. As discussed above, homoepitaxial growth can enable the first GaN epitaxial layer 201 to be grown far thicker than layers formed using conventional methods. In general, in some embodiments, thicknesses can vary between 0.5 μm and 100 μm, for example. Resulting parallel plane breakdown voltages for the P-i-N diode can vary depending on the embodiment. Some embodiments provide for breakdown voltages of at least 100V, 300V, 600V, 1.2 kV, 1.7 kV, 3.3 kV, 5.5 kV, 13 kV, or 20 kV.
Different dopants can be used to create n- and p-type GaN epitaxial layers and structures disclosed herein. For example, n-type dopants can include silicon, oxygen, selenium, tellurium, sulfur, or the like. P-type dopants can include magnesium, beryllium, calcium zinc, or the like.
The thickness of the second GaN epitaxial layer 301 can vary, depending on the process used to form the layer and the desired functionality of the P-i-N diode. In some embodiments, the thickness of the second GaN epitaxial layer 301 may be between 0.1 μm and 5 μm.
The second GaN epitaxial layer 301 can be highly doped, for example in a range from about 5×1017 cm−3 to about 1×1019 cm−3. Additionally, as with other epitaxial layers, the dopant concentration of the second GaN epitaxial layer 301 can be uniform or non-uniform as a function of thickness. In some embodiments, the dopant concentration increases with thickness, such that the dopant concentration is relatively low near the first GaN epitaxial layer 201 and increases as the distance from the first GaN epitaxial layer 201 increases. Such embodiments provide higher dopant concentrations at the top of the second GaN epitaxial layer 301 where metal contacts can be subsequently formed. Other embodiments utilize heavily doped contact layers (not shown) to form contacts.
One method of forming the second GaN epitaxial layer 301, and other layers described herein, can be through a regrowth process that uses an in-situ etch and diffusion preparation processes. These preparation processes are described more fully in U.S. patent application Ser. No. 13/198,666, filed on Aug. 4, 2011, the disclosure of which is hereby incorporated by reference in its entirety.
In other embodiments, second GaN epitaxial layer 301 may be formed by selective epitaxial regrowth. For example, a masking material that inhibits the epitaxial growth of GaN may be formed on surfaces 502 prior to the formation of second GaN epitaxial layer 301. When second GaN epitaxial layer 301 is grown, it will not grow on the masking material (e.g. silicon dioxide or silicon nitride). The masking material may then be removed, leaving the structure shown in
The ion implantation can be performed through mask openings formed in a layer of photoresist, silicon dioxide, or other suitable masking materials. In one embodiment, the same mask that was used to expose surfaces 502 may also be used to mask the ion implantation. In other embodiments, a metal contact layer coupled to the remaining portion of the second GaN epitaxial layer 301 (see, e.g., metal structure 701 of
The ion implantation process illustrated in
As described elsewhere herein, the conductivity of the epitaxial layer(s) can be modified using an ion implantation process to reduce the conductivity with respect to the unimplanted state. The conductivity of the epitaxial layer will depend, in part, on the active dopants or charge in the epitaxial layer times the thickness of the layer (i.e., the integrated charge in the layer). The ion implantation processes used herein implant ionic species to increase the resistivity (i.e., decrease the conductivity) of predetermined portions of the epitaxial layer, which can provide a spatial variation or modulation in the conductivity. Without limiting embodiments of the present invention, the inventors believe that the implantation process reduces the conductivity by at least one of the following mechanisms: compensating for dopants, annihilating dopants, increasing vacancy density, increasing void density, decreasing the total net charge in the epitaxial layer, decreasing the density of ionized acceptors (donors for n-type material), some or all of which may provide for increased resistivity. Throughout the specification, reference is made to decreased conductivity or increased resistivity, which can also be referred to as a decrease in active charge, a decrease in active dopant species, a decrease in charge density, or the like. Due to the robust nature of GaN-based materials, ion implantation can produce implanted ions interspersed with unchanged epitaxial material, effectively reducing the conductivity in an averaged sense, with voids or vacancies interspersed in the lattice with as-grown epitaxial material. The present invention is not limited by the physical mechanism resulting in the spatial conductivity modulation.
Utilizing embodiments of the present invention, it is possible to provide a charge density in the implanted region that is substantially lower than a charge density in the surrounding epitaxial layer. According to one embodiment, for example, the charge density in the implanted region is reduced by at least 90%. According to other embodiments, the charge density in the implanted region is reduced by at least 95% or at least 99%.
This causes the depletion region in the first GaN epitaxial layer 201 (formed by the junction between the remaining portion of the second GaN epitaxial layer 301 and the first GaN epitaxial layer 201) to be pushed away from the edge of the remaining portion of the second GaN epitaxial layer 301, reducing the effects of edge field crowding. The critical electric field (i.e. magnitude of electric field at which avalanche breakdown occurs) may also be significantly higher within implanted region 601 in comparison to other portions of the first GaN epitaxial layer 201, which may further increase the breakdown voltage of the P-i-N diode.
The implanted ion species may be argon, nitrogen, helium, hydrogen, or other appropriate species at doping concentrations to dramatically reduce the conductivity of the resulting isolation implanted region(s) 601. Multiple implantations may be performed through the same mask opening, each implant being performed at a different energy, such that the implanted profiles extend deeper vertically, without a need to diffuse the dopants using a high temperature drive-in process. Thus, although the implanted regions are illustrated as a homogeneous material in
In one embodiment, implanted region(s) 601 may comprise three nitrogen implantations performed with first, second, and third implantation energies of about 20 to 60 keV, about 100 to 200 keV, and about 300 to 500 keV, respectively. These nitrogen implant doses may be in the range of 5×1012 to 1×1016 cm−2. In another embodiment, a single argon implant may be used with energy of 20 to 100 keV and a dose in the range of 1×1012 to 5×1016 cm−2. After the ion implantation process(es), an optional high-temperature anneal may be performed to activate the implanted ions and/or repair damage in the III-nitride material which may be introduced by the ion implantation.
The physical dimensions of the isolation implanted region(s) 601 can vary, depending on desired functionality. In some embodiments, for example, the depth 602 of the isolation implanted region(s) 601 can be 0.1 μm to 1 μm or greater. Furthermore, according to some embodiments, the width 603 of the isolation implanted region(s) 601 can be 0.5 μm to 10 μm or greater. In yet other embodiments, one or more portions of the second GaN epitaxial layer 301 also may be implanted during ion implantation.
Although some embodiments provided herein are discussed in terms of GaN substrates and GaN epitaxial layers, the present invention is not limited to these particular binary III-V materials and is applicable to a broader class of III-V materials, in particular III-nitride materials. Additionally, although a GaN substrate 200 is illustrated in
Some embodiments provided in relation to the fabrication process illustrated in
Additionally, although described in relation to the fabrication of a P-i-N diode, the techniques provided herein for the formation of edge termination region can be applied to a variety of structures including, but not limited to, PN diodes, Schottky barrier diodes, vertical junction field-effect transistors (JFETs), thyristors, bipolar transistors, and other semiconductor devices.
The method further includes forming a second III-nitride epitaxial layer coupled to the first III-nitride epitaxial layer (830). As indicated earlier, the second III-nitride epitaxial layer can have an opposite conductivity type than the first III-nitride epitaxial layer and III-nitride substrate. Where the first III-nitride epitaxial layer is an n− GaN epitaxial layer, for example, the second III-nitride epitaxial layer may be a p-type GaN epitaxial layer.
The method further includes removing a portion of the second III-nitride epitaxial layer to expose a portion of the first III-nitride epitaxial layer (840). This allows for subsequent ion implantation near the edge of the active region of the III-nitride device to provide edge termination. As indicated previously, the removal process can include a variety of processes, such as etching. The physical dimension of the portions removed by the removal process can vary, depending on a variety of factors (e.g., dimensions of the subsequently formed edge termination regions, operation voltage, etc.), as will be appreciated by one of ordinary skill in the art.
The method further includes implanting ions into a region of the exposed portion of the first III-nitride epitaxial layer physically adjacent to a remaining portion of the second III-nitride epitaxial layer to reduce the charge of the region (850). The reduced charge in the region expands the depletion region near the edge of the active region of the III-nitride device, creating an edge termination region that mitigates edge field crowding effects that would reduce the breakdown voltage of the III-nitride device.
A first metal structure is coupled to a remaining portion of the second III-nitride epitaxial layer (860) to form a first electrical contact to the III-nitride device. As stated earlier, some embodiments may include forming the first metal structure before implanting ions into the region of the exposed portion of the first III-nitride epitaxial layer in order to use the first metal structure as a mask during the ion implantation process. A second metal structure is coupled to the III-nitride substrate (870) to form a second electrical contact to the III-nitride device.
It should be appreciated that the specific steps illustrated in
Rather than remove portions of the second GaN epitaxial layer 301 to provide for direct ion implantation of the first GaN epitaxial layer 201, the embodiment of
As illustrated in
The metal structure 903 may extend laterally over the isolation implanted regions(s) 901 for a distance 904 before contacting the dielectric layer 902. This distance 904 can vary depending on application, but generally can be 0.5 μm to 10 μm or greater. Additionally, the distance 905 of lateral overlap of the metal structure 903 with the dielectric layer 902 can vary. According to some embodiments, the distance 905 is greater than 1 μm. According to one embodiment, for example, the distance 905 is 5 μm. One of ordinary skill in the art would recognize many variations, modifications, and alternatives.
In another embodiment, the dielectric layer 902 may be eliminated, and the metal structure 903 may extend over a portion of the implanted region(s) 901. In yet other embodiments, the dielectric layer 902 may be replaced with an insulating layer such as unintentionally doped GaN, aluminum nitride, aluminum gallium nitride, or the like. Here, unintentionally doped GaN can include a GaN lay with net background or other dopant levels of approximately 1×1014 cm−3 to 1×1015 cm−3. In one embodiment, this insulating layer may be grown in-situ when the first GaN epitaxial layer 201 and second GaN epitaxial layer 301 are formed, providing very high quality material with excellent interface between the second GaN epitaxial layer 301 and the overlying insulating material. This insulating material may be masked and etched to expose the active portion of the second GaN epitaxial layer 301 prior to formation of the metal structure 903.
It should be appreciated that the specific steps illustrated in
It is also understood that the examples and embodiments described herein are for illustrative purposes only and that various modifications or changes in light thereof will be suggested to persons skilled in the art and are to be included within the spirit and purview of this application and scope of the appended claims.
This application is a continuation of U.S. patent application Ser. No. 14/454,524, filed on Aug. 7, 2014, the disclosure of which is incorporated by reference herein in its entirety for all purposes. Additionally, following regular U.S. patent applications are incorporated by reference into this application for all purposes: application Ser. No. 13/270,606, filed Oct. 11, 2011, entitled “METHOD AND SYSTEM FOR FLOATING GUARD RINGS IN GAN MATERIALS”;application Ser. No. 13/300,028, filed Nov. 18, 2011, entitled “GAN-BASED SCHOTTKY BARRIER DIODE WITH FIELD PLATE”;application Ser. No. 13/299,254, filed Nov. 17, 2011, entitled “METHOD AND SYSTEM FOR FABRICATING FLOATING GUARD RINGS IN GAN MATERIALS.”application Ser. No. 13/335,329, filed Dec. 22, 2011, entitled “METHOD OF FABRICATING A GAN P-I-N DIODE USING IMPLANTATION”; andapplication Ser. No. 13/335,355, filed Dec. 22, 2011, entitled “FABRICATION OF FLOATING GUARD RINGS USING SELECTIVE REGROWTH”.
| Number | Name | Date | Kind |
|---|---|---|---|
| 8592298 | Romano et al. | Nov 2013 | B2 |
| 8643134 | Raj et al. | Feb 2014 | B2 |
| 8749015 | Disney et al. | Jun 2014 | B2 |
| 20030006453 | Liang et al. | Jan 2003 | A1 |
| 20030045035 | Shenai et al. | Mar 2003 | A1 |
| 20040124435 | D'Evelyn et al. | Jul 2004 | A1 |
| 20090085166 | Iwamuro et al. | Apr 2009 | A1 |
| 20100032685 | Zhang | Feb 2010 | A1 |
| 20100301351 | Flynn et al. | Dec 2010 | A1 |
| 20110198693 | Shiomi et al. | Aug 2011 | A1 |
| 20130087835 | Edwards et al. | Apr 2013 | A1 |
| 20130126885 | Disney | May 2013 | A1 |
| 20140346527 | Kizilyalli | Nov 2014 | A1 |
| Number | Date | Country |
|---|---|---|
| 102084487 | Jun 2011 | CN |
| 102187433 | Sep 2011 | CN |
| 104011865 | Aug 2014 | CN |
| 104094417 | Oct 2014 | CN |
| 2013096013 | Jun 2013 | WO |
| Entry |
|---|
| CN201280068139.9, Office Action, Apr. 27, 2016, 8 pages. |
| CN201280068139.9, Office Action, Sep. 25, 2015, 8 pages. |
| PCT/US2012/068972, International Search Report and Written Opinion for PCT/US2012/068972, PCT/US2012/068972, Feb. 20, 2013, 12 Pages. |
| Number | Date | Country | |
|---|---|---|---|
| 20150364612 A1 | Dec 2015 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 14454524 | Aug 2014 | US |
| Child | 14834306 | US | |
| Parent | 13335329 | Dec 2011 | US |
| Child | 14454524 | US |
