1. Field of the Invention
The present invention is related to a method of forming a metal gate structure, and more particularly, to a method of forming a metal gate structure with an oxidation process.
2. Description of the Prior Art
Poly-silicon is conventionally used as a gate electrode in semiconductor devices, such as the metal-oxide-semiconductor (MOS). However, with a trend toward scaling down the size of semiconductor devices, the conventional poly-silicon gate has faced problems such as inferior performance due to boron penetration and unavoidable depletion effect which increases equivalent thickness of the gate dielectric layer, reduces gate capacitance, and worsens a driving force of the devices. Therefore, work function metals are used to replace the conventional poly-silicon gate to be the control electrode that is suitable for use as the high-k gate dielectric layer.
In a complementary metal-oxide semiconductor (CMOS) device, one of the dual work function metal gates is used in an NMOS device and the other one is alternatively used in a PMOS device. It is well-known that compatibility and process control for the dual metal gate are more complicated, meanwhile thickness and composition controls for materials used in the dual metal gate method are more precise. The conventional dual metal gate methods are categorized into gate first processes and gate last processes. In a conventional dual metal gate method applied with the gate first process, the annealing process for forming the source/drain ultra-shallow junction, and the silicide process are performed after forming the metal gate. In the conventional gate last process, a sacrifice gate or a replacement gate is provided and followed by performing processes used to construct a normal MOS transistor. Then, the sacrificial/replacement gate is removed to form a gate trench. Consequently, the gate trench is filled with metals according to the different electrical requirements. However, because of the complicated steps of the gate last processes, the manufacturers are devoted to simplifying the manufacturing process.
In the gate first process or the gate last process, the metal gate of the PMOS or the NMOS may include a plurality of metal layers. The materials of the metal layers always affect the work function of the NMOS or the PMOS, therefore affect the performance of the product. Thus, the manufacturers are searching for new manufacturing method to obtain a MOS with better work function performance.
The present invention therefore provides a method of forming a metal gates structure, which exhibits good electrical performance.
According to one embodiment of the present invention, the method of forming a metal gate structure has the following steps. A substrate and a dielectric layer with a trench are provided. Next, a work function metal (WFM) layer is formed in the trench, following by performing an oxidation process under a vacuum condition to oxidize a part of the WFM layer to form an oxidized WFM layer. Thereafter, a conductive layer is formed on the oxidized WFM layer to complete fill the trench.
The present invention eliminates the needs to transfer the wafer out from the apparatus to the oxidized WFM layer and one only deposition apparatus is needed to conduct all the metal gate deposition processes (in-situ deposition and oxidation). Moreover, since the oxidation process is performed by supplying oxygen containing gas in the chamber, instead of the atmosphere in conventional arts, and it can be carried out with an annealing process, the quality of the oxidized WFM layer and the throughput of the process can be upgraded.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
To provide a better understanding of the presented invention, preferred embodiments will be made in detail. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements.
Please refer to
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In one embodiment, the factory interface 200 comprises at least one docking station 202, at least one factory interface robot 204 to facilitate transfer of wafer or object. The docking station 202 is configured to accept one or more front opening unified pod (FOUP). Four FOUPS 204A, 204B, 204C and 204D are shown in the embodiment of
Each of the loadlock chambers 104A, 104B have a first port coupled to the factory interface 200 and a second port coupled to the transfer chamber 106A. The loadlock chamber 104A, 104B are coupled to a pressure control system (not shown) which pumps down and vents the chambers 104A, 104B to facilitate passing the wafer between the vacuum environment of the transfer chamber 106A and the substantially ambient (e.g., atmospheric) environment of the factory interface 200. Therefore, the platform 100 of the deposition apparatus 1000 can be maintained in an ultrahigh vacuum environment.
A robot arm 110A disposed in the transfer chamber 106A can transfer the substrate 120 between the load lock chambers 104A, 104B, the processing chambers 102A, 102F, the temporary chambers 108A, 108B, and the service chambers 112A, 112B. A robot arm 110B disposed in the transfer chamber 106B can transfer the substrate 120 between the processing chambers 102B, 102C, 102D, 102E, and the temporary chambers 108A, 108B. The temporary chambers 108A, 108B are used to maintain ultrahigh vacuum conditions while allowing substrate 120 to be transferred between the transfer chamber 106A and the transfer chamber 106B within the platform 100. Each processing chamber 102A-102F may be configured to perform one of a number of substrate processing operations, such as cyclical layer deposition (including atomic layer deposition (ALD)), chemical vapor deposition (CVD), physical vapor deposition (PVD), pre-clean, de-gas, orientation and other substrate processes. The detailed description of the chambers will be shown in the following context. An optional service chamber 112A, 112B may be coupled to the transfer chamber 103. In one embodiment, optional service chambers 112A, 112B may be configured to perform other substrate processes, such as degassing, orientation, pre-cleaning process, cool down and the like, but is not limited thereto.
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Generally, in comparison with other chambers, the temporary chamber 108A, 108B does not perform deposition process so no deposition unit (for example, the target 412 or the deposition electrode 416) is installed herein. In some embodiment, the temporary chamber 108A, 108B can install the gas source 406 and/or a heater in the pedestal 410, so as to provide required gas or temperature.
Please refer to
Step 500: providing a substrate and a dielectric layer with a trench;
Step 502: forming a work function metal (WFM) layer in the trench;
Step 504: performing an oxidation process under a vacuum condition to oxidize a part of the WFM layer to form an oxidized WFM layer; and
Step 506: forming a conductive layer on the oxidized WFM layer to completely fill the trench.
For the detail description, please refer to
In one embodiment, the transistor 604 includes an interfacial layer 606, a gate dielectric layer 608, an etching stop layer 610, a sacrifice gate 612, a capping layer 614, a spacer 616, alight doped drain (LDD) 618 and a source/drain 620, for example. In one preferred embodiment of the present invention, the interfacial layer 606 includes SiO2 which is formed by an oxidation process for example. The gate dielectric layer 608 is comprised of high-k material, for example, rare earth metal oxide or lanthanide oxide, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta2O5), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO), yttrium oxide (Yb2O3), yttrium silicon oxide (YbSiO), zirconium aluminate (ZrAlO), hafnium aluminate (HfAlO), aluminum nitride (AlN), titanium oxide (TiO2), zirconium oxynitride (ZrON), hafnium oxynitride (HfON), zirconium silicon oxynitride (ZrSiON), hafnium silicon oxynitride (HfSiON), strontium bismuth tantalite (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi1-xO3, PZT) or barium strontium titanate (BaxSr1-xTiO3, BST), but is not limited thereto. The etching stop layer 610 includes metal or metal nitride, such as Ti, TiN, Ta, TaN, Ti/TiN, Ta/TaN or their combination. The sacrifice gate 612 comprises poly-silicon, amorphous silicon or germanium. The capping layer 614 is an optional layer including SiN or SiO2. The spacer 616 can be a multilayered structure including high temperature oxide (HTO), SiN, SiO or SiN formed by hexachlorodisilane (Si2Cl6) (HCD-SiN). The LDD 618 and the source/drain 620 are formed by appropriate implant doping. In one embodiment, the interfacial layer 606 is about 10 angstroms, the gate dielectric layer 608 is about 20 angstroms, and the etching stop layer 610 is about 20 angstroms. After forming the transistor 604, a contact etch stop layer (CESL) 622 and an inter-layer dielectric (ILD) layer 624 are formed on the substrate 600 to cover the transistor 604.
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After forming the oxidized WFM layer 634, the wafer with the substrate 600 is transferred to the next chamber, such as the processing chamber 102B in
After the above-mentioned deposition processes, the wafer with the substrate 600 is transferred out from the deposition apparatus 1000, and as shown in
The above embodiment shows forming the high-k gate dielectric layer at first (namely, the “high-k first” process). However, those skilled in the art can realize that, in the present invention, it is also available to form the high-k gate dielectric layer after removing the sacrifice gate (namely, the “high-k last” process). In this embodiment, the etching stop layer 610 can be omitted.
As described above, in one embodiment, the steps of deposition the metal layers of the metal gate is preferably carried out in the same deposition apparatus 1000 and under an ultra-high vacuum environment. No air-broken process is used during forming the WFM layer and forming the oxidized WFM layer. In conventional procedure, these deposition steps usually require two deposition apparatus, one for forming the bottom barrier layer and the WFM layer and the other for forming the top barrier layer and the conductive layer. In some cases, a small part of the WFM would be oxidized to form the oxidized WFM layer when the wafer is transferred from one deposition apparatus to another deposition apparatus, and an air broken step occurs. However, since the oxidized WFM layer is formed outside the deposition apparatus, it is under a room temperature and an atmosphere pressure, taking more than 2-4 hours to completely the oxidation process. In comparison, the present invention eliminates the needs to transfer the wafer out from the apparatus and one only deposition apparatus is needed to conduct all the metal gate deposition processes (in-situ deposition and oxidation). It is particularly advantageous in the present invention that the oxidation process can be performed with an annealing process, the overall throughout can therefore be upgraded.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.