This application claims the priority of Chinese patent application number 201310217267.1, filed on Jun. 3, 2013, the entire contents of which are incorporated herein by reference.
The present invention relates generally to the semiconductor technology, and more particularly, to forming sigma (Σ)-shaped trenches.
With the advancing of semiconductor manufacturing technology, critical dimensions of semiconductor devices shrink increasingly. For example, when to fabricate a P-Type metal oxide semiconductor (PMOS) transistor with a critical dimension of 40 nm or below, the employment of the embedded silicon-germanium (SiGe) epitaxial growth process is needed for increasing a drive current of the PMOS transistor. Before the SiGe epitaxial growth process, a trench forming process is needed to form a trench in the silicon substrate. The trench typically resembles in shape either the capital U or the capital Greek letter sigma (Σ), in which, the Σ-shaped one can better increase the drive current since the outer periphery of which is closer to the conductive channel of the transistor.
In the above-described method, the wet etching process determines how the horizontal width of the Σ-shaped trench 50 varies. That is, a maximum width L of the Σ-shaped trench 50 is determined by a vertical depth H (referring to
The present invention is directed to a method of forming a Σ-shaped trench to simplify the process and enable geometric variations of the Σ-shaped trench.
The present invention provides, in one aspect, a method of forming a Σ-shaped trench, which includes: providing a silicon substrate; and performing a plasma etching process to form a Σ-shaped trench in the silicon substrate. The plasma etching process includes: etching the silicon substrate using a first plasma etching gas including a sulphur-containing fluoride; and etching the silicon substrate using a second plasma etching gas including a sulphur-containing fluoride and a polymer gas.
Further, the first plasma etching gas may contain SF6 supplied at a flow rate of 5 SCCM to 20 SCCM and the silicon substrate is etched using the first plasma etching gas in an etching chamber under a pressure of 40 mTorr to 60 mTorr, at an etching power of 200 W to 300 W and at a bias power of 0 W for 15 seconds to 25 seconds.
Further, the second plasma etching gas may contain SFS supplied at a flow rate of 5 SCCM to 10 SCCM and a polymer gas formed of HBr supplied at a flow rate of 20 SCCM to 50 SCCM and O2 supplied at a flow rate of 2 SCCM to 10 SCCM; the silicon substrate may be etched using the second plasma etching gas in an etching chamber under a pressure of 5 mTorr to 10 mTorr, at an etching power of 100 W to 200 W and at a bias power of 200 W to 300 W for 10 seconds to 20 seconds.
Further, the Σ-shaped trench may have a horizontal width gradually increasing to a maximum and then gradually decreasing, from a surface of the silicon substrate downwards.
The present invention provides, in another aspect, a method of forming a semiconductor device, which includes: providing a silicon substrate having two gate structures formed thereon and forming a protective layer over the silicon substrate; performing a plasma etching process on the protective layer and the underlying silicon substrate to form a Σ-shaped trench in a portion of the silicon substrate between the two gate structures; and forming a SiGe epitaxial layer in the Σ-shaped trench; wherein the plasma etching process includes: etching the protective layer to expose a surface of the silicon substrate using a first plasma etching gas including a carbon-containing fluoride; etching the portion of the silicon substrate between the two gate structures using a second plasma etching gas including a sulphur-containing fluoride; and etching the portion of the silicon substrate between the two gate structures using a third plasma etching gas including a sulphur-containing fluoride and a polymer gas.
Further, the protective layer may be fabricated by silicon nitride and may have a thickness of 100 Å to 150 Å. Further, the first plasma etching gas may contain CF4 supplied at a flow rate of 50 SCCM to 100 SCCM.
As indicated above, the present invention has the following advantages over the prior art.
The Σ-shaped trench is formed only by employing the plasma etching process whilst not employing the wet etching process, therefore, the wet etching process apparatuses are not needed, thus simplifying the process. Further, as plasma (dry) etching processes are better controllable than wet etching processes, the Σ-shaped trench formation process of the present invention could be more precisely controlled and result in a Σ-shaped trench having an outer periphery closer to the conductive channel of the transistor and thereby further improving a drive current thereof.
The present invention provides a method of forming a sigma (Σ)-shaped trench and a method of forming a semiconductor device using the same.
As illustrated in
In a second step S2, a plasma etching process is performed to form a Σ-shaped trench in a portion of the silicon substrate between the two gate structures.
Lastly, in a third step S3, a silicon-germanium (SiGe) epitaxial layer is formed in the Σ-shaped trench.
The invention is explained in greater detail below on the basis of exemplary embodiments and the figures pertaining thereto.
Referring now to
Next, referring to
Lastly, referring to
In the illustrated embodiment, the first plasma etching gas includes carbon tetrafluoride (CF4) supplied at a flow rate of 50 standard cubic centimeters per minute (SCCM) to 100 SCCM for 20 seconds to 40 seconds to remove portions of the protective silicon nitride layer 300. Additionally, the second plasma etching gas includes sulfur hexafluoride (SF6) supplied at a flow rate of 5 SCCM to 20 SCCM, and the silicon substrate is etched in an etching chamber under a pressure of 40 mTorr to 60 mTorr, at an etching power of 200 W to 300 W and at a bias power of 0 W for 15 seconds to 25 seconds. Furthermore, the third plasma etching gas consists of SF6 and a polymer gas formed by HBr and O2, where HBr is supplied at a flow rate of 20 SCCM to 50 SCCM, O2 is supplied at a flow rate of 2 SCCM to 10 SCCM, SF6 is supplied at a flow rate of 5 SCCM to 10 SCCM, and the silicon substrate is etched in an etching chamber under a pressure of 5 mTorr to 10 mTorr, at an etching power of 100 W to 200 W and at a bias power of 200 W to 300 W for 10 seconds to 20 seconds.
In one embodiment, the plasma etching process is performed by sequentially introducing the first, second and third etching gases in a LAM Kiyo or kiyo45 etching tool.
As described herein, the Σ-shaped trench 400 is formed by using different plasma etching gases, among which, SF6 has an isotropic characteristic and hence determines the width of the Σ-shaped trench 400, while HBr has an anisotropic characteristic and hence determines the depth of the Σ-shaped trench 400 together with SF6. The profile of the Σ-shaped trench 400 being etched could be controlled by adjusting the flow rates and etching time of the respective plasma etching gases. The Σ-shaped trench 400 formed has an outer periphery closer to the conductive channel of the transistor and the Σ-shaped trench 400 is formed only by employing the plasma etching process whilst not employing the wet etching process, therefore, the wet etching process apparatuses are not needed, thus simplifying the process. In addition, a so-called sidewall spanning distance D (as shown in
The preferred embodiments described herein are intended to explain aspects and features of the inventive technology in sufficient detail to enable those skilled in the art to understand and practice the technology, but not intended to limit the scope of the present invention in any way. Therefore, all modifications, substitutions and the like made without departing from the scope of the present invention are considered to be within the scope of the invention.
Number | Date | Country | Kind |
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201310217267.1 | Jun 2013 | CN | national |