The present exemplary embodiments relate to in-process intralayer defect detection and correction and interlayer shunt defect detection and correction. It finds particular application to Printed Organic Electronics (POE) arrays, but can be applied to a wide variety of electronic arrays including, for example, liquid crystal displays (LCD), memory arrays (RAM, ROM, etc.), printed circuit boards (PCB), active matrix displays, and passive matrix displays.
With respect to conventional array fabrication processes, forming patterns using traditional photolithographic mask printing methods is highly productive in producing parts that have the exact same pattern over and over again. With this approach, substrate die yield is highly dependent on the absence of process artifacts (i.e. particles etc). If these artifacts cause a line open in the electrical circuitry, repair by localized line reconnection is expensive, tedious, time consuming and may not be practical. Defective dies are usually marked and rejected after die dicing. When die size becomes very large, as in for example, a POE array or a flat panel display (FPD), rejecting such a large die (large real estate) can be very costly. Moreover, bad or poor NSN+ amorphous silicon chemical vapor deposition (CVD) sometimes makes the substrates un-testable as the matrix arrays become non-functional. In particular, process defects due to layer to layer electrical shunts can sometimes disable an entire read out chip making defect isolation and defect locating impossible. The chip, even if working, may produce unreliable results for detection purposes.
Traditionally, electrical evaluation of array matrices has been performed as a final step (as opposed to an in-process step) in the array matrix fabrication process and has been accomplished by contact or non-contact probing of I/O (input and output) pads that have been patterned and defined. A typical array matrix's large physical size can present quite a challenge for such a high I/O test pad connection count to the outside world. For example, most POE arrays have a very large number of DATA and GATE interconnect lines that require testing. In order to manage electrical testing on such a large physical substrate form factor, contact type probe card based testers such as those from Tokyo Cathode Laboratory and flying probe testers such as those from Acculogic have been used. However, these probe testers (or probers) are capital intensive and do not usually fully test the multilevel device matrix. Static multiple probe approaches (“bed of nail” type) have also been used. The apparatus described in U.S. Pat. No. 6,834,243 (“Apparatus and method for electrical testing of electrical circuits”) is an example that is suitable for high probe count electrical testing. However these “bed of nail” methods require custom fixturing for each device design and are hence very costly.
An example of a LCD panel final test is illustrated by the LCD evaluation method described in U.S. Pat. No. 5,081,687 and RE37,847. This evaluation method uses a video image capture method to detect FPD matrix electrical opens and shorts by comparing the newly acquired display pattern to a previously captured golden standard sample display image pattern result. For these types of measurement, the FPD is energized through contact type edge shorting bars. This approach is also capital intensive and requires the full process fabrication of the device matrix to the pixel level formation so that the LCD panel can be tested. Another approach for testing POE arrays uses an x-ray imaging system after the formation of the active matrix thin film transistors (TFTs). The x-ray images produced by the imaging system show horizontal and vertical defect lines. However, it is very difficult to quantify the exact cause of such line defects. For example,
Later developed processes utilize peripheral shorting bars and/or short circuit rings. For example, U.S. Pat. No. 7,330,583 (“Integrated visual imaging and electronic sensing inspection systems”) utilizes shorting bars to expand the video image capture method to various electronic sensing means such as voltage, e-beam and charge sensing. These shorting bars and/or short circuit rings can be classified into full ring structures or grouped into segmented shorting bar structures. The full ring structures are typically used for static electricity mitigation to protect the array matrix device pixels. An example of this is found in U.S. Pat. No. 5,650,834 (“Active-matrix device having silicide thin film resistor disposed between an input terminal and a short-circuit ring”), where silicided resistors positioned between the edge short circuit ring and the interior array matrix provide static electricity protection for the pixel thin film transistors (TFT).
Another example of an LCD panel final test evaluation is illustrated by Orbotech Ltd.'s evaluation method illustrated in U.S. Pat. No. 5,771,068 (“Apparatus and method for display panel inspection”). This final test evaluation used a full field image sensor to capture and analyze a FPD matrix that was stimulated with various pixel patterns.
Non-contact probing methods have also been used. U.S. Pat. No. 6,630,832 (“Method and apparatus for the electrical testing of printed circuit boards employing intermediate layer grounding”) used stimulating and sensing heads and various AC frequencies to probe printed circuit boards (PCBs).
The prior art methods mentioned above apply predominantly to the final stage of testing matrix arrays. Since matrix arrays become a high value added item when fabrication approaches the formation of array pixels, device rejection at this final test stage due to line open, line bridge (i.e. short), and shunt defects becomes very costly. It is thus desirable to have an in-process (or in-fabrication) approach to electrical testing for matrix arrays that is thorough and effective for open, short and shunt defect detection. The exemplary methods and systems utilize a hybrid static peripheral I/O connection method in conjunction with a dynamic probing scheme, an arrangement of sacrificial edge shorting bars (with or without cut lines), and an analytical method to determine defect type and defect locations. For these methods and systems, a previously measured golden standard reference sample result is not required.
The presently described embodiments relate to an in-process method of detecting DATA and GATE line defects and an in-process method of detecting shunts between the DATA and GATE layers.
In one aspect, a method and system for in-process yield evaluation and correction in an array type of device are provided. The method and system include measuring an electrical property between individual GATE lines, DATA lines, a DATA bus I/O pad, and a GATE bus I/O pad; and analyzing the measured electrical resistance or capacitance to identify at least one of the following: GATE line open defects, GATE line bridge defects, DATA line open defects, DATA line bridge defects, and interlayer shunt defects.
In another aspect, a method and system for in-process correction of defects in an array type of substrate are provided. The method and system include receiving identified defect types, locations, and process state and dynamically reconfiguring a die or chip design to account for defects on the substrate based at least partially on the received defect types, locations and process state.
a and 7b illustrate a data plot of the measured resistance for an array matrix both before and after a shunt repair is performed;
a and 8b illustrate a data plot of the measured resistance for an array matrix both before and after a shunt repair is performed using a differential data analysis technique;
a illustrates a close-up view of an interlayer shunt defect;
b illustrates the correction of the interlayer shunt defect of
Aspects of the present exemplary embodiments relate to a system and method for in-process detection and/or correction of intralayer opens and bridges, and interlayer shunts between metal layers, in an array type of device (such as passive matrix or active matrix) during the manufacturing process. The utilization of electrical measurements and data analysis result in identifying potential defect locations and enabling in-process yield assessment and repairs. The exemplary embodiment, in one form, operates on Printed Organic Electronics (POE) arrays. However, the proposed systems and methods can operate on any electronic array including, for example, printed circuit boards, liquid crystal displays, active matrix displays, passive matrix displays, and memory arrays. Also, the exemplary embodiment, in one form, operates on array design architectures constructed with peripheral bus structures which are particularly suited for in-process detection.
In one exemplary embodiment, the POE matrix array is mounted onto a stage carrier in preparation for electrical measurements. Electrical measurements of the matrix lines are performed by connecting a probe to the matrix array. For convenience, a standard commercial IC probe station with a probe card may be used to probe the matrix lines. The probe station contains a switching matrix which switches the tension of the testing instrument to each one of the lines, one at a time. This type of probe equipment does not require the purchase of an expensive dedicated system. The parts are available off the shelf.
Additionally, the exemplary embodiments described here measure electrical resistance across the matrix array. However, the exemplary embodiments may measure capacitance or any other electrical property instead of resistance to achieve the desired goals.
Identifying Intra-Layer Line Opens
For the DATA line (Dline) open measurements, the Dline to DATA pad (Dpad) resistance is sampled across the matrix 300 from the Dpad 302 to the individual Dlines 308a-308n, using a probe 309, 310 or other measurement device connected to the system controller 204. Each combination of Dline to Dpad may be measured. For instance, the first measurement might be from Dpad 302 to Dline 308a, the second measurement from Dpad 302 to Dline 308b, and so on.
In
Similarly, open GATE line (Gline) defect data (represented by horizontal lines in the matrix 400) is collected and analyzed as shown in
For the GATE line (Gline) measurements, the GATE bus links 409 are severed before any measurements are taken. Using a probe 410, 412 or other measurement device connected to the system controller 204, the Gline to GATE pad (Gpad) resistance is sampled across the matrix 400 from the Gpad 406 to the individual Glines 408a-408n. Each combination of Gline 408a-408n to Gpad 406 is measured. For instance, the first measurement might be from Gpad 406 to Gline 408a, the second measurement from Gpad 406 to Gline 408b, and so on. In
Identifying Intra-Layer Line Bridges
Dline bridging is identified by the Dline to Dline probe measurements as illustrated in
For detecting GATE layer bridges, a similar arrangement as that used in
Identifying Interlayer Shunts
In addition to measuring the Dline resistance to the Dpad which reveals the open Dline defects, much can be learned by collecting Dline to Gpad resistance data.
Alternatively, the shunt defect 604 of
With respect to
a and 8b compare Dline differential plots of an array matrix containing a shunt defect both before repair 800 and after repair 802 with a laser ablation process. With the differential data analysis technique, the resistance data is plotted after compensating for environmental factors such as initial line resistance.
With respect to
Correcting Identified Defects
The exemplary embodiments also comprise a method and system for dynamically reconfiguring a die (or chip) design to correct for fabrication defects, such as the open-line, bridge and shunt defects identified and/or identified above. This approach takes advantage of the on-demand printing flexibility of a digital lithography system. Chip fabrication defects are identified during the fabrication process and these faults are intelligently interpreted to redefine the chip circuitry. The chip defect type (i.e., intralayer open, intralayer bridge or interlayer shunt), location, process state and other pertinent information is dynamically input into the system so that the system can dynamically modify and re-route the chip circuitry. The new reconfigured circuitry results in modified mask layers which are then downloaded onto the digital lithography system for the printing of subsequent mask layer for the defective substrate.
The exemplary embodiment described requires no additional equipment or layers for the repairs, which call only for modifications of the specifications for layers that are already part of the circuit design. Although the current embodiment and emphasis is on POE arrays, this methodology can be applied to other devices as well. Trace opens and VIA opens in PCB and other low temperature polysilicon application manufacturing can also benefit by using the exemplary embodiment. These techniques can be used to fix memory arrays, FPD arrays etc. as well.
Referring now to
With respect to
With respect to
With respect to
At step 1900, a GATE pattern is formed on a substrate via a printing process utilizing digital lithography based design.
At step 1902, the system controller (
At step 1904, the Gline resistance measured in step 1902 is plotted and analyzed by the system controller (
At step 1906, additional TFT fabrication processing is performed.
At step 1908, a DATA pattern is formed on the substrate via a printing process utilizing digital lithography based design.
At step 1910, the Dline resistance from the DATA pads to the DATA bus I/O pad and GATE bus I/O pad is measured as shown in
At step 1912, the measured resistance from step 1910 is plotted and analyzed (in a manner similar to step 1904) in order to detect Dline defects and shunt defects. Any defects detected here will be corrected in step 1916.
At step 1914, any necessary additional TFT fabrication processing is performed.
At step 1916, the defect knowledge gained in steps 1904 and 1912 by the system controller (
At step 1918, the fabrication of the TFT POE array matrix is completed. If desired, the fabricated product can then be tested using conventional techniques such as x-ray imaging.
It will be appreciated that various of the above-disclosed and other features and functions, or alternatives thereof, may be desirably combined into many other different systems or applications. Also that various presently unforeseen or unanticipated alternatives, modifications, variations or improvements therein may be subsequently made by those skilled in the art which are also intended to be encompassed by the following claims.
This invention was made with Government Support under Contract Number: 70NANB3H3029 awarded by the National Institute of Standards and Technology. The Government has certain rights in this invention.
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