Patent Application
20220359258
This patent application is a national phase filing under section 371 of PCT/EP2021/050721, filed Jan. 14, 2021, which claims the priority of German patent application 102020102003.1, filed Jan. 28, 2020, each of which is incorporated herein by reference in its entirety.
The present invention relates to a method of manufacturing and passivating a die, comprising an active frontside with an electrically conductive protrusion.
A commonly used method for sealing a die comprises a molding process with several steps requiring pre- and post-treatment to apply one or more protective layers to a semiconductor die.
Further state of the art methods for manufacturing and passivating semiconductors are usually based on a wafer level packaging method and comprise multiple steps. Semiconductor wafers are manufactured, comprising two or more different passivation layers applied on several sides of the wafer in several steps. Usually, the passivation layers are deposited by chemical vapor deposition (CVD). Afterwards the wafer is singulated into dies. Examples of such methods are disclosed in US 2014/0091482 A1 or US 2008/0318396 A1.
United States Patent Application Publication No. 2005/0167799 A1 describes a manufacturing method comprising applying a passivation layer on the backside of a semiconductor wafer, laminating the backside with an adhesive tape and dicing of the wafer. Afterwards, as a pre-treatment step, the adhesive tape is expanded to enlarge the gap between the single semiconductor dies, followed by applying a passivation layer on the frontside and the lateral sides of the semiconductor dies.
All of these methods comprise multiple technical extensive steps comprising several passivation steps and pre-treatment and post-treatment steps to passivate the dies and are therefore time-consuming and cost-intensive.
Embodiments provide an improved and less expensive and time-consuming method for manufacturing and passivating dies.
The method comprises the following steps:
The steps are preferably completed in the disclosed order.
By applying the passivation layer on all sides in one single process step, several time-consuming passivation steps can be avoided.
The protruded area may be a solder bump or a thick film metallization.
The cover member may be a passivation tape.
In one method, the cover member may be a passivation tape comprising a first base layer having a first adhesive layer thereon.
The method may comprise the following steps:
The steps are preferably completed in the disclosed order.
After delaminating the passivation tape no post-treatment steps are necessary. In particular, no chemical post-treatment steps like etching are necessary to remove the passivation layer from the electrical contact area as it would be necessary in a commonly used method. By avoiding this step costs and time can be saved.
The die may comprise a semiconductor material. The semiconductor material may comprise a silicon (Si) material. The die based on a semiconductor material can be used for a micro-electro-mechanical system (MEMS) device for different applications. Alternatively, the die may consist of a mineral material. The mineral material may comprise a ceramic. The die can be used as capacitor, varistor or thermistor.
It is possible that the passivation layer is applied by atomic layer deposition (ALD). In general, passivation layers on semiconductor dies and other dies are usually applied by CVD. In principle, in CVD processes, reactive species react in a gas phase under a controlled atmosphere and elevated temperature to deposit a layer. The CVD process is usually performed at relatively high temperature which may potentially introduce impurities from the gas atmosphere into the layer of deposited material. Technically, such a high required deposition temperature for CVD processes limits the choice and hence the functionality of materials including the tape that are involved in the process.
The ALD process, on the other hand, has the main advantage of being capable of depositing layers in a low temperature regime with high uniformity and quality. In general, ALD as a variant of the CVD process, involves the deposition of a monolayer on any target substrate. Multiple monolayers can be deposited by systematically repeating cycles including dosage of gaseous precursor into a deposition chamber, reacting same with the surface of the target and flushing the chamber with an inert gas to purge out the not chemisorbed precursors. In the present method, the ALD process is preferred considering the introduced tape and the specific required passivation material due to the demanded crucial properties of the passivation layer (electrical, mechanical etc.).
Further embodiments provide a method performed at wafer level and hence provides a wafer level packaging method. In said method dies may be manufactured from a wafer by conducting the following steps:
a) providing a wafer, comprising an active frontside with several protrusions, which are arranged for electrically contacting the die, and a backside. On the active frontside a plurality of device structures for a plurality of single devices may be provided;
b) singulating the wafer into single dies. Each die then comprises device structures that realize a single electrical device. Each die further comprises at least one protrusion made from an electrically conductive material;
c) covering a portion of each protrusion by a cover member. It is significant for this method, that the cover member at least partially covers at least one protrusion on each die;
d) applying a passivation layer on all sides, including the frontside, backside and all lateral sides, of the singulated dies in one step, except on the portions covered by the cover member which form electrical contact areas; and
e) detaching the cover member from the covered portions of the protrusions after applying the passivation layer to expose the portions of the protrusions. No passivation layer covers these portions which are thus defined as electrical contact areas.
The steps are preferably completed in the disclosed order.
The cover member includes a passivation tape.
In a method, the cover member includes a passivation tape comprising a first base layer having a first adhesive layer thereon. The passivation tape is laminated on the portions of each protrusion.
In a preferred method, singulating the wafer in step b) comprises the following steps:
i) partial-cut dicing the wafer into dies, each with at least one protrusion, from the frontside;
ii) laminating a grinding tape comprising a second base layer having a second adhesive layer thereon to the frontside of the wafer. After that step the tape covers the frontside of the dies completely;
iii) singulating the dies by grinding the wafer from the backside. In this step, the continuous wafer layer at the backside of the wafer that remains after the partial-cut dicing step is completely removed;
iv) detaching the grinding tape from the singulated dies.
The introduced lower case letters and roman numbers show an obvious sequence of the several steps of the disclosed process. They can be regarded as reference signs, designating a specified procedure.
Since the dicing step is executed before grinding, the risk of backside chipping and die damaging is minimized in the present method. Therefore, this method allows the processing of thinner dies in comparison with dicing after grinding methods.
The wafer may comprise a semiconductor material like silicon or a mineral material like a ceramic. The single dies singulated from the wafer can be used like the single die described above. Thus the wafer level packaging method enables a simultaneous manufacturing of several micro-electronic devices at the same time.
Because of the advantages described above it is preferable to apply the passivation layer by an ALD process. As a further advantage of the ALD process the layer thickness can be easily controlled even if the passivation layer is deposited in a trench or hole having a high aspect ratio such as e.g. at a dicing street. Hence, also the aspect ratio of the dicing street that is the ratio of dicing depth over width of dicing street can be well defined by the ALD process.
In one embodiment, the surface topography of the frontside and the shape of the protrusions thereon is considered for the selection of the grinding tape.
For example, the second adhesive layer on the grinding tape may be thicker than the first adhesive layer on the passivation tape. This allows adhesion of the grinding tape to the whole surface of the frontside independent of a surface topography and the shape of the protrusions thereon. The thick adhesive layer may cover all structures and shapes that are projecting over the frontside surface.
By using an ALD process, it is possible to keep the distance between two adjacent dies during applying the passivation layer in step d) equal to the width of a dicing street produced during dicing in step i). No further step is taken or required to increase the distance between the dies after singulating the dies and before applying the passivation layer. In conventional processes, the individual dies are mounted onto an appropriate tape. This tape is expanded to increase their mutual distances to a minimum required value. In the disclosed embodiment this additional step can be omitted, saving time and costs.
It is possible to apply a protective layer on the frontside of the wafer before dicing in step i). Said protective layer passivates the frontside of the layer. Furthermore, it allows an exact definition of electrical contact points on the frontside by etching openings for vias in said protection layer to expose a desired area for the contact points. The electrically conductive protrusions are positioned on these contact points. They may be formed by soldering metal on the contact points.
In one method, the backside may be covered with a dicing tape, comprising a third base layer having a third adhesive layer thereon, during partial-cut dicing the wafer into dies from the frontside in order to mechanically protect the backside against possible damages like wafer cracks and the like.
The designations first, second and third base layer and adhesive layer do not refer to the order in which the layers are used during the described process. The designation is for distinction only. The layers are components of different tapes, may comprise different materials and may have different properties.
In one method, one or more of the passivation, the grinding and the dicing tape may be detached by a physical method comprising at least one of UV-exposure, if the adhesive is UV-releasable, or heating, if the adhesive is thermally releasable. Such a physical method weakens the adhesive forces of the tapes and thus makes the releasing step easier.
It is possible that a solder bump for electrical interconnection is applied on the frontside of the wafer before laminating or adhering the passivation tape to the frontside. In this case said protrusion is the solder bump.
Alternatively, a thick film metallization for electrical interconnection may be applied on the frontside of the wafer. In this case said protrusion is the thick film metallization.
The solder bump or the thick film metallization may only partially be covered by the passivation tape in step c). Thus, the passivation layer will be partially applied onto non-covered and still exposed areas of the protrusion, e.g. the bump or the metallization, during step d). The size of an electric contact area can be defined by the size of the surface of the protrusion which is covered by the passivation tape. Hence, this size can be defined exactly.
Embodiments further comprises a die as it can be manufactured by the method described above. The die has a passivation layer covering all sides and edges of the die except an electrical contact area. Furthermore, the passivation layer is uniform, continuous and homogeneous on every side. In one embodiment it also has the same thickness on every side. These properties simplify further processing steps on the die.
In an embodiment, the die may be a semiconductor. The semiconductor may comprise a silicon (Si) or silicon carbide (SiC) material. The semiconductor can be used for a micro-electro-mechanical system (MEMS) device. Alternatively, the die may consist of a mineral material. The mineral material may comprise a ceramic. The electric device of the die may be embodied as capacitor, varistor or thermistor.
In an embodiment, a solder bump is applied as a protrusion on a frontside of the wafer for electrical interconnection. The solder bump is partially covered by the passivation layer. Alternatively, a thick film metallization is applied on the frontside for electrical interconnection, which can also be partially covered by the passivation layer. The non-covered portion of the protrusion serves as the electrical contact area for interconnection e.g. with an external circuit environment like a PCB or the like.
The frontside of the die may have two layers. A protective layer seals the frontside. By recesses in this protective layer the electrical contact points can be defined. Herein the word ‘point’ does not have its mathematical meaning. Rather it describes a small defined area.
A passivation layer all around the die is laminated onto the protective layer. The materials of the two layers may be different from each other. The passivation layer protects the die against potential environmental impacts including moisture, chemical contamination or physical damage in subsequent assembly steps.
In one embodiment the passivation layer may be electrically insulating. A passivation layer deposited by ALD may comprise any metal nitride or oxide. In particular the passivation layer may comprise one or more of Al2O3, AlN and TiO2. Al2O3 has high electric resistance and high thermal conductivity.
In the following, the invention will be explained in more detail with reference to accompanied drawings. The drawings show:
Similar or apparently identical elements in the figures are marked with the same reference signs. The figures and the proportions in the figures are not scalable.
Bond pads 104 are formed on the active surface connected to device structures. Said bond pads serve as electrical contact points between the wafer and any connected circuitry. Protrusions for electrical interconnections are applied on said bond pads.
The backside 105 of the wafer shown at the bottom part of the figure is free of circuitry. Thus the backside of the wafer may be designated as passive surface. The passive surface 106 may comprise the material of the wafer.
Alternatively, the opening may be filled with a thick film metallization 205 deposited by a conventional sputtering and subsequent electroplating process. Both the solder bump 204 and the thick film metallization 205 enable electrical interconnection between the semiconductor die 101 and the electrical device realized by device structures in or on the die and an external circuitry like a printed circuit board (PCB).
In step a) of an exemplary method a semiconductor wafer as shown in
When the tape 303 is attached to the backside 105 of the wafer 100, the wafer 100 is diced into single dies Dolby sawing dicing streets 302 from the frontside 103. The single dies 101 are only partially divided by the dicing step i), as shown in
In a third step ii) illustrated in
Next, the adhesive layer of the tape 303 on the backside 105 is detached from the wafer 100. The releasing can be executed by mechanical pressure, heating, UV exposure or a different method depending on the adhesive's properties.
In step iii) the wafer 100 is divided into singulated dies 101 by grinding since the continuous layer on the backside 401 is ground until it is completely removed as shown in
The described dicing before grinding (DBG) process allows better control of the dicing process, minimum backside chipping and minimum risk of die damage. The grinding tape 501 protects the active surface on the frontside 103 from damage during backside-grinding.
Once the wafer 100 is ground and the dies 101 are singulated, a specific delamination and lamination process is required to delaminate the grinding tape 501 (step iv) and to laminate a passivation tape 701 (step c) on the frontside 103 of the dies 101, as shown in
After the later electrical contact areas are covered by the tape 701, a passivation layer 801 is deposited by ALD as illustrated in
In contrast to other methods, in the described method no expansion of the tapes 501 or 701 in order to enlarge the distance between the lateral sides 602 of the dies 101 is required. Here, such a step is superfluous since passivation by an ALD process allows the deposition of single passivation layers in nanometer scale. By repeatedly applying such mono-layers, layer thicknessness up to μm scale can be achieved. Therefore, neither the small distances between facing lateral sides 602, which are equal to the width of the dicing streets 302, nor the small gaps between the frontside 103 of the die and the tape 701 do hinder uniform deposition of passivation.
Furthermore, an ALD process has the main advantages of being capable of depositing layers in a low temperature regime with a high uniformity and quality and being capable of covering high aspect ratio topographies with minimum variation of less than 1 nm. Only the ALD process allows a thin-film deposition of passivation layers based on metal nitrides or metal oxides like alumina since the required temperature in a CVD process would be higher than the decomposition temperature of most polymers. In contrast to CVD, ALD can be performed at low temperatures, i.e. around room temperature. CVD for passivation processes is performed at elevated temperatures above 150° C.
When the deposition of the passivation layer 801 is completed, the passivation tape 701 is detached from the dies 101 (step e). The releasing can be forced by heating, UV exposure or a different method depending on the adhesive's properties. A usual fatigue strength of the first adhesive layer 701B of the passivation tape 701 is about 6 to 8 N/mm2. When releasing the tape 701 from the dies 101, the passivation layer 801 that is also deposited to the bottom surface of the tape 701 delaminates at the upper edge between the protrusion and the tape 701, since the edge is a weak point of said layer.
For example, the passivation layer 801 delaminates at the upper edge of a thick film metallization 205 and the tape 701 or at the edge between a solder bump 204 and the tape 701. The exact borderline of the passivation layer 801 can be defined by the thickness of the adhesive layer 701B of the tape 701. A thick adhesive layer 701B covers a large area of the solder bump 204 or of the thick film metallization 205. Thus, on a large area of the solder bump 204 or of the thick film metallization 205 no passivation layer can be deposited. The borderline runs close to the surface of the die.
On the other hand, a thin adhesive layer 701B covers a comparatively smaller portion of the solder bump 204 or of the thick film metallization 205. Thus, the passivation layer 801 can be deposited on a larger portion of the solder bump 204 or of the thick film metallization 205. In such a way, the size of an electric contact area not covered by the passivation layer 801 can be defined. Hence, this size can be defined exactly.
The resulting dies 901 and 902 with passivation layer 801 are shown in
The passivation layer 801 may consist of a dielectric material such as alumina (Al2O3 ), which allows high electrical insulation. Other possible materials are AlN or a mixture of Al2O3 and TiO2. The exact composition of the passivation layer material depends on external influences, the required material qualities such as electrical resistance, thermal conductivity and temperature resistance and on material costs.
The passivation layer 801 protects the semiconductor die 101 against external influences such as moisture, chemical contamination or mechanical damages in the following process steps.
In one embodiment not shown in the figures the semiconductor die may be used for forming a micro-electro-mechanical system (MEMS) device for a variety of applications such as sensing, protection, power electronics, etc.
In another embodiment not shown in the figures the die may comprise a mineral material. The mineral material may comprise a ceramic. The electric device of the die may be embodied as capacitor, varistor or thermistor.
In another embodiment not shown in the figures the wafer may comprise a mineral material. The wafer may be divisible in singulated dies. The mineral material may comprise a ceramic. The electric devices of the dies may be embodied as capacitor, varistor or thermistor.
Although the invention has been illustrated and described in detail by means of the preferred embodiment examples, the present invention is not restricted by the disclosed examples and other variations may be derived by the skilled person without exceeding the scope of protection of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10 2020 102 003.1 | Jan 2020 | DE | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2021/050721 | 1/14/2021 | WO |
