Patent Application
20100203713
This invention relates to an electronic device including a thin film transistor (TFT) or the like and its manufacturing method and, further, relates to a display device (organic EL device, inorganic EL device, liquid crystal display device, or the like) using TFTs, a circuit board, and other electronic devices and their manufacturing method.
Generally, a display device such as a liquid crystal display device, an organic EL device, or an inorganic EL device has conductive patterns such as a wiring pattern and an electrode pattern formed and patterned on a substrate having a flat main surface. Further, various films, an electrode film, and so on necessary for elements that constitute the display device are also disposed on the substrate.
In recent years, there is a growing demand for making a size of such display device bigger. In order to form a large-size display device, it is necessary to form as many as display elements on a substrate with high accuracy and to electrically connect these elements to a wiring pattern. In this case, insulating films, TFTs (thin film transistors), light emitting elements, and so on are formed, in addition to the wiring pattern, on the substrate in a multilayered state. As a result, level differences are normally formed on the substrate in a stepwise fashion and the wiring pattern is arranged across these level differences.
When the wiring has level differences, it is necessary to increase the wiring width, but when the wiring width is increased, there arises a drawback that a driver load due to wiring parasitic capacitance becomes larger. Therefore, it has been desired to solve these level differences.
Further, when the size of the display device becomes bigger, the wiring pattern itself becomes longer and thus it is necessary to reduce the resistance of the wiring pattern. As techniques for solving the level differences of the wiring pattern and reducing the resistance thereof, Patent Document 1, Japanese Patent Application No. 2005-173050 (referred to as Related Document 1), and Patent Document 2 are proposed, wherein, in order to form wiring for a flat panel display device such as a liquid crystal display device, a wiring pattern is formed on a surface of a transparent substrate and a transparent insulating material having a height equal to that of the wiring pattern is formed in contact with the wiring pattern.
Among them, Patent Document 1 proposes to use an inkjet method or a screen printing method as a wiring forming method. Related Document 1 discloses a method of forming a conductive metal layer for a gate electrode or the like by electroless plating of Cu or the like, while Patent Document 2 discloses a method of more flattening the wiring by heat press or CMP.
Further, Japanese Patent Application No. 2006-313492 (hereinafter referred to as Related Document 2) discloses a TFT and a method of manufacturing it by forming an insulating layer provided with a trench on a substrate, providing a gate electrode in the trench using electroless plating so as to be substantially flush with a surface of the insulating layer, and providing a gate insulating film and a semiconductor layer on the gate electrode. In Patent Document 3, a gate electrode is formed by electroless plating of copper or the like and part of a gate insulating film is formed by spin-coating an insulating coating film. According to this structure, since the insulating coating film formed by spin coating can maintain its surface extremely flat, it is possible to obtain an electronic device such as a TFT excellent in flatness.
If the wiring is formed by the inkjet method or the screen method as in Patent Document 1, a surface of the wiring becomes rough so that the flatness of an insulating layer or the like formed on the wiring is degraded. On the other hand, if the electroless plating is used as in Related Documents 1 and 2, it is not possible to cope with the increase in size of the display device on a practical level. That is, when the size of a glass substrate is super-enlarged to about 3 m square, a plating apparatus (plating bath) large enough to electroless-plate the super-enlarged glass substrate becomes necessary. However, as a matter of fact, there is no such a large plating apparatus that can plate the super-enlarged glass substrate and, therefore, it is not possible to plate a super-large glass substrate by the use of a plating apparatus. Further, it is practically difficult to uniformly electroless-plate such a super-large area. Moreover, the electroless plating is difficult to control and thus there frequently arises a problem that a circular unplated region is formed in nickel plating on gold plating. Further, when a conductive pattern is formed by electroless plating, it is necessary to provide a layer underlying the plating layer for enhancing the adhesion.
Further, it is extremely difficult to uniformly flatten the wiring on a super-large glass substrate over a wide area using heat press or CMP as in Patent Document 2 and this is also difficult for practical use in terms of economy.
It is therefore a technical object of this invention to provide an electronic device having a conductive pattern uniformly formed on a super-large substrate and a method of manufacturing the electronic device.
It is another technical object of this invention to provide a display device that can be manufactured without using CMP or the like and thus is low-priced and large-sized.
It is still another technical object of this invention to provide a semiconductor device excellent in flatness with a small leakage current.
According to a first aspect of this invention, there is provided a method of manufacturing an electronic device having a substrate, a transparent resin film formed on the substrate, and a metal film selectively buried in the transparent resin film, characterized by comprising a step of forming an insulator coating film on the transparent resin film, a step of forming a trench selectively in the coating film and the transparent resin film, a step of forming a metal film on an entire surface including the inside of the trench and the top of said coating film by sputtering, and a step of lifting off the metal film on the top of said coating film by removing the coating film by etching, thereby obtaining a structure in which the metal film is buried in the trench.
According to a second aspect of this invention, there is provided a method of manufacturing an electronic device according to the first aspect, characterized in that the coating film is porous.
According to a third aspect of this invention, there is provided a method of manufacturing an electronic device according to the first or the second aspect, characterized in that the coating film comprises a porous coating film containing one kind or two or more kinds of oxides of Si, Ti, Al, and Zr.
According to a forth aspect of this invention, there is provided a method of manufacturing an electronic device according to the first aspect, characterized in that the coating film contains one kind or two or more kinds of compositions expressed by ((CH3)nSiO2-n/2)x(SiO2)1-x (where n=1 to 3 and x≦1).
According to a fifth aspect of this invention, there is provided a method of manufacturing an electronic device according to the first aspect, characterized in that the step of forming an insulator coating film comprises a step of forming a porous coating film and a step of forming a nonporous coating film on the porous coating film.
According to a sixth aspect of this invention, there is provided a method of manufacturing an electronic device according to any one of the first to the fifth aspects characterized in that the step of forming a trench selectively in the coating film and the transparent resin film comprises a step of providing a photosensitive resist film on the coating film, a step of removing the photosensitive resist film selectively by exposure and development to form a predetermined pattern, and a step of removing the coating film selectively by etching using the predetermined pattern of the photosensitive resist film as a mask.
According to a seventh aspect of this invention, there is provided a method of manufacturing an electronic device according to the sixth aspect, wherein characterized in that the step of forming a trench selectively in the coating film and the transparent resin film further comprises a step of removing the transparent resin film selectively by etching using as a mask at least one of the predetermined pattern of the photosensitive resist film and the remainder of the coating film selectively removed by etching.
According to an eighth aspect of this invention, there is provided a method of manufacturing an electronic device according to the sixth aspect, characterized in that the step of removing the coating film selectively by etching using the predetermined pattern of the photosensitive resist film as a mask comprises a dry etching process using a corrosive gas.
According to a ninth aspect of this invention, there is provided a method of manufacturing an electronic device according to the eighth aspect, characterized in that the step of forming a trench selectively in the coating film and the transparent resin film further comprises a step of removing the transparent resin selectively film by dry etching with the use of the corrosive gas using as a mask at least one of the predetermined pattern of the photosensitive resist film and the remainder of the coating film selectively removed by etching.
According to a tenth aspect of this invention, there is provided a method of manufacturing an electronic device according to the eighth or the ninth aspect, characterized in that the corrosive gas contains a CxFy gas.
According to a eleventh aspect of this invention, there is provided a method of manufacturing an electronic device according to the tenth aspect, characterized in that the corrosive gas contains a CF4 gas.
According to a twelfth aspect of this invention, there is provided a method of manufacturing an electronic device according to the tenth aspect, characterized in that the corrosive gas contains a C5F8 gas and an O2 gas.
According to a thirteenth aspect of this invention, there is provided a method of manufacturing an electronic device according to according to any one of the first to the twelfth aspects, characterized by further comprising a step of removing the metal film adhering to a side wall of the trench of the coating film after the step of forming the metal film and before removing the coating film by etching.
According to a fourteenth aspect of this invention, there is provided a method of manufacturing an electronic device according to any one of the first to the thirteenth aspects, characterized in that the step of lifting off the metal film on the coating film by removing the coating film by etching, thereby obtaining a structure in which the metal film is buried in the trench comprises a step of removing the coating film by etching using an etching solution containing hydrofluoric acid.
According to a fifteenth aspect of this invention, there is provided a method of manufacturing an electronic device according to any one of the first to the fourteenth aspects, characterized by comprising a step of forming the transparent resin film to a thickness of 1 to 2 μm on the substrate.
According to a sixteenth aspect of this invention, there is provided a method of manufacturing an electronic device according to any one of the first to the fifteenth aspects, characterized in that the step of forming an insulator coating film on the transparent resin film comprises a step of forming the insulator coating film to a thickness of 300 to 2,000 nm.
According to a seventeenth aspect of this invention, there is provided a method of manufacturing an electronic device according to the first aspect, characterized in that the step of forming an insulator coating film on the transparent resin film comprises a step of forming a porous coating film to a thickness of 700 to 1,600 nm and a step of forming a nonporous coating film to a thickness of 100 to 300 nm on the porous coating film.
According to an eighteenth aspect of this invention, there is provided a method of manufacturing an electronic device according to any one of the first to the seventeenth aspects, characterized by comprising a step of forming a semiconductor layer on the selectively buried metal film through an insulating layer therebetween.
According to this invention, there is obtained a super-large-area and low-priced wiring board or display device having a uniform conductor layer. Further, according to this invention, there are obtained a semiconductor device having a structure in which no level difference due to gate wiring is formed at a TFT channel gate portion, and a method of manufacturing the semiconductor device.
Hereinbelow, embodiments of this invention will be described.
The gate electrode 12 of
The illustrated TFT has an insulating coating film 141 uniformly formed on the transparent resin film 11 and the gate electrode 12 so as to lie over them. The insulating coating film 141 is formed by a coating film disclosed in Related Document 2. This insulating coating film 141 is formed by spin-coating a coating solution in the form of a mixture of a complex of polymethylsilsesquioxane and silica and a solvent and then drying it. The coating solution is a liquid in the spin-coated state described above and, therefore, in the state where the glass substrate 10 is maintained horizontal, a surface of the solution after the coating is also maintained horizontal. Further, even if a gap exists between the transparent resin film 11 and the gate electrode 12, the coating solution also flows into the gap and, as a result, the surface of the solution after the coating is maintained horizontal. Even if dried in this state, the insulating coating film (hereinafter, the insulating coating film and its composition may respectively be abbreviated as a SiCO film) 141 maintains high flatness and thus can also be called a flattening film. The insulating coating film 141 coated and dried has a surface roughness of 0.27 μm or less in average surface roughness Ra and a permittivity ∈r of to 5.0.
A dielectric film 142 such as a silicon nitride film is formed by CVD on the insulating coating film 141. As a result, the illustrated TFT has an insulating layer 14 including a gate insulating film formed by the insulating coating film 141 and the dielectric film 142.
Further, the illustrated TFT has a semiconductor layer 161 of amorphous silicon (a-Si) formed on the insulating layer 14, semiconductor layers 162 of n+a-Si formed on the semiconductor layer 161, and source and drain electrodes 17 and 18 of a metal formed on the semiconductor layers 162. The semiconductor layer 161 forms a channel region. Further, an insulating film 20 of silicon nitride (Si3N4) is formed on the source electrode 17, the drain electrode 18, and the channel region.
In this structure, since the gate electrode 12 is formed by sputtering, the gate electrode with good adhesion to the glass substrate 10 can be formed and, further, since aluminum over the transparent resin film 11 is removed by the lift-off (chemical lift-off) technique, the manufacturing cost can be significantly reduced as compared with removal using CMP.
Next, referring to
A magnetron sputtering apparatus 50 shown in
The plasma shielding member 66 forms a slit extending in an axial direction of the columnar rotary shaft 52 and opening the target 51 with respect to the substrate 60. In this case, the width and the length of the slit of the plasma shielding member 66 are set so that when the rotary magnet group 53 is rotated at a constant frequency, a region where the magnetic field strength is 75% or more of the maximum value in the time average distribution of magnetic field strengths of components parallel to a surface of the target 51 in a magnetic field formed on the surface of the target 51 is opened as seen from the substrate 60. Simultaneously, the width and the length of the slit are set so that a region of the substrate 60 where the film thickness to be formed per unit time is 80% or less of the maximum film thickness to be formed on the substrate 60 per unit time when end portions of the target 51 are not shielded is shielded by the plasma shielding member 66. A region not shielded by the plasma shielding member 56 is a region where the magnetic field strength is high and thus a plasma with a high density and a low electron temperature is generated so that there is no charge-up damage or ion irradiation damage to the substrate 60, and is simultaneously a region where the film forming rate is high. By shielding the region other than this region by the shielding member 66, it is possible to carry out film formation with no damage without substantially reducing the film forming rate.
On the other hand, a DC power supply, a RF power supply, and a matching device are connected to the feeder line 62. The plasma excitation power is supplied to the backing plate 56 and the target 51 from the DC power supply and the RF power supply through the matching device and further through the feeder line 62 and the housing so that a plasma is excited on the surface of the target. A plasma can be excited only by the DC power or the RF power, but in terms of the film quality controllability and the film forming rate controllability, it is preferable to apply both.
The frequency of the RF power is normally selected between several hundred kHz and several hundred MHz, but in terms of increasing the plasma density and reducing the plasma electron temperature, a high frequency is preferable. In this embodiment, it is set to 13.56 MHz. The plasma shielding member 66 also functions as a ground plate for the RF power. With this ground plate, even if the substrate 60 is in an electrically floating state, a plasma can be efficiently excited. The paramagnetic member 65 has an effect of magnetic shielding of a magnetic field generated by the magnets and an effect of reducing a change in magnetic field due to disturbance near the target. Further, a non-illustrated vertically movable mechanism driven by a motor is provided in a region inside a dotted line 71.
By setting an aluminum target as the target 51 of the illustrated magnetron sputtering apparatus 50 and setting as the substrate 60 the glass substrate 10 having the transparent resin film 11 selectively formed with the trench as shown in
Next, processes up to forming the insulating coating film 141 and the dielectric film 142 to form the insulating layer 14 after forming the transparent resin film 11 on the glass substrate 10 as shown in
First, as shown in
Then, as shown in
Then, as shown in
The glass substrate 10 formed with the trench 12a is introduced into the magnetron sputtering apparatus shown in
The glass substrate 10 formed with the aluminum film 12 is removed from the magnetron sputtering apparatus 50 and introduced into an apparatus for chemical lift-off. In the chemical lift-off, the insulating coating film 14a is etched with a SiO2-based selective etching solution (containing hydrofluoric acid) and simultaneously the aluminum film 12 on the insulating coating film 14a is removed by lift-off. As a result, as shown in
Then, as shown in
In the above-mentioned example, the ordinary photoresist is provided on the insulating coating film 14a and, using it as a mask, the insulating coating film 14a and the transparent resin film 11 are etched by dry etching for patterning. However, the insulating coating film 14a may be photosensitive and, after patterning the insulating coating film 14a itself by mask exposure, the transparent resin film 11 may be patterned using the patterned insulating coating film 14a as a mask.
This invention is not limited to these techniques. For example, an ordinary photoresist is provided on the insulating coating film 14a and, using it as a mask, the insulating coating film 14a may be wet-etched with an etching solution, and then, using the etched insulating coating film 14a as a mask, the transparent resin film 11 may be wet-etched for patterning.
As described above, the trench 12a shown in
The lift-off process described with reference to
Next, referring to
On the insulating coating film 14b, the aluminum film 12 was formed using the magnetron sputtering apparatus shown in
Subsequently, as shown in
Then, in order to increase the etching rate, the composition expressed by ((CH3)nSiO2-n/2)x(SiO2)1-x (where n=1 to 3 and x≦1) of the insulating coating film was improved. In this case, the insulating coating film containing the composition expressed by ((CH3)nSiO2-n/2)x(SiO2)1-x (where n=1 to 3 and x≦1) was changed to a porous-type coating film. That is, the insulating coating film was changed to a porous coating film containing one kind or two or more kinds of oxides of Si, Ti, Al, and Zr (hereinafter referred to simply as porous-type). As a result of comparison, it was found that the etching rate of the porous-type SiCO film was 0.5 μm/sec and thus was seven times that of the nonporous SiCO film.
Referring to
Next, in the structure shown in
First, as shown in
Then, as shown in
Then, as shown in
Then, as shown in
The glass substrate 10 of
Then, as shown in
Then, as shown in
As described above, according to this invention, since the lift-off process is used, it is possible to manufacture a Flat-TFT having a gate electrode with no level difference. Therefore, according to this invention, a thorough reduction in off-leakage current can be achieved, the mobility of a channel can be improved, and further, since the thickness of a gate wiring film can be increased, the wiring width can be reduced so that it is possible to achieve a reduction in driver load by a reduction in wiring parasitic capacitance.
Further, according to this invention, it is possible to suppress variation in threshold voltage of TFTs and to obtain a low power consumption TFT. Further, according to this invention, it is also possible to obtain a TFT with high current driving capability and thus to realize an increase in panel size and image quality of a display device.
As described above, a thin film electronic device and its manufacturing method of this invention can be applied to an organic EL element, an inorganic EL element, a liquid crystal display, and the like and the manufacture thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-234974 | Sep 2007 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2008/066080 | 9/5/2008 | WO | 00 | 3/10/2010 |
