BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic cross-sectional view showing one example of a structure of a memory cell section of a DRAM.
FIG. 2 is a schematic plan view showing one example of the alignment mark pattern.
FIG. 3 is a schematic cross-sectional view for explaining problems of the conventional alignment mark.
FIGS. 4A to 4G are schematic cross-sectional views for explaining the steps for a method of manufacturing an alignment mark in the present inventions.
FIG. 5 is a set of diagrams showing the detection light contrasts for explaining the effects of the alignment mark in the present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
An example of the present invention is described in details below, referring to FIGS. 4A to 4G and FIG. 5. FIGS. 4A to 4G show cross-sectional structures of a memory cell section illustrated in FIG. 1 and the alignment mask section formed in a region other than the element formation region in contrast with each other. Further, while the alignment mark employed in the alignment mark section hereat had the same pattern as shown in FIG. 2, it is, for convenience, presented as a single bar in FIG. 4.
EXAMPLE
Firstly, as shown in the memory cell section of FIG. 4A, an element isolation region 2 was formed by a well-known method in prescribed region of a surface of a semiconductor substrate 1 which was made of p-type single-crystal silicon, and then a gate insulating film 3 with a thickness of 4 nm was formed by a thermal oxidation method on the surface of the semiconductor substrate. After that, a first silicon film 4 was grown by a well-known CVD (Chemical Vapor Deposition) method with monosilane (SiH4) being used as a source gas. The thickness of the first silicon film 4 was set to be 70 nm. Next, a metal film 5 was grown to a thickness of 90 nm by a well-known sputtering method, and, further, a silicon nitride film 6 were grown to a thickness of 120 nm by a well-known plasma CVD method with monosilane and ammonia (NH4) being used as source gases, and a silicon oxide film 7 were grown to a thickness of 80 nm by a well-known plasma CVD method with monosilane and dinitrogen monoxide (N2O) being used as source gases. Next, by means of lithography and dry etching, the silicon oxide film 7, the silicon nitride film 6, the metal film 5 and the first silicon film 4 were worked upon. Further, a silicon nitride film was grown to a thickness of 30 nm over the entire surface, and applying an etch back thereto, a sidewall insulating film 8 consisting of a silicon nitride film was formed and thereby a word line was formed. Though not shown in the drawings, a dopant diffusion layer such as a source and a drain may be formed, by the ion implantation method, on the surface of the semiconductor substrate either before or after the formation of the sidewall insulating film 8.
After forming the word line, a second silicon film 13a was grown to a thickness of 80 nm over the entire surface, and then a silicon oxide film 24 was grown to a thickness of 120 nm. At this stage, in the alignment mark section, layers of the gate insulating film 3, the first silicon film 4, the metal film 5, the silicon nitride film 6, the silicon oxide film 7, the second silicon film 13a and the silicon oxide film 24 were lying, in this order, on the semiconductor substrate 1.
Next, as shown in the memory cell section of FIG. 4B, the silicon oxide film 24 and the second silicon film 13a were worked upon by means of lithography and dry etching to form contact plugs 12 and 13. In order to form the contact plugs 12 and 13, the silicon oxide film 24 was first etched, using a photoresist pattern formed by lithography as a mask, and then the second silicon film 13a was etched, using this silicon oxide film 24 as a mask, a gas plasma of trifluoromethane (CHF3) was used for the etching of the silicon oxide film 24, and a gas plasma of hydrogen bromide (HBr) was used for the etching of the second silicon film 13a. At this stage, in the alignment mark section, an alignment mark layer 13b consisting of the second silicon film was formed.
Next, as shown in FIG. 4C, an interlayer insulating film 14 consisting of a silicon oxide film deposited by a HDP (High Density Plasma) method was formed over the entire surface, and then the planarization by the CMP method was applied to its surface. The thickness of the interlayer insulating film 14 was set to be 500 nm. Further, the interlayer insulating film can consist of a layered film comprising the silicon oxide film grown by the HDP method and a silicon oxide film grown by a plasma CVD method.
Next, as shown in FIG. 4D, the interlayer insulating film 14 was worked upon by means of lithography and dry etching to form a bit line contact hole 25 in the memory cell section and to form a mark hole 102 in the alignment mark section. As mentioned previously, the alignment mark layer 13b was, at this stage, covered only with the interlayer insulating film 14 that is transmissive to the visible light, so that the alignment mark layer 13b could be used as an alignment mark for forming the bit line contact hole 27.
Further, the mark hole 102 was formed by dry etching, using a gas plasma containing octafluorocyclopentane (C5F8), trifluoromethane, oxygen and argon. Since the gas plasma allows selective etching of a silicon oxide film over a silicon film, it was possible to leave the alignment mark layer 13b, even if the interlayer insulating film 14 was etched to expose the alignment mark layer 13b on the bottom of the mark hole 102 in the alignment mark section. Further, in the present invention, since the structure was such that the insulating film consisting of the silicon oxide film 7 and the silicon nitride film 6 lay immediately under the alignment mark layer 13b, the lower layers of the silicon oxide film 7 and the silicon nitride film 6 could be etched in the manner of self-alignment, using the alignment mark layer 13b as a mask during the formation of the mark hole 102. Moreover, since a metal film made of tungsten or the like could be hardly etched with the foregoing gas plasma, the etching automatically stopped when the metal film 5 was exposed. Accordingly, inside the mark hole 102, an alignment mark consisting of a multi-layered film comprising the silicon nitride film, the silicon oxide film and the alignment mark layer 13b was formed, which had a stepped part with an increased difference.
Next, as shown in FIG. 4E, a titanium nitride film 15 and a tungsten film 16 were successively grown to a thickness of 25 nm and 200 nm, respectively, so as to fill up the bit line contact hole 25 in the memory cell section. The titanium nitride film was formed by the CVD method with titanium tetrachloride (TiCl4) and ammonia being used as source gases, and besides, prior to the formation of the titanium nitride film, a titanium silicide had been deposited on the surface of the contact plug 13 (not shown in the drawings) by depositing titanium with titanium tetrachloride being used as a sole source gas, at an initial stage for formation of layer. Further, since the mark hole 102 in the alignment mark section occupied a large area, the mark hole could not be filled up with the tungsten film with such a thickness as mentioned above and thereby the titanium nitride film 15 and the tungsten film 16 were formed inside and outside the mark hole 102, accordingly. In this case, a stepped part of the alignment mark was maintained.
Next, as shown in FIG. 4F, portions of the tungsten film 16 and the titanium nitride film 15 lying on the interlayer insulating film 14 were removed by the CMP by the CMP method to form a bit line contact plug in the memory cell section.
Next, as shown in FIG. 4G, a metal film 17a made of tungsten was grown to a thickness of 70 nm over the entire surface and the metal film 17a was etched by mean of lithography and dry etching to form a bit line 17.
In the present example, when the metal film 17a is formed over the entire surface, the alignment mark in the alignment mark section is covered with the titanium nitride film 15, the tungsten film 16 and the metal film 17a, all of which is opaque to the visible light, so that the presence of the alignment mark layer 13b can not be detected from above. Nevertheless, since the alignment mark is constituted with the stepped part created by the multi-layered film comprising the silicon nitride film 6, the silicon oxide film 7 and the alignment mark layer 13b, the stepped part 26 can be maintained when the metal film 17a was formed thereon, and thereby the alignment of a photoresist pattern in lithography can be made by using the contrast of the detection light induced by the stepped part 26. That is to say, by forming a photoresist with an anti-reflection coating film after depositing the metal film 17a, and detecting the contrast of the detection light induced by the stepped part 26 of the foregoing alignment mark, a bit line pattern from the photoresist can be formed with an alignment of the position with the lower contact plug 13. Because the bit line contact plug was aligned with the contact plug 13, the bit line pattern was formed with an alignment with the bit line contact plug as a result.
FIG. 5 shows a set of schematic contrasts of a detection light for detecting an alignment mark when the alignment mark of the present invention formed by the manufacturing method of the present example is used and when the alignment mark formed by the conventional method shown in FIG. 3 is used. In the case of the alignment mark formed by the conventional method, the contrast 105 of the detection light is more or less flat to hardly distinguish the position of the alignment mark. Compared with this, in the case of the alignment mark of the present invention, the clear contrasts 103 and 104 of the detection light corresponding to the alignment mark 101 are obtained to be able to align the position accurately.
Patent Application
20070275520
