Patent Application
20240128171
This application claims priority under 35 USC 119(a) of Korean Patent Application No. 10-2022-0130414 filed on Oct. 12, 2022 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated by reference herein for all purposes.
The present disclosure relates to a method of manufacturing a semiconductor package, and a semiconductor package.
In general, a semiconductor chip may be implemented as a semiconductor package such as a wafer level package (WLP) or a panel level package (PLP), and the semiconductor package may be used as an electronic component of a device.
A process of manufacturing a semiconductor package may be accompanied by a plurality of equipment (e.g., equipment for disposing semiconductor chips, equipment for forming a redistribution layer, and equipment for forming bumps/UBMs). Accordingly, semiconductor packages being manufactured may be accompanied by movement between the equipment. A carrier may be used to move the semiconductor packages between the equipment.
It is an aspect to provide a method of manufacturing a semiconductor package, and a semiconductor package, in which a carrier may be implemented to be robust to external structures (e.g., adjacent equipment) and to physical conditions.
According to an aspect of one or more example embodiments, a method of manufacturing a semiconductor package comprises applying a cutter to a boundary between a main portion of a second metal layer and an edge portion of the second metal layer that surrounds the main portion, the second metal layer being on an upper surface of a first metal layer disposed on an upper surface of a carrier substrate; peeling the edge portion of the second metal layer from the first metal layer; forming a cover insulating layer on an upper surface of the main portion of the second metal layer; and disposing a semiconductor chip on an upper surface of the cover insulating layer.
According to another aspect of one or more example embodiments, a method of manufacturing a semiconductor package comprises exposing a portion of a first metal layer by removing an edge portion of a second metal layer that surrounds a main portion of the second metal layer, the second metal layer being on an upper surface of the first metal layer disposed on an upper surface of a carrier substrate; forming a cover insulating layer on an upper surface of the main portion of the second metal layer; and disposing a semiconductor chip on an upper surface of the cover insulating layer, wherein a thickness of the second metal layer is greater than 1 μm and less than 10 μm.
According to yet another aspect of one or more example embodiments, a semiconductor package comprising a semiconductor chip electrically connected to a redistribution layer; and a cover insulating layer disposed on a first surface of the semiconductor chip opposite to a second surface of the semiconductor chip that faces the redistribution layer, wherein the cover insulating layer does not provide an electrical connection path between a facing surface of the cover insulating layer that faces the semiconductor chip and an opposite surface of the cover insulating layer that is opposite to the facing surface, the opposite surface of the cover insulating layer has a protruding structure that surrounds the semiconductor chip from a viewpoint facing the semiconductor chip, and a protruding length of the protruding structure is greater than 1 μm and less than 10 μm.
The above and other aspects will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which:
The detailed description refers to the accompanying drawings which, by way of example, illustrate specific embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable one skilled in the art to practice the embodiments. It should be understood that the various embodiments are different from each other but are not necessarily mutually exclusive. For example, one embodiment of specific shapes, structures, and characteristics described herein may be implemented in another embodiment without departing from the spirit and scope of the present disclosure. Additionally, it should be understood that the location or arrangement of individual components within each disclosed embodiment may be changed without departing from the spirit and scope of the present disclosure. Accordingly, the detailed description set forth below is not intended to be taken in a limiting sense, and the scope of the present disclosure is limited only by the appended claims, with all equivalents as claimed by those claims. Like reference numbers in the drawings indicate the same or similar function throughout the various aspects.
A semiconductor package may include a redistribution layer for electrically connecting a semiconductor chip to a device or a printed circuit board. The redistribution layer may have a structure in which redistributions implemented finer than wirings of a wiring layer of a general printed circuit board are extended horizontally.
The redistribution layer may be electrically connected to bumps to vertically extend the electrical connection path, and Under Bump Metallurgy (UBM) may improve electrical connection efficiency between the redistribution layer and bumps.
As described above, a process of manufacturing a semiconductor package may be accompanied by a plurality of equipment (e.g., equipment for disposing semiconductor chips, equipment for forming a redistribution layer, and equipment for forming bumps/UBMs). Accordingly, semiconductor packages being manufactured may be accompanied by movement between equipment. A carrier may be used to move the semiconductor packages between the equipment, and the carrier may be disposed on the upper or lower surface of the semiconductor package being manufactured.
Hereinafter, various embodiments will be described in detail with reference to the accompanying drawings such that those skilled in the art may easily practice the present disclosure.
Referring to
Accordingly, even if an external structure (e.g., adjacent equipment) contacts the side surface of the carrier 10a-3, the external structure may not contact the side surface of the second metal layer 13. That is, the external structure may be prevented from contacting the side surface of the second metal layer 13 due to the excluded portion 13p. Therefore, the adhesiveness between the first metal layer 12 and the second metal layer 13 may be stably maintained, and the carrier 10a-3 may be implemented to be robust to physical conditions and/or to external structures (e.g., adjacent equipment).
Since the carrier substrate 11 may be excluded from the finished semiconductor package, the first metal layer 12 and the second metal layer 13 may be bonded to each other such that the carrier substrate 11 may be easily removed. For example, an organic release layer about 20 nm thick may be disposed between the first and second metal layers 12 and 13 as an adhesive between the first and second metal layers 12 and 13. For example, each of the first and second metal layers 12 and 13 may be a single metal layer containing copper.
Therefore, when the main portion 13a and the edge portion 13p of the second metal layer 13 are separated from each other by the cutter CUT, the edge portion 13p may be excluded from the carrier 10a-3 without photolithography. In detail, the peeling operation (10a-2) may include detaching the edge portion 13p of the second metal layer in a method different from the photolithography method.
For example, in some embodiments, the peeling operation (10a-2) may include pulling the edge portion 13p of the second metal layer from the first metal layer 12. In some embodiments, the peeling operation (10a-2) may include pulling the edge portion 13p of the second metal layer from the first metal layer 12 in a direction (e.g., a horizontal direction and/or an upward direction) different from a direction facing the first metal layer 12 (e.g., a downward direction). In some embodiments, the peeling operation (10a-2) may include pulling the edge portion 13p of the second metal layer from the first metal layer 12 by applying a force to the edge portion 13p of the second metal layer. For example, in some embodiments, one of the equipment for performing the semiconductor package manufacturing method may include a structure attached to the edge portion 13p of the second metal layer, such as a jig, and the structure may receive an upwardly moving force from one of the devices while attached to the edge portion 13p of the second metal layer. In some embodiments, the structure may collide with or apply stress to the side of the edge portion 13p of the second metal layer. Accordingly, the edge portion 13p of the second metal layer may be peeled off without photolithography.
In some embodiments, the cutter (CUT) may be a laser. For example, the operation 10a-1 of applying the cutter (CUT) may include irradiating the laser onto the boundary between the main portion 13a and the edge portion 13p. The laser irradiation time may be set to a time adjusted such that the first metal layer 12 is not divided into a plurality of parts by the cutter (CUT). In other words, in some embodiments, only the second metal layer 13 may be cut and not the first metal layer.
For example, the carrier 10a-3 may be a Detachable Copper Foil (DCF) carrier. In this case, the carrier substrate 11 may contain prepreg. The DCF carrier may be advantageous in reducing the possibility of warpage of a semiconductor package being manufactured. Reducing the possibility of distortion of the semiconductor package may be more important when the horizontal size of the semiconductor package is relatively larger, such as a fan-out panel level package (FO-PLP).
Referring to
An upper surface of the cover insulating layer 14 may be an upper surface on which a semiconductor chip of a semiconductor package is disposed or a redistribution layer is disposed. Thus, in some embodiments, the cover insulating layer 14 may be a passivation layer. For example, the cover insulating layer 14 may contain an insulating material such as prepreg, and a specific composition of the cover insulating layer 14 and a specific composition of the carrier substrate 11 may be different from each other. For example, in some embodiments, the specific composition may be determined by an inorganic filler that may be mixed with an insulating material.
The cover insulating layer 14 may include a main portion 14a and a protruding structure 14b that surrounds the main portion 14a. A thickness T1+T3 of the protruding structure 14b may be greater than a thickness T3 of the main portion 14a.
The insulating material contained in the cover insulating layer 14 may be placed on the upper surface 14as of the main portion 13a of the second metal layer and a portion 14bs of the upper surface of the first metal layer 12 in a state of being slightly fluid. A portion of the insulating material may move from the upper surface 14as to a portion 14bs of the upper surface. Therefore, in some embodiments, a density of the insulating material contained in the protruding structure 14b may be slightly lower than a density of the insulating material contained in the main portion 14a.
If the difference in density between the main portion 14a and the protruding structure 14b is too large, the protruding structure 14b may include micro-voids, and the micro-voids may limit the planarization performance of the cover insulating layer 14. For example, the microvoids may be distributed close to edges of a stepped structure formed by the upper surface 14as of the main portion 13a of the second metal layer, a side surface 14ss of the main portion 13a, and the portion 14bs of the upper surface of the first metal layer 12. If the edge portion of the first metal layer 12 is also excluded, the thickness difference between the thickness T1+T2+T3 of the protrusion structure 14b and the thickness T3 of the main portion 14a may become too large. If the thickness difference is too large, the density difference between the main portion 14a and the protruding structure 14b may become larger, and the thickness T3 of the main portion 14a of the cover insulating layer 14 required to secure the planarization performance of the cover insulating layer 14 may be thicker or an additional cover insulating layer may be required.
By contrast, the method of manufacturing a semiconductor package and a semiconductor package according to some example embodiments are implemented such that a thickness difference between the thickness T1+T3 of the protruding structure 14b and the thickness T3 of the main portion 14a is less than 10 IIM. As the planarization performance of the cover insulating layer 14 may be efficiently secured, the thickness T3 of the main portion 14a of the cover insulating layer 14 may be effectively reduced. In addition, since the thickness difference exceeds 1 μm, physical robustness to the external structure (e.g., adjacent equipment) of the carrier 10a-4 may be secured.
Since the edge portion of the first metal layer 12 is not excluded, a thickness difference between the thickness T1+T3 of the protruding structure 14b and the thickness T3 of the main portion 14a may be substantially equal to the thickness T1 of the second metal layer 13. Accordingly, the thickness T1 of the second metal layer 13 may be greater than 1 μm and less than 10 μm.
The thickness T2 of the first metal layer 12 may be thicker than the thickness T1 of the second metal layer 13. For example, the thickness T2 may be about 18 μm. The fact that the thickness T2 of the first metal layer 12 is relatively thick may mean that the thickness T3 required to secure the planarization performance of the cover insulating layer 14 may vary relatively greatly depending on whether or not the edge portion of the first metal layer 12 is excluded.
For example, the thicknesses T1, T2, and T3 may be measured by analysis using at least one of a micrometer, transmission electron microscopy (TEM), atomic force microscope (AFM), scanning electron microscope (SEM), focused ion beam (FIB) optical microscope, and surface profiler, and may be defined as the average value of the sum of vertical thicknesses for each horizontal position of the corresponding layer.
Referring to
Accordingly, the edge portion 13p of the second metal layer may have a shape surrounding each of the main portions 13a. The number of main portions 13a is not particularly limited.
Referring to
For example, the semiconductor chip 221′ may include a body portion containing a semiconductor material such as silicon (Si), germanium (Ge), or gallium arsenide (GaAs), and an element layer or an active layer disposed below the body and including an integrated circuit (IC). The semiconductor chip 221′ may include a logic semiconductor chip and/or a memory semiconductor chip. The logic semiconductor chip may be a micro-processor, and may be a Central Processing Unit (CPU), Graphic Processing Unit (GPU), Field Programmable Gate Array (FPGA), Application Processor (AP), Digital Signal Processor, Cryptographic Processor, a controller, or an application specific integrated circuit (ASIC). The memory semiconductor chip may be a volatile memory such as dynamic random access memory (DRAM) or static random access memory (SRAM) or a non-volatile memory such as flash memory.
The width W3 of each of the main portions 13a of the second metal layer may be smaller than the width W2 of the first metal layer 12 and may be wider than the width W1 of the semiconductor chip 221′. Accordingly, since the horizontal size of the finished semiconductor package may be greater than the horizontal size of the semiconductor chip 221′, the finished semiconductor package may be a fan-out package, but embodiments are not limited thereto.
The top surface of the semiconductor chip 221′ may provide an electrical connection path between the semiconductor chip 221′ and the redistribution layer (211 in
For example, the operation 10b+221 of arranging the semiconductor chip 221′ may include disposing the semiconductor chip 221′ such that the number of cover insulating layers 14 is one between the main portion 13a of the second metal layer and the semiconductor chip 221′. That is, in some embodiments, a single cover insulating layer 14 may be between the main portion 13a of the second metal layer and the semiconductor chip 221′. Since the thickness of the main portion 13a of the second metal layer is greater than 1 μm and less than 10 μm, the thickness requirement required to secure the planarization performance of the cover insulating layer 14 may be satisfied even if the number of cover insulating layers 14 is one.
For example, according to the chip first method, the operation 10b+221 of arranging the semiconductor chip 221′ may include disposing the semiconductor chip 221′ such that in the semiconductor chip 221′, the opposite surface (e.g., lower surface) of the surface (e.g., upper surface) electrically connected to the redistribution layer (211 in
Referring to
Referring to
In some embodiments, the interlayer insulating layers 212 may include an insulating material, and for example, may include a thermosetting resin such as epoxy resin or a thermoplastic resin such as polyimide may be included. For example, in some embodiments, the interlayer insulating layers 212 may include a photosensitive insulating material such as a Photo Imageable Dielectric (PID) resin. In some embodiments, the interlayer insulating layers 212 may include a resin mixed with an inorganic filler, for example, Ajinomoto Build-up Film (ABF). In some embodiments, the interlayer insulating layers 212 may include prepreg, flame retardant (FR-4), or bismaleimide triazine (BT). In some embodiments, the interlayer insulating layers 212 may include the same or different materials, and the boundary therebetween may not be distinguished depending on the material and process forming each layer.
The redistribution layers 211 and the interlayer vias 213 may form an electrical path. The redistribution layers 211 may be arranged in a line shape on the x-y plane, and the interlayer vias 213 may have a cylindrical shape with side surfaces that are inclined toward the bottom or top and become narrow in width. The interlayer vias 213 are illustrated as a filled via structure in which the inside is completely filled with a conductive material, but is not limited thereto. For example, the interlayer vias 213 may have a conformal via shape in which a metal material is formed along an inner wall of the via hole. The redistribution layers 211 and the interlayer vias 213 may include a conductive material, for example, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof.
Referring to
Referring to
The non-conductive film layers 231′,232′, and 233′ may be disposed between the redistribution structure 210′ and the semiconductor chips 221′,222′, and 223′ to surround the bumps 235′. The non-conductive film layers 231′,232′, and 233′ may be referred to as underfill layers, and may contain a non-conductive polymer. For example, in some embodiments, the non-conductive film layers 231′,232′, and 233′ may contain and may contain a non-conductive paste (NCP).
Referring to
According to some embodiments, some of the semiconductor chips 222′ and 223′ may be omitted, and the encapsulant 240′ may fill a space occupied by some of the semiconductor chips 222′ and 223′. In some embodiments, the core member 260′ illustrated in
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
The bumps 250′ are electrically connected to the redistribution layers 211 and may be arranged on one surface (e.g., the lower surface) of the redistribution structure 210′. For example, the bumps 250′ may have a ball or column shape, and may include a solder containing tin (Sn) or an alloy (Sn—Ag—Cu) containing tin (Sn). The bumps 250′ may have a relatively low melting point compared to other metal materials, and may thus be connected and fixed on the UBM 214 by a thermal compression bonding (TCB) process or a reflow process.
Under Bump Metallurgy (UBM) 214 may be electrically connected between the interlayer vias 213 and the bumps 250′, and the bumps 250′ may be arranged to face each other in a stacking direction (e.g., a vertical direction) of the redistribution structure 210′. For example, the UBMs 214 may provide a sufficiently wide bottom surface such that some of the material of the bumps 250′ does not leak sideways when the bumps 250′ are formed. The bumps 250′ may contact the wide lower surfaces of the UBMs 214. Accordingly, the UBMs 214 may be advantageous in reducing contact resistance between the bumps 250′ and the redistribution layers 211.
Referring to
Referring to
The cover insulating layer 14 may not provide an electrical connection path between a surface facing the semiconductor chip 221′ (e.g., lower surface) and an opposite surface (e.g., upper surface) of the cover insulating layer 14. Therefore, the role of the cover insulating layer 14 (e.g., planarization, provision of the surface of a semiconductor package) may be different from the role of the interlayer insulating layer 212 (e.g., provision of insulation between redistribution layers and arrangement space for redistribution layers).
The cover insulating layer 14 may include a main portion 14a disposed on the upper surface of the semiconductor chip 221′ and a protruding structure 14b surrounding the main portion 14a. The protruding structure 14b may protrude from a surface (e.g., an upper surface) opposite to a surface (e.g., a lower surface) facing the semiconductor chip 221′ in the cover insulating layer 14, and may be positioned so as to surround the semiconductor chip 221′ from a viewpoint facing the semiconductor chip 221′ (e.g., in a vertical direction). The protruding length of the protruding structure 14b may be greater than 1 μm and less than 10 μM.
Accordingly, the thickness of the main portion 14a of the cover insulating layer 14 may be reduced, and the number of cover insulating layers 14 may be one between the surface facing the semiconductor chip 221′ (e.g., lower surface) and the opposite surface (e.g., upper surface) of the cover insulating layer 14. That is, a single cover insulating layer 14 may be between the surface facing the semiconductor chip 221′ (e.g., lower surface) and the opposite surface (e.g., upper surface) of the cover insulating layer 14.
Since the cover insulating layer 14 may provide surfaces of the semiconductor packages 200a and 200b and may protect the semiconductor packages 200a and 200b from external impact, and the protruding structure 14b may be exposed to air in a protruding direction (e.g., upper surface).
Referring to
Referring to
For example, since a core insulation layer 262′ of the core member 260′ may have greater thickness and/or rigidity than one of interlayer insulating layers 212, the core insulation layer 262′ may reduce a possibility of warpage of the redistribution structure 210. For example, the core insulation layer 262′ may be similar to a core disposed in a center of a printed circuit board, and the core member 260′ may have a structure resulting from a PLP structure, but is not limited thereto. Since the core member 260′ surrounding the semiconductor chip 221′ may be disposed to overlap the redistribution structure 210 in a vertical direction, the semiconductor packages 200b and 200c may have a FO-PLP structure.
Referring to
Referring to
As set forth above, a method of manufacturing a semiconductor package and a semiconductor package according to some example embodiments may improve efficiency related to a carrier implemented to be robust against physical conditions with respect to an external structure (e.g., adjacent equipment).
While example embodiments have been illustrated and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present disclosure as defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0130414 | Oct 2022 | KR | national |
