Patent Application
20180122652
This application relates generally to the preparation of lamellae for transmission electron microscopy to analyze semiconductor defects, and more particularly to a method of region-of-interest (ROI) encapsulation during axis conversion of cross-sectional lamellae.
Integrated circuits (ICs) are typically designed using software tools in which designers can combine known components to produce a model for an actual IC. The software can also predict the operation of the modeled device, and the designer can make corrections based on the simulated operation of the modeled circuitry. However, when the IC design is sent to the foundry that produces the actual prototype IC, unexpected defects may occur due to increasingly complicated processing techniques. Such defects are exacerbated as transistor dimensions decrease and advanced processing techniques are utilized. For example, the use of resolution enhancement techniques such as optical proximity correction, phase shift masks, and double patterning lead to variations in lithography that are difficult to accurately model during the design process. Variations in chemical mechanical planarization due to surface density effects and other issues can also contribute to this problem.
When such defects are detected, the circuit designer may send the defective IC to a failure analysis team to identify the defect so that the design may be corrected. Some defects can be observed using non-destructive techniques, e.g., electro-optical techniques such as LVP (Laser Voltage Probing), SDL (Soft Defect Localization), and LADA (Laser Assisted Device Alteration), among others. However, some defects require destructive failure analysis methods in which the IC is milled down to a thin film in order to find the region-of-interest (ROI) for fault detection. One such technique is transmission electron microscopy (TEM), which is commonly used for fault analysis for the latest process nodes (e.g., 7 nm to 20 nm).
To employ TEM, the IC being analyzed is milled into thin samples denoted as “lamellae” (plural). A resulting lamella is then subjected to relatively intense electron bombardment (e.g., in a range of 30 kV to 300 kV). The electrons are imaged after passing through the lamella (hence the use of “transmission” in Transmission Electron Microscopy). The relatively large amounts of power used to excite the electrons in TEM causes the electrons to have short wavelengths. As a result, TEM has much finer resolution than other electron-based microscopy techniques, such as scanning electron microscopy (SEM). The resolution for TEM can thus extend down to the atomic scale, which is very useful for isolating faults in modern process nodes.
Although TEM provides robust resolution, the milling of the lamellae becomes problematic at advanced process nodes. In particular, modern process nodes have moved from the traditional planar transistor architectures to three-dimensional structures such as in a fin-shaped field effect transistor (FinFET). FinFETs differ from planar CMOS (Complementary Metal Oxide Semiconductor) devices in that in a CMOS transistor, a gate controls a channel through only one plane. In such planar processes, the gate may not have good control of the channel, exhibiting leakage currents between the source and drain even when the gate is off. In contrast, the channel in a FinFET is contained within a thin vertical fin with the gate deposited on the two sides and top of the fin so that the channel is controlled from 3 different planes.
Given the three-dimensional structure of a FinFET, the lamella orientation can be either aligned with a longitudinal axis of the gate to form an “y-directed” lamella or aligned with a longitudinal axis of the fin to form an “x-directed lamella.” For example, suppose a FinFET having three fins is determined to be faulty. To isolate the fault, an initial y-directed lamella may be used so that the cross-sectional view of the fins can point to the faulty one. The nature of the fault would then be better determined by converting the y-directed lamella into an x-directed lamella of the faulty fin. But such conversion is hampered in that the initial y-directed lamella is typically quite thin (e.g., less than 40 nm). Although a more robust thickness would be desirable to ease the formation of the x-directed lamella, the presence of the source and drain contacts would compromise the analysis such that the initial y-directed lamella must be relatively thin.
The relatively-thin y-directed lamella would then have structural integrity issues if it were converted into an x-directed lamella without any further modification. It is thus conventional to bolster the y-directed lamella with a electron-beam deposition of a metal such as tungsten (W) prior to the axis conversion of the lamella. But the resulting lamella is then subject to warping due to the residual stress of the tungsten deposition, particularly since the deposition must occur sequentially on each side of the lamella. This warpage prevents the proper formation of the desired x-directed lamella.
Accordingly, there is a need in the art for improved axis conversion techniques for lamellas for TEM-based fault analysis of semiconductor structures.
An advantageous axis conversion for semiconductor lamellae used in TEM fault analysis is disclosed that eliminates the warping issues that conventionally occur during the conversion. The conversion begins with the attachment of the semiconductor device to a TEM grid and the subsequent milling of the attached semiconductor device along a first axis to form a first-axis-directed lamella containing a region-of-interest (ROI). One or more markers are then deposited on the first-axis-directed lamella adjacent to the ROI to form a marked first-axis-directed lamella. A strengthening material is then sputtered onto the marked first-axis-directed lamella to cover it with a layer of strengthening material. The first-axis-directed lamella is then detached from the TEM grid and re-mounted in an orthogonal alignment to how it was originally attached to the TEM grid. Guided by the markers, the covered and marked first axis-directed lamella is then milled along a second axis to expose the ROI and form a second-axis-directed lamella, wherein the second axis is substantially orthogonal to the first axis. The sputter deposition of the strengthening layer (e.g., carbon, silicon dioxide, or a metal such as gold, palladium, or chromium) provides rigidity and structural support during the axis conversion of the lamella without the warpage problems from conventional e-beam tungsten deposition techniques. In addition, note that the strengthening material may be deposited using other suitable techniques besides sputtering such as chemical vapor deposition.
These and additional advantages may be better appreciated through the following detailed description.
These aspects of the disclosure and their advantages are best understood by referring to the detailed description that follows. It should be appreciated that like reference numerals are used to identify like elements illustrated in one or more of the figures.
An axis conversion technique for lamellae is provided that avoids the warpage issues that have thwarted prior art axis conversions. The axis conversion may be from a y-directed lamella into an x-directed lamella. Similarly, the axis conversion may be from an x-directed lamella into a y-directed lamella. To better appreciate what is meant by the “y-directed” and “x-directed” lamellae orientations, consider the generic FinFET transistor 100 shown in
Analysis of image 200 may show that a particular fin 105 is defective such that an x-directed axis conversion of the y-directed lamella parallel to a longitudinal axis of the defective fin would be desirable. But note that the y-directed lamella must be quite thin such as a thickness no more than the approximate width of gate 110 (
The carbon deposition covers all the surfaces of the lamella such that it can be problematic to appropriately mill the lamella during its axis conversion into a x-directed lamella. To provide a landmark for the axis conversion, a marker of a suitable material is deposited adjacent to the region-of-interest (such as the defective fin) such as through an electron beam or an ion beam deposition. To distinguish the marker from the strengthening material, it is preferable that the marker be a different material, for example a metal such as tungsten or platinum in the case of a carbon sputtering. The marked-lamella from such a deposition that is then sputtered with carbon. An example SEM image 300 of a x-directed lamella with several tungsten markers 305 prior to the carbon deposition is shown in
A TEM image 400 after an axis conversion of the x-directed lamella of
A method of forming an axis-converted lamella will now be discussed with regard to the flowchart of
As those of some skill in this art will by now appreciate and depending on the particular application at hand, many modifications, substitutions and variations can be made in and to the materials, apparatus, configurations and methods of use of the devices of the present disclosure without departing from the scope thereof. For example, the semiconductor device being milled need not comprise a FinFET but instead may comprise a nanowire device or a planar CMOS transistor. In light of this, the scope of the present disclosure should not be limited to that of the particular embodiments illustrated and described herein, as they are merely by way of some examples thereof, but rather, should be fully commensurate with that of the claims appended hereafter and their functional equivalents.
This application claims the benefit of U.S. Provisional Application No. 62/416,889 filed Nov. 3, 2016.
| Number | Date | Country | |
|---|---|---|---|
| 62416889 | Nov 2016 | US |
