Patent Application
20160300729
Various embodiments described herein relate generally to methods and product for an improved semiconductor device performance, such as harmonic performance. Such semiconductor devices include metal-oxide-semiconductor (“MOS”) field effect transistors (“FET”s), devices with MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) substrates, and trap-rich SOT transistors, among others.
It is desirable to improve interface electrical performance for semiconductor devices including metal-oxide-semiconductor (“MOS”) field effect transistors (“FET”s), and particularly to MOSFETs fabricated on Semiconductor-On-Insulator (“SOI”) and Silicon-On-Sapphire (“SOS”) substrates, the present invention provides methods and apparatus for same.
Herein described are various aspects of disclosure describing the utility of a deuterium anneal over a trap-rich region under a semiconductor device.
According to a first aspect, a semiconductor device is disclosed, comprising: a trap-rich region; a buried oxide layer on the trap-rich layer; a semiconductor layer on the buried oxide layer; and a deuterium rich region at an interface between the buried oxide layer and the trap-rich layer.
According to a second aspect, a method of deuterium annealing a semiconductor device is disclosed, comprising: providing a semiconductor device comprising: a trap-rich layer; a buried oxide layer on the trap-rich layer; a semiconductor layer on the buried oxide layer; and an interface between the buried oxide layer and the trap-rich layer; and contacting the semiconductor device with deuterium gas at a temperature of at least 20° C. and a pressure of at least 1 atmosphere for an interval of time.
Further aspects of the disclosure are presented herein.
The accompanying drawings, which are incorporated into and constitute a part of this specification, illustrate one or more embodiments of the present disclosure and, together with the description of example embodiments, serve to explain the principles and implementations of the disclosure.
Throughout this description, embodiments and variations are described for the purpose of illustrating uses and implementations of the inventive concept. The illustrative description should be understood as presenting examples of the inventive concept, rather than as limiting the scope of the concept as disclosed herein. Embodiments of the present disclosure are directed to methods and apparatus for passivation of semiconductor interfaces by deuterium annealing.
It is an object of the present invention to improve the harmonic performance of a semiconductor device by a deuterium anneal under the oxide layer. In one embodiment, the passivation of dangling bonds and charge traps within the trap-rich layer of a semiconductor device by deuterium annealing improves its harmonic performance as shown by the RF linearity results. The semiconductor device can include, but is not limited to, silicon CMOS, MOSFET, SOI, and SOS. The semiconductor device can include a trap-rich region in the substrate.
As used herein, “a trap-rich region” is meant as a region of high resistivity material with a high density of traps or defects that reduces the carrier lifetimes of the charge carriers. A “trap-rich layer” as used herein refers to a trap-rich region that forms a layer structure. A trap-rich region on the top of the substrate layer can effectively reduce parasitic surface conduction. In one embodiment the trap-rich region is made of a layer of polycrystalline silicon. In another embodiment, the trap-rich region is localized under a device and does not extend beyond the outer boundaries of source and drain regions laterally.
Embodiments of trap-rich materials can include oxygen doped polycrystalline silicon (“SIPOS”), amorphous silicon, polycrystalline silicon, rapid thermal anneal (“RTA”) crystallized polysilicon, and nanocrystalline silicon. The embodiments of trap-rich materials can also include polycrystalline/amorphous silicon carbide (SiC), which has a higher thermal conductivity than most other trap-rich materials and, therefore, will extract heat from the device more efficiently and reduce any increase in device resistance due to self-heating during operation.
In one embodiment, the trap-rich region has a bulk resistivity in a range of 1,000 to 10,000 Ohm-cm. In another embodiment, the trap-rich region has a resistivity profile in a range of 2,000 to 8,000 Ohm-cm.
In one embodiment, the trap-rich region is a layer with a thickness in a range of 0.1 to 10 micrometers. In another embodiment, the trap-rich region is a layer with a thickness in the range of 0.5 to 2 micrometers.
A dangling bond as used herein refers to an unsatisfied valence on an immobilized atom. In one embodiment, a dangling bond is present in a silicon atom at the poly-silicon grain boundary. In another embodiment, a dangling bond is present at the gate oxide to silicon interface. In one embodiment, a dangling bond is present at the buried oxide-substrate silicon interface. In another embodiment, a dangling bond is present at the buried oxide to silicon interface. The presence of dangling bonds can facilitate the current flow between the source and drain at these interfaces. The dangling bonds in a substrate act as trapped charges and affect device performance.
A typical bulk silicon MOSFET transistor is shown in
A silicon atom with a dangling bond is capable of forming a complete covalent bond. Without being bound by the theory, it is understood that silicon dangling bonds are capable of covalent bond formation with deuterium and thus become passivated. The passivation by deuterium in effect neutralizes the trapped charge. As described herein, a deuterium anneal passivates dangling bonds at the oxide-silicon interface and improves device performance.
An interface 121 is formed between the gate oxide layer 120 and channel region 114 of the substrate 110.
In one embodiment, deuterium anneal is performed on a device or a wafer that has been previously annealed with hydrogen. In another embodiment, deuterium anneal is performed on a device or a wafer that has not been previously hydrogen annealed.
In one embodiment, deuterium anneal is performed on a wafer prior to device fabrication. In another embodiment, deuterium anneal is performed on a wafer after device fabrication.
A typical semiconductor-on-insulator (“SOT”) structure is shown in
As shown in
In one embodiment, the buried-oxide is made of sapphire to give silicon-on-sapphire (“SOS”) devices. Such a SOS device can be advantageously used for high-performance radio frequency (RF) and radiation-sensitive applications.
During device operation, a charge layer can build up at the interface 223 under the BOX 210. The charge layer can severely degrade the harmonic performance of the RF devices on the SOT substrates.
Referring to
Referring to
The trap-rich region 410 can be made of a layer of polycrystalline silicon which contains dangling bonds at the polycrystalline grains boundaries as well as at the buried oxide-polycrystalline interface 323. In addition, the trap-rich region may include a modified region of the substrate in which the charge traps are introduced by disrupting the crystalline substrate by means of ion-implantation, for example. Passivation, near the interface 323, of these dangling bonds with deuterium reduces charge traps and enhances the harmonic performance of such devices at radio frequencies.
In one embodiment, the deuterium anneal was performed after device fabrication. The deuterium anneal was performed in a high pressure furnace under the following conditions in Table 1. The device could be previously hydrogen annealed, but it is envisioned that the process can be performed with devices that are not pre-annealed (i.e. only having deuterium anneal). Even with a hydrogen pre-anneal of a device, the deuterium can displace the hydrogen such that a majority of the passivation in the device is from deuterium (i.e., there is more deuterium than hydrogen in the region). As is shown in Table 1, the oxygen content of the silicon substrate can be low or high.
As used herein, ppma refers to parts per million atoms. In one embodiment, the value for low oxygen content is about 5 N-ppma. In another embodiment, the value for high oxygen content is about 15 N-ppma. The N-ppma values are based on the ASTM-F1188 standard for determination of the interstitial oxygen content of single crystal silicon.
Results of testing the CPW harmonic performance for Split #1 (i.e., D2anneal at 400 ° C. for 30 minutes at 20 atmospheres with “Low” oxygen) are summarized in Table 2. The coplanar waveguide is an electrical transmission line consisting of 3 parallel, conducting metal strips as shown in
In one embodiment the tested device is a transistor. The gate length (Lg) of the transistor was 0.2 μm. For the ‘ON’ harmonic measurement, transistors with a gate width of 0.5 mm were used; whilst for the ‘OFF’ harmonic measurement, transistors with a gate width of 2 mm were used instead. All harmonic results were measured in dBm units. As is shown in Table 2, a larger negative number implies an improved harmonic performance.
The effect of 400° C. anneal duration on the harmonic performance is shown in Table 3 for Split #1 and 3.
Both the substrate harmonic performance (CPW measurement) and the device harmonics are improved after deuterium anneal as shown in the result for Split #1.
The deuterium anneal duration affects the harmonic performance of the substrate. A comparison of Split #1 and 3 shows that a 60 minute anneal gives a better substrate harmonic improvement (“enhancement”) than a 30 minute anneal with all other conditions being the same.
Applications that can include the novel apparatus and systems of various embodiments include electronic circuitry used in high-speed computers, communication and signal processing circuitry, modems, single or multi-processor modules, single or multiple embedded processors, data switches, and application-specific modules, including multilayer, multi-chip modules. Such apparatus and systems can further be included as sub-components within a variety of electronic systems, such as televisions, cellular telephones, personal computers (e.g., laptop computers, desktop computers, handheld computers, tablet computers, etc.), workstations, radios, video players, audio players (e.g., mp3 players), vehicles, medical devices (e.g., heart monitor, blood pressure monitor, etc.) and others. Some embodiments can include a number of methods.
It can be possible to execute the activities described herein in an order other than the order described. Various activities described with respect to the methods identified herein can be executed in repetitive, serial, or parallel fashion.
The accompanying drawings that form a part hereof show, by way of illustration and not of limitation, specific embodiments in which the subject matter can be practiced. The embodiments illustrated are described in sufficient detail to enable those skilled in the art to practice the teachings disclosed herein. Other embodiments can be utilized and derived therefrom, such that structural and logical substitutions and changes can be made without departing from the scope of this disclosure. This disclosure, therefore, is not to be taken in a limiting sense, and the scope of various embodiments is defined only by the appended claims, along with the full range of equivalents to which such claims are entitled.
Such embodiments of the inventive subject matter can be referred to herein, individually or collectively, by the term “invention” merely for convenience and without intending to voluntarily limit the scope of this application to any single invention or inventive concept, if more than one is in fact disclosed. Thus, although specific embodiments have been illustrated and described herein, any arrangement calculated to achieve the same purpose can be substituted for the specific embodiments shown. This disclosure is intended to cover any and all adaptations or variations of various embodiments. Combinations of the above embodiments, and other embodiments not specifically described herein, will be apparent to those of skill in the art upon reviewing the above description.
An Abstract of the disclosure is provided to comply with 37 C.F.R. §1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In the foregoing disclosure, various features are grouped together in a single embodiment for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted to require more features than are expressly recited in each claim. Rather, inventive subject matter can be found in less than all features of a single disclosed embodiment. Thus the following claims are hereby incorporated into the disclosure herein, with each claim standing on its own as a separate embodiment.
