Patent Application
20180286918
Semiconductor memory is widely used in various electronic devices such as mobile computing devices, mobile phones, solid-state drives, digital cameras, personal digital assistants, medical electronics, servers, and non-mobile computing devices. Semiconductor memory may include non-volatile memory or volatile memory. A non-volatile memory device allows information to be stored or retained even when the non-volatile memory device is not connected to a power source.
One example of non-volatile memory uses non-volatile memory cells that include reversible resistance-switching memory elements that may be reversibly switched between a high resistance state and a low resistance state. The memory cells may be individually connected between first and second conductors (e.g., a bit line electrode and a word line electrode). The state of such a memory cell is typically changed by proper voltages being placed on the first and second conductors.
In recent years, non-volatile memory devices have been scaled to reduce the cost per bit. However, as process geometries shrink, many design and process challenges are presented.
FIGS. 2C1-2C3 depict an embodiment of a portion of a monolithic three-dimensional memory array.
FIGS. 5A1-5H3 are cross-sectional views of a portion of a substrate during an example fabrication of the monolithic three-dimensional memory array of
Technology is described for including isolation elements in a non-volatile memory cell, such as a reversible resistance-switching memory cell. The non-volatile memory cell is disposed between a word line and a bit line. The non-volatile memory cell includes an isolation element that includes a semiconductor material disposed between a first conductor and a second conductor. The semiconductor material may be amorphous silicon-germanium (α-SiGe), the first conductor may be copper (Cu) and the second conductor may be titanium nitride (TiN).
In some embodiments, a memory array may include a cross-point memory array. A cross-point memory array may refer to a memory array in which two-terminal non-volatile memory cells are placed at the intersections of a first set of control lines (e.g., word lines) arranged in a first direction and a second set of control lines (e.g., bit lines) arranged in a second direction perpendicular to the first direction. The two-terminal non-volatile memory cells may include a reversible resistance-switching memory element, such as a phase change material, a ferroelectric material, or a metal oxide (e.g., hafnium oxide), disposed between first and second conductors. Example reversible resistance-switching memory elements include a phase change material, a ferroelectric material, a metal oxide (e.g., hafnium oxide), a barrier modulated switching structure, or other similar reversible resistance-switching memory elements.
Example barrier modulated switching structures include a semiconductor material layer adjacent a conductive oxide material layer (e.g., an amorphous silicon layer adjacent a crystalline titanium oxide layer). Other example barrier modulated switching structures include a thin (e.g., less than about 2 nm) barrier oxide material disposed between the semiconductor material layer and the conductive oxide material layer (e.g., an aluminum oxide layer disposed between an amorphous silicon layer and a crystalline titanium oxide layer). As used herein, a memory cell that includes a barrier modulated switching structure is referred to herein as a “barrier modulated cell” (BMC).
In some embodiments, each non-volatile memory cell in a cross-point memory array includes a reversible resistance-switching memory element in series with a steering element or an isolation element, such as one or more diodes, to reduce leakage currents. In other cross-point memory arrays, the non-volatile memory cells do not include isolation elements.
In an embodiment, a non-volatile storage system may include one or more two-dimensional arrays of non-volatile memory cells. The non-volatile memory cells within a two-dimensional memory array may form a single layer of non-volatile memory cells and may be selected via control lines (e.g., word lines and bit lines) in the X and Y directions. In another embodiment, a non-volatile storage system may include one or more monolithic three-dimensional memory arrays in which two or more layers of non-volatile memory cells may be formed above a single substrate without any intervening substrates.
In some cases, a three-dimensional memory array may include one or more vertical columns of non-volatile memory cells located above and orthogonal to a substrate. In an example, a non-volatile storage system may include a memory array with vertical bit lines or bit lines that are arranged orthogonal to a semiconductor substrate. The substrate may include a silicon substrate. The memory array may include rewriteable non-volatile memory cells, wherein each non-volatile memory cell includes a reversible resistance-switching memory element and an isolation element in series with the reversible resistance-switching memory element. In other embodiments, each non-volatile memory cell includes a reversible resistance-switching memory element without an isolation element in series with the reversible resistance-switching memory element.
In some embodiments, a non-volatile storage system may include a non-volatile memory that is monolithically formed in one or more physical levels of arrays of non-volatile memory cells having an active area disposed above a silicon substrate. The non-volatile storage system may also include circuitry associated with the operation of the non-volatile memory cells (e.g., decoders, state machines, page registers, and/or control circuitry for controlling reading, programming and erasing of the non-volatile memory cells). The circuitry associated with the operation of the non-volatile memory cells may be located above the substrate or within the substrate.
In some embodiments, a non-volatile storage system may include a monolithic three-dimensional memory array. The monolithic three-dimensional memory array may include one or more levels of non-volatile memory cells. Each non-volatile memory cell within a first level of the one or more levels of non-volatile memory cells may include an active area that is located above a substrate (e.g., above a single-crystal substrate or a crystalline silicon substrate). In one example, the active area may include a semiconductor junction (e.g., a P-N junction). The active area may include a portion of a source or drain region of a transistor. In another example, the active area may include a channel region of a transistor.
Memory chip controller 104 may include one or more state machines, page registers, SRAM, and control circuitry for controlling the operation of memory chip 106. The one or more state machines, page registers, SRAM, and control circuitry for controlling the operation of memory chip 106 may be referred to as managing or control circuits. The managing or control circuits may facilitate one or more memory array operations, such as forming, erasing, programming, and reading operations.
In some embodiments, the managing or control circuits (or a portion of the managing or control circuits) for facilitating one or more memory array operations may be integrated within memory chip 106. Memory chip controller 104 and memory chip 106 may be arranged on a single integrated circuit. In other embodiments, memory chip controller 104 and memory chip 106 may be arranged on different integrated circuits. In some cases, memory chip controller 104 and memory chip 106 may be integrated on a system board, logic board, or a PCB.
Memory chip 106 includes memory core control circuits 108 and a memory core 110. Memory core control circuits 108 may include logic for controlling the selection of memory blocks (or arrays) within memory core 110, controlling the generation of voltage references for biasing a particular memory array into a read or write state, and generating row and column addresses.
Memory core 110 may include one or more two-dimensional arrays of non-volatile memory cells or one or more three-dimensional arrays of non-volatile memory cells. In an embodiment, memory core control circuits 108 and memory core 110 are arranged on a single integrated circuit. In other embodiments, memory core control circuits 108 (or a portion of memory core control circuits 108) and memory core 110 may be arranged on different integrated circuits.
A memory operation may be initiated when host 102 sends instructions to memory chip controller 104 indicating that host 102 would like to read data from memory system 100 or write data to memory system 100. In the event of a write (or programming) operation, host 102 will send to memory chip controller 104 both a write command and the data to be written. The data to be written may be buffered by memory chip controller 104 and error correcting code (ECC) data may be generated corresponding with the data to be written. The ECC data, which allows data errors that occur during transmission or storage to be detected and/or corrected, may be written to memory core 110 or stored in non-volatile memory within memory chip controller 104. In an embodiment, the ECC data are generated and data errors are corrected by circuitry within memory chip controller 104.
Memory chip controller 104 controls operation of memory chip 106. In one example, before issuing a write operation to memory chip 106, memory chip controller 104 may check a status register to make sure that memory chip 106 is able to accept the data to be written. In another example, before issuing a read operation to memory chip 106, memory chip controller 104 may pre-read overhead information associated with the data to be read. The overhead information may include ECC data associated with the data to be read or a redirection pointer to a new memory location within memory chip 106 in which to read the data requested. Once a read or write operation is initiated by memory chip controller 104, memory core control circuits 108 may generate the appropriate bias voltages for word lines and bit lines within memory core 110, and generate the appropriate memory block, row, and column addresses.
In some embodiments, one or more managing or control circuits may be used for controlling the operation of a memory array. The one or more managing or control circuits may provide control signals to a memory array to perform an erase operation, a read operation, and/or a write operation on the memory array. In one example, the one or more managing or control circuits may include any one of or a combination of control circuitry, state machine, decoders, sense amplifiers, read/write circuits, and/or controllers. The one or more managing circuits may perform or facilitate one or more memory array operations including erasing, programming, or reading operations. In one example, one or more managing circuits may include an on-chip memory controller for determining row and column address, word line and bit line addresses, memory array enable signals, and data latching signals.
Address decoders 120 may generate memory block addresses, as well as row addresses and column addresses for a particular memory block. Voltage generators (or voltage regulators) for first control lines 122 may include one or more voltage generators for generating first (e.g., selected) control line voltages. Voltage generators for second control lines 124 may include one or more voltage generators for generating second (e.g., unselected) control line voltages. Signal generators for reference signals 126 may include one or more voltage and/or current generators for generating reference voltage and/or current signals.
As depicted, read/write circuits 146 may be shared across multiple memory blocks within a memory bay. This allows chip area to be reduced because a single group of read/write circuits 146 may be used to support multiple memory blocks. However, in some embodiments, only a single memory block may be electrically coupled to read/write circuits 146 at a particular time to avoid signal conflicts.
In some embodiments, read/write circuits 146 may be used to write one or more pages of data into memory blocks 140-144 (or into a subset of the memory blocks). The non-volatile memory cells within memory blocks 140-144 may permit direct over-writing of pages (i.e., data representing a page or a portion of a page may be written into memory blocks 140-144 without requiring an erase or reset operation to be performed on the non-volatile memory cells prior to writing the data).
In one example, memory system 100 of
In some cases, read/write circuits 146 may be used to program a particular non-volatile memory cell to be in one of three or more data/resistance states (i.e., the particular non-volatile memory cell may include a multi-level non-volatile memory cell). In one example, read/write circuits 146 may apply a first voltage difference (e.g., 2V) across the particular non-volatile memory cell to program the particular non-volatile memory cell into a first state of the three or more data/resistance states or a second voltage difference (e.g., 1V) across the particular non-volatile memory cell that is less than the first voltage difference to program the particular non-volatile memory cell into a second state of the three or more data/resistance states.
Applying a smaller voltage difference across the particular non-volatile memory cell may cause the particular non-volatile memory cell to be partially programmed or programmed at a slower rate than when applying a larger voltage difference. In another example, read/write circuits 146 may apply a first voltage difference across the particular non-volatile memory cell for a first time period to program the particular non-volatile memory cell into a first state of the three or more data/resistance states, and apply the first voltage difference across the particular non-volatile memory cell for a second time period less than the first time period. One or more programming pulses followed by a non-volatile memory cell verification phase may be used to program the particular non-volatile memory cell to be in the correct state.
Row decoder 152 decodes a row address and selects a particular word line in memory array 150 when appropriate (e.g., when reading or writing non-volatile memory cells in memory array 150). Column decoder 154 decodes a column address and selects one or more bit lines in memory array 150 to be electrically coupled to read/write circuits, such as read/write circuits 146 in
Row decoders 152a and 152b may be split such that even word lines in memory array 150a are driven by row decoder 152a and odd word lines in memory array 150a are driven by row decoder 152b. Row decoders 152c and 152b may be split such that even word lines in memory array 150b are driven by row decoder 152c and odd word lines in memory array 150b are driven by row decoder 152b.
Column decoders 154a and 154b may be split such that even bit lines in memory array 150a are controlled by column decoder 154b and odd bit lines in memory array 150a are driven by column decoder 154a. Column decoders 154c and 154d may be split such that even bit lines in memory array 150b are controlled by column decoder 154d and odd bit lines in memory array 150b are driven by column decoder 154c.
The selected bit lines controlled by column decoder 154a and column decoder 154c may be electrically coupled to read/write circuits 146a. The selected bit lines controlled by column decoder 154b and column decoder 154d may be electrically coupled to read/write circuits 146b. Splitting the read/write circuits into read/write circuits 146a and 146b when the column decoders are split may allow for a more efficient layout of the memory bay.
As depicted, disposed between the intersection of each local bit line and each word line is a particular non-volatile memory cell (e.g., non-volatile memory cell M111 is disposed between local bit line LBL11 and word line WL10). The particular non-volatile memory cell may include a floating gate memory element, a charge trap memory element (e.g., using a silicon nitride material), a reversible resistance-switching memory element, or other similar device. The global bit lines GBL1-GBL3 are arranged in a third direction (e.g., a y-direction) that is perpendicular to both the first direction and the second direction.
Each local bit line LBL11-LBL33 has an associated bit line select transistor Q11-Q33, respectively. Bit line select transistors Q11-Q33 may be field effect transistors, such as shown, or may be any other transistors. As depicted, bit line select transistors Q11-Q31 are associated with local bit lines LBL11-LBL31, respectively, and may be used to connect local bit lines LBL11-LBL31 to global bit lines GBL1-GBL3, respectively, using row select line SG1. In particular, each of bit line select transistors Q11-Q31 has a first terminal (e.g., a drain/source terminal) coupled to a corresponding one of local bit lines LBL11-LBL31, respectively, a second terminal (e.g., a source/drain terminal) coupled to a corresponding one of global bit lines GBL1-GBL3, respectively, and a third terminal (e.g., a gate terminal) coupled to row select line SG1.
Similarly, bit line select transistors Q12-Q32 are associated with local bit lines LBL12-LBL32, respectively, and may be used to connect local bit lines LBL12-LBL32 to global bit lines GBL1-GBL3, respectively, using row select line SG2. In particular, each of bit line select transistors Q12-Q32 has a first terminal (e.g., a drain/source terminal) coupled to a corresponding one of local bit lines LBL12-LBL32, respectively, a second terminal (e.g., a source/drain terminal) coupled to a corresponding one of global bit lines GBL1-GBL3, respectively, and a third terminal (e.g., a gate terminal) coupled to row select line SG2.
Likewise, bit line select transistors Q13-Q33 are associated with local bit lines LBL13-LBL33, respectively, and may be used to connect local bit lines LBL13-LBL33 to global bit lines GBL1-GBL3, respectively, using row select line SG3. In particular, each of bit line select transistors Q13-Q33 has a first terminal (e.g., a drain/source terminal) coupled to a corresponding one of local bit lines LBL13-LBL33, respectively, a second terminal (e.g., a source/drain terminal) coupled to a corresponding one of global bit lines GBL1-GBL3, respectively, and a third terminal (e.g., a gate terminal) coupled to row select line SG3.
Because a single bit line select transistor is associated with a corresponding local bit line, the voltage of a particular global bit line may be applied to a corresponding local bit line. Therefore, when a first set of local bit lines (e.g., LBL11-LBL33) is biased to global bit lines GBL1-GBL3, the other local bit lines (e.g., LBL32-LBL32 and LBL13-LBL33) must either also be driven to the same global bit lines GBL1-GBL3 or be floated.
In an embodiment, during a memory operation, all local bit lines within the memory array are first biased to an unselected bit line voltage by connecting each of the global bit lines to one or more local bit lines. After the local bit lines are biased to the unselected bit line voltage, then only a first set of local bit lines LBL11-LBL33 are biased to one or more selected bit line voltages via the global bit lines GBL1-GBL3, while the other local bit lines (e.g., LBL12-LBL32 and LBL13-LBL33) are floated. The one or more selected bit line voltages may correspond with, for example, one or more read voltages during a read operation or one or more programming voltages during a programming operation.
In an embodiment, a vertical bit line memory array, such as memory array 200, includes a greater number of non-volatile memory cells along the word lines as compared with the number of non-volatile memory cells along the vertical bit lines (e.g., the number of non-volatile memory cells along a word line may be more than 10 times the number of non-volatile memory cells along a bit line). In one example, the number of non-volatile memory cells along each bit line may be 16 or 32, whereas the number of non-volatile memory cells along each word line may be 2048 or more than 4096. Other numbers of non-volatile memory cells along each bit line and along each word line may be used.
In an embodiment of a read operation, the data stored in a selected non-volatile memory cell (e.g., non-volatile memory cell M111) may be read by biasing the word line connected to the selected non-volatile memory cell (e.g., selected word line WL10) to a selected word line voltage in read mode (e.g., 0V). The local bit line (e.g., LBL11) coupled to the selected non-volatile memory cell (M111) is biased to a selected bit line voltage in read mode (e.g., 1 V) via the associated bit line select transistor (e.g., Q11) coupled to the selected local bit line (LBL11), and the global bit line (e.g., GBL1) coupled to the bit line select transistor (Q11). A sense amplifier may then be coupled to the selected local bit line (LBL11) to determine a read current IREAD of the selected non-volatile memory cell (M111). The read current IREAD is conducted by the bit line select transistor Q11, and may be between about 100 nA and about 500 nA, although other read currents may be used.
In an embodiment of a write operation, data may be written to a selected non-volatile memory cell (e.g., non-volatile memory cell M221) by biasing the word line connected to the selected non-volatile memory cell (e.g., WL20) to a selected word line voltage in write mode (e.g., 5V). The local bit line (e.g., LBL21) coupled to the selected non-volatile memory cell (M221) is biased to a selected bit line voltage in write mode (e.g., 0 V) via the associated bit line select transistor (e.g., Q21) coupled to the selected local bit line (LBL21), and the global bit line (e.g., GBL2) coupled to the bit line select transistor (Q21). During a write operation, a programming current IPGRM is conducted by the associated bit line select transistor Q21, and may be between about 3 uA and about 6 uA, although other programming currents may be used.
Monolithic three-dimensional memory array 202 includes word lines WL10, WL11, WL12, . . . , WL42 that are formed in a first direction (e.g., an x-direction), vertical bit lines LBL11, LBL12, LBL13, . . . , LBL33 that are formed in a second direction perpendicular to the first direction (e.g., a z-direction), and non-volatile memory material 214 formed in the second direction (e.g., the z-direction). A spacer 216 made of a dielectric material (e.g., silicon dioxide, silicon nitride, or other dielectric material) is disposed between adjacent word lines WL10, WL11, WL12, . . . , WL42.
Non-volatile memory material 214 may include, for example, an oxide material, a reversible resistance-switching memory material (e.g., one or more metal oxide layers such as nickel oxide, hafnium oxide, or other similar metal oxide materials, a phase change material, a barrier modulated switching structure or other similar reversible resistance-switching memory material), a ferroelectric material, or a charge trapping material (e.g., a layer of silicon nitride). In an embodiment, non-volatile memory material 214 may include a single continuous layer of material that may be used by a plurality of non-volatile memory cells or devices.
In an embodiment, portions of non-volatile memory material 214 may include a part of a first non-volatile memory cell associated with the cross section between WL12 and LBL13 and a part of a second non-volatile memory cell associated with the cross section between WL22 and LBL13. In some cases, a vertical bit line, such as LBL13, may include a vertical structure (e.g., a rectangular prism, a cylinder, or a pillar) and the non-volatile material may completely or partially surround the vertical structure (e.g., a conformal layer of phase change material surrounding the sides of the vertical structure).
As depicted, each of the vertical bit lines LBL11, LBL12, LBL13, . . . , LBL33 may be connected to one of a set of global bit lines via an associated vertically-oriented bit line select transistor (e.g., Q11, Q12, Q13, Q23). Each vertically-oriented bit line select transistor may include a MOS device (e.g., an NMOS device) or a vertical thin-film transistor (TFT).
In an embodiment, each vertically-oriented bit line select transistor is a vertically-oriented pillar-shaped TFT coupled between an associated local bit line pillar and a global bit line. In an embodiment, the vertically-oriented bit line select transistors are formed in a pillar select layer formed above a CMOS substrate, and a memory layer that includes multiple layers of word lines and memory elements is formed above the pillar select layer.
FIGS. 2C1-2C3 depict an embodiment of a portion of a monolithic three-dimensional memory array 204 that includes a first memory level 218, a second memory level 220 positioned above first memory level 218, a third memory level 222 positioned above second memory level 220, and a fourth memory level 224 positioned above third memory level 222. Memory array 204 is one example of an implementation for memory array 150 of
As depicted, disposed between the intersection of each local bit line and each word line is a particular non-volatile memory cell. For example, non-volatile memory cell M111 is disposed between local bit line LBL11 and word line WL10, non-volatile memory cell M225 is disposed between local bit line LBL23 and word line WL22, and non-volatile memory cell M433 is disposed between local bit line LBL32 and word line WL41.
In an embodiment, each non-volatile memory cell includes a reversible resistance-switching memory element coupled in series with an isolation element. For example, non-volatile memory cell M414 includes reversible resistance-switching memory element R414 coupled in series with isolation element S414, non-volatile memory cell M321 includes reversible resistance-switching memory element R321 coupled in series with isolation element S321, and non-volatile memory cell M233 includes reversible resistance-switching memory element R233 coupled in series with isolation element S233.
In an embodiment, each of isolation elements S111-S436 of monolithic three-dimensional memory array 204 exhibits an ON-state current density of greater than about 1-5 MA/cm2, an OFF-state leakage current of less than about 10-20 nA@1V, and an ON/OFF current ratio of greater than about 500. In addition, in an embodiment, each of isolation elements S111-S436 of monolithic three-dimensional memory array 204 exhibits bipolar operation, such as depicted in the current versus voltage diagram depicted in
Isolation element optionally may include a first capping layer 310a disposed between semiconductor layer 306 and barrier layer 308, and a second capping layer 310b disposed between semiconductor layer 306 and second electrode 304. Although depicted in
In an embodiment, first electrode 302 is Cu, with a thickness of between about 10 nm and about 100 nm, second electrode 304 is TiN, with a thickness of between about 10 nm and about 100 nm, semiconductor layer 306 is silicon-germanium (SixGe1-x, with x between about 0.3 to about 0.7), with a thickness of between about 5 nm and about 20 nm, and barrier layer 308 is tantalum nitride (TaN), with a thickness of between about 1 nm and about 5 nm. Optional first capping layer 310a and second capping layer 310b each may be silicon, with a thickness of between about 1 nm and about 5 nm. Other materials, thicknesses and ratios may be used.
In an embodiment, semiconductor layer 306 is amorphous silicon-germanium (α-SixGe1-x), and can be deposited by low pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) (e.g., sputtering), or other process. Amorphous silicon (α-Si) is a non-crystalline form of silicon in which the silicon atoms form a continuous random network. Alternatively, semiconductor layer 306 may be polycrystalline silicon-germanium. In embodiments, semiconductor layer 306 may be one or more of silicon, germanium, SixGe1-x or other similar semiconductor materials or low density oxides such as hafnium oxide (HfO2), silicon oxide (SiOx), titanium oxide (TiO2), tungsten oxide (WO), zinc oxide ZnO or other similar low density oxides. In embodiments, semiconductor layer 306 may be a doped or an undoped semiconductor material, and may be amorphous or polycrystalline.
In other embodiments, first electrode 302 may be one or more of Cu, silver (Ag), nickel (Ni) or other metal, second electrode 304 may be one or more of TiN, a conductive carbon, platinum (Pt), ruthenium (Ru), palladium (Pd), iridium (Ir), titanium aluminum nitride (TiAlN), tungsten (W), or other conductive material, barrier layer 308 may be one or more of titanium (Ti), tantalum (Ta), TiN, TaN, tungsten nitride (WN), tantalum carbide (TaC), or other barrier layer material, first capping layer 310a and second capping layer 310b may be SiOx, aluminum oxide (Al2O3), or other similar material. In other embodiments, another metal cap layer such as TaN, TiN, Al, etc., may be added on top of first electrode 302 for better current confinement during switching/cycling and improved Cu ionization. For simplicity, the remaining description assumes that first electrode 302 is copper, second electrode 304 is TiN, semiconductor layer 306 is a-SixGe1-x, and barrier layer 308 is TaN.
In an embodiment, isolation element 300 operates as a threshold switching device.
Without wanting to be bound by any particular theory, and assuming that first electrode 302 is Cu, it is believed that during forming, voltage induced migration of Cu ions takes place from the TEL (TEL acts as an ion source) towards the BEL. As a result, it is believed that a metallic Cu filament is formed due to an electrochemical reaction which changes a resistance of the cell. A forming bias condition is chosen to obtain a desired cell conductivity, which is monitored by a cell current (ICELL) measurement after each pulse (or during a voltage sweep). In an embodiment, a target ICELL (@1V) is in the range of between about 50 nA and about 200 nA. It is believed that after the initial positive forming, segregated Cu at the BEL may serve as reservoir and act as cation injector (virtual Cu electrode) for negative polarity switching.
In an embodiment, a forming step uses an incremental step pulse program (ISPP) algorithm in which a voltage amplitude is increased gradually for a fixed pulse width with I-limit Forming (
Persons of ordinary skill in the art will understand that forming pulses may be current pulses, and that other pulse magnitude, pulse duration, pulse rise time and Iverify values may be used. Persons of ordinary skill in the art will understand that the forming step may be performed using multiple pulse (burst mode), DC sweep, multilevel soft forming, a combination of forward and reverse forming (e.g., for better filament control), or other similar forming methods.
Following the forming step, voltage (or current) pulses may be applied to isolation element 300 to switch isolation element 300 ON or OFF. In an embodiment, if positive voltage pulses exceeding a first threshold voltage VTHP are applied to first electrode 302 while second electrode 304 is grounded, isolation element 300 switches from OFF to ON, and stays ON until the voltage pulse falls below a first hold voltage, VHP.
For positive polarity switching, an ISPP algorithm is used in which the pulse voltage is incremented (positive) and the pulse current is measured (e.g., using an oscilloscope) until an “I-limit switching” point is reached, as illustrated in
In an embodiment, during this sequence of pulsing, the pulse current is also measured (e.g., using an oscilloscope). In an embodiment, a sharp drop in current is observed at VHP (Holding Voltage) and the cell moves to the OFF state. In an embodiment, after each pulse (increment/decrement) ICELL@VREAD is monitored to check cell damage. In embodiments, VREAD=1V or other value, typically much less than VTHP. In an embodiment, this completes one cycle (in positive polarity) of threshold switching (TS) of the cell from the TEL side.
In embodiments, first threshold voltage VTHP may be between about 1.2 V and about 2.5 V, and first hold voltage VHP may be between about 1.0 V and about 2 V, although other values may be obtained based on the switching algorithm that is used. In an embodiment, voltage (or current) pulses having a trapezoidal shape (e.g., rise time less than fall time) are used, although other pulse shapes may be used. In embodiments, between about 10 to about 50 positive threshold switching operations are performed before opposite polarity (negative polarity) switching is started so that there is enough segregated Cu available in the BEL reservoir and in the SiGe system to enable stable bipolar threshold switching I-V characteristics, such as shown in
In another embodiment, if positive voltage pulses exceeding a second threshold voltage VTHN are applied to second electrode 304 while first electrode 302 is grounded, isolation element 300 switches from OFF to ON, and stays ON until the voltage pulse falls below a second hold voltage, VHN. In an embodiment, for reverse operation of the cell the same flow as described above is used with voltage pulses applied from the BEL. This will result in the negative I-V characteristic shown in
In embodiments, second threshold voltage VTHN may be between about 1.5V and about 2.7 V, and second hold voltage VHN may be between about 1.2V and about 2 V, although other values may be used. In an embodiment, voltage (or current) pulses having a trapezoidal shape (e.g., rise time less than fall time) are used, although other pulse shapes may be used.
Without wanting to be bound by any particular theory, it is believed that first electrode 302 may function as an active electrode (ion source), semiconductor layer 306 may function as an ion conducting layer (solid electrolyte), barrier layer 308 may limit ion movement from first electrode 302 to semiconductor layer 306 (solid electrolyte) during switching and may function as a local resistor to limit capacitive surge currents during switching, second electrode 304 may function as a counter-electrode, and first capping layer 310a and second capping layer 310b may prevent germanium loss due to subsequent process steps and may act as tunnel barrier that may further reduce IOFF. Second capping layer 310b also may acts as a seed layer for the α-SixGe1-x.
In an embodiment, during fabrication of isolation element 300, semiconductor layer 306 is annealed in H2 (30-50%) at a temperature of between about 350° C. and about 450° C. for between about 30 minutes and about 120 minutes. Other temperatures and processing times may be used. Without wanting to be bound by any particular theory, it is believed that annealing isolation element 300 may reduce leakage current of isolation element 300 by reducing the trap levels in α-SixGe1-x, for example, from several hundreds of nano-amps without annealing to tens of nano-amps with annealing. Other leakage current values may be used.
In an embodiment, the above-specified anneal may be performed immediately after silicon deposition. Other anneals such as an H2/D2 high pressure anneal (HPA) (e.g., 9-20 atm/30 min./350 C) also can be employed to achieve similar or better results. HPA is particularly useful as it is normally done at lower temperature than furnace anneal and may be employed after the complete processing of a wafer.
Referring again to FIGS. 2C1-2C3, isolation elements S111-S436 are each coupled between one of local bit lines LBL11-LBL33 and a corresponding one of reversible resistance-switching memory elements R111-R436, respectively. Accordingly, in an embodiment, each of isolation elements S111-S436 may include one of isolation elements 300 of
The monolithic three-dimensional memory array 204 illustrated in FIGS. 2C1-2C3 includes vertical bit lines and horizontal word lines. The technology described above also may be used in other monolithic three-dimensional memory array configurations. For example, a cross-point memory array may include non-volatile memory cells each having a reversible resistance-switching memory element coupled in series with an isolation element such as isolation element 300 described above and illustrated in
Monolithic three-dimensional memory array 400 includes vertical bit lines LBL11-LBL33 arranged in a first direction (e.g., a z-direction), word lines WL10, WL11, . . . , WL43 arranged in a second direction (e.g., an x-direction) perpendicular to the first direction, row select lines SG1, SG2, SG3 arranged in the second direction, and global bit lines GBL1, GBL2, GBL3 arranged in a third direction (e.g., a y-direction) perpendicular to the first and second directions. Vertical bit lines LBL11-LBL33 are disposed above global bit lines GBL1, GBL2, GBL3, which each have a long axis in the second (e.g., x-direction). Person of ordinary skill in the art will understand that monolithic three-dimensional memory arrays, such as monolithic three-dimensional memory array 400 may include more or fewer than twenty-four word lines, three row select lines, three global bit lines, and nine vertical bit lines.
In an embodiment, global bit lines GBL1, GBL2, GBL3 are disposed above a substrate 402, such as a silicon, germanium, silicon-germanium, undoped, doped, bulk, silicon-on-insulator (“SOP”) or other substrate with or without additional circuitry. In an embodiment, an isolation layer 404, such as a layer of silicon dioxide, silicon nitride, silicon oxynitride or any other suitable insulating layer, is formed above substrate 402. In an embodiment, global bit lines GBL1, GBL2, GBL3 are formed of a conductive material 406, such as tungsten or another appropriate metal, heavily doped semiconductor material, a conductive silicide, a conductive silicide-germanide, a conductive germanide, or the like deposited by any suitable method (e.g., CVD, PVD, etc.).
In an embodiment, a first dielectric material layer 408 (e.g., silicon dioxide) and a second dielectric material layer 410 (e.g., silicon dioxide) are formed above isolation layer 404. Global bit lines GBL1, GBL2, GBL3 are disposed above isolation layer 404 and are separated from one another by first dielectric material layer 408. Row select lines SG1, SG2, SG3 are disposed above global bit lines GBL1, GBL2, GBL3. A first etch stop layer 412 (e.g., silicon nitride) is disposed above second dielectric material layer 410. A stack of word lines WL10, WL11, . . . , WL43 is disposed above first etch stop layer 412, with a third dielectric material layer 414 (e.g., silicon dioxide) separating adjacent word lines.
A non-volatile memory cell is disposed between the intersection of vertical bit lines LBL11-LBL33 and word lines WL10, WL11, . . . , WL43. For example, a non-volatile memory cell M111 is disposed between vertical bit line LBL11 and word line WL10, a non-volatile memory cell M116 is disposed between vertical bit line LBL13 and word line WL13, a non-volatile memory cell M411 is disposed between vertical bit line LBL11 and word line WL40, and so on. In an embodiment, monolithic three-dimensional memory array 400 includes seventy-two non-volatile memory cells M111, M112, . . . , M436. Persons of ordinary skill in the art will understand that monolithic three-dimensional memory arrays may include more or fewer than seventy-two non-volatile memory cells.
In an embodiment, each of non-volatile memory cells M111, M112, . . . , M436 includes a corresponding reversible resistance-switching memory element R111, R112, . . . , R436, respectively, coupled in series with a corresponding isolation element S111, S112, . . . , S436, respectively. For example, non-volatile memory cell M111 includes reversible resistance-switching memory element R111 coupled in series with isolation element S111, non-volatile memory cell M411 includes reversible resistance-switching memory element R411 coupled in series with isolation element S411, non-volatile memory cell M116 includes reversible resistance-switching memory element R116 coupled in series with isolation element S116, and so on.
Each reversible resistance-switching memory element R111, R112, . . . , R436 may include a single material layer or multiple material layers. In an embodiment, each reversible resistance-switching memory element R111, R112, . . . , R436 includes a barrier modulated switching structure that includes a semiconductor material layer 418 and a conductive oxide material layer 420. A barrier material layer (e.g., about 2 nm of Al2O3) (not shown) may be disposed between semiconductor material layer 418 and conductive oxide material layer 420.
In embodiments, semiconductor material layer 418 includes between about 3 nm and about 8 nm of one or more of amorphous silicon, amorphous tantalum nitride, amorphous tantalum silicon nitride, or other similar semiconductor material, and conductive oxide material layer 420 includes between about 6 nm and about 12 nm of one or more of crystalline titanium oxide, crystalline zinc oxide, crystalline tungsten oxide, crystalline strontium titanate, yttria-stabilized zirconia, crystalline praseodymium calcium manganese oxide, or other similar conductive oxide material. Other semiconductor materials and/or conductive oxide materials may be used. As described above, a BMC memory cell includes a barrier modulated switching structure.
In an embodiment, each of isolation elements S111, S112, . . . , S436, is an isolation element 300 of
In an embodiment, vertical bit lines LBL11-LBL33 are Cu, conductive material layer 422 is TiN, with a thickness of between about 10 nm and about 50 nm, semiconductor material 424 is a-silicon-germanium (α-SixGe1-x, with x between about 0.3 to about 0.7), with a thickness of between about 5 nm and about 15 nm, and barrier material 426 is TaN, with a thickness of between about 1 nm and about 5 nm. Although not shown in
In other embodiments, vertical bit lines LBL11-LBL33 may be one or more of Cu, Ag, Ni or other metal, semiconductor material 424 may be one or more of silicon, germanium, SixGe1-x or other similar semiconductor materials or low density oxides such as HfO2, SiOx, TiO2, WO, ZnO, or other similar low density oxides, conductive material layer 422 may be one or more of TiN, a conductive carbon, Pt, Ru, Pd, Ir, TiAlN, W, or other conductive material, and barrier material 426 may be one or more of Ti, Ta, TiN, TaN, WN, TaC, or other barrier layer material. For simplicity, the remaining description assumes that first electrode 302 is copper, second electrode 304 is TiN, semiconductor layer 306 is α-SixGe1-x, and barrier layer 308 is tantalum nitride.
Vertical bit lines LBL11-LBL33 are separated from one another by a fourth dielectric material layer 430 (e.g., silicon dioxide). In some embodiments, each of vertical bit lines LBL11-LBL33 includes a vertical structure (e.g., a rectangular prism, a cylinder, or a pillar), and semiconductor material 424 and barrier material 426 may completely or partially surround the vertical structure (e.g., a conformal layer of material surrounding the sides of the vertical structure).
Vertically-oriented bit line select transistors Q11-Q33 may be used to select a corresponding one of vertical bit lines LBL11-LBL33. Vertically-oriented bit line select transistors Q11-Q33 may be field effect transistors, although other transistors types may be used. Each of vertically-oriented bit line select transistors Q11-Q33 has a first terminal (e.g., a drain/source terminal), a second terminal (e.g., a source/drain terminal), a first control terminal (e.g., a first gate terminal) and a second control terminal (e.g., a second gate terminal).
The first gate terminal and the second gate terminal may be disposed on opposite sides of the vertically-oriented bit line select transistor. The first gate terminal may be used to selectively induce a first conductive channel between the first terminal and the second terminal of the transistor, and the second gate terminal may be used to selectively induce a second conductive channel between the first terminal and the second terminal of the transistor.
In an embodiment, the first gate terminal and the second gate terminal are coupled together to form a single control terminal that may be used to collectively turn ON and OFF the vertically-oriented bit line select transistor. Thus, the first gate terminal and the second gate terminal of each of vertically-oriented bit line select transistors Q11-Q33 may be used to select a corresponding one of vertical bit lines LBL11, LBL12, . . . , LBL33.
Without wanting to be bound by any particular theory, for each of vertically-oriented bit line select transistors Q11-Q33, it is believed that the current drive capability of the transistor may be increased by using both the first gate terminal and the second gate terminal to turn ON the transistor. For simplicity, the first and second gate terminal of each of select transistors Q11-Q33 will be referred to as a single gate terminal.
Referring to
Row select lines SG1, SG2, SG3 are used to turn ON/OFF vertically-oriented bit line select transistors Q11, Q12, Q13, respectively, to connect/disconnect vertical bit lines LBL11, LBL12, LBL13, respectively, to/from global bit line GBL1. A gate dielectric material layer 432 (e.g., silicon dioxide) is disposed between row select lines SG1, SG2, SG3 and vertically-oriented bit line select transistors Q11, Q12, Q13.
Likewise, vertically-oriented bit line select transistors Q11, Q21, . . . , Q33 are used to selectively connect/disconnect vertical bit lines LBL11, LBL21, LBL31 to global bit lines GBL1, GBL2, GBL3, respectively, using row select line SG1. In particular, each of vertically-oriented bit line select transistors Q11, Q21, Q31 has a first terminal (e.g., a drain/source terminal) coupled to a corresponding one of vertical bit lines LBL11, LBL21, LBL31, respectively, a second terminal (e.g., a source/drain terminal) coupled to a corresponding one of global bit lines GBL1, GBL2, GBL3, respectively, and a control terminal (e.g., a gate terminal) coupled to row select line SG1. Row select line SG1 is used to turn ON/OFF vertically-oriented bit line select transistors Q11, Q21, Q31 to connect/disconnect vertical bit lines LBL11, LBL23, LBL31, respectively, to/from global bit lines GBL1, GBL2, GBL3, respectively.
Similarly, vertically-oriented bit line select transistors Q13, Q23, Q33 are used to selectively connect/disconnect vertical bit lines LBL13, LBL23, LBL33 to/from global bit lines GBL1, GBL2, GBL3, respectively, using row select line SG3. In particular, each of vertically-oriented bit line select transistors Q13, Q23, Q33 has a first terminal (e.g., a drain/source terminal) coupled to a corresponding one of vertical bit lines LBL13, LBL23, LBL33, respectively, a second terminal (e.g., a source/drain terminal) coupled to a corresponding one of global bit lines GBL1, GBL2, GBL3, respectively, and a control terminal (e.g., a gate terminal) coupled to row select line SG3. Row select line SG3 is used to turn ON/OFF vertically-oriented bit line select transistors Q13, Q23, Q33 to connect/disconnect vertical bit lines LBL33, LBL23, LBL33, respectively, to/from global bit lines GBL1, GBL2, GBL3, respectively.
Referring now to FIGS. 5A1-5H3, an example method of forming a monolithic three-dimensional memory array, such as monolithic three-dimensional array 400 of
With reference to FIGS. 5A1-5A3, substrate 402 is shown as having already undergone several processing steps. Substrate 402 may be any suitable substrate such as a silicon, germanium, silicon-germanium, undoped, doped, bulk, silicon-on-insulator (“SOI”) or other substrate with or without additional circuitry. For example, substrate 402 may include one or more n-well or p-well regions (not shown). Isolation layer 404 is formed above substrate 402. In some embodiments, isolation layer 404 may be a layer of silicon dioxide, silicon nitride, silicon oxynitride or any other suitable insulating layer.
Following formation of isolation layer 404, a conductive material layer 406 is deposited over isolation layer 404. Conductive material layer 406 may include any suitable conductive material such as tungsten or another appropriate metal, heavily doped semiconductor material, a conductive silicide, a conductive silicide-germanide, a conductive germanide, or the like deposited by any suitable method (e.g., CVD, PVD, etc.). In at least one embodiment, conductive material layer 406 may comprise between about 20 nm and about 250 nm of tungsten. Other conductive material layers and/or thicknesses may be used. In some embodiments, an adhesion layer (not shown), such as titanium nitride or other similar adhesion layer material, may be disposed between isolation layer 404 and conductive material layer 406, and/or between conductive material layer 406 and subsequent vertically-oriented bit line select transistors layers.
Persons of ordinary skill in the art will understand that adhesion layers may be formed by PVD or another method on conductive material layers. For example, adhesion layers may be between about 2 nm and about 50 nm, and in some embodiments about 10 nm, of titanium nitride or another suitable adhesion layer such as tantalum nitride, tungsten nitride, tungsten, molybdenum, combinations of one or more adhesion layers, or the like. Other adhesion layer materials and/or thicknesses may be employed.
Following formation of conductive material layer 406, conductive material layer 406 is patterned and etched. For example, conductive material layer 406 may be patterned and etched using conventional lithography techniques, with a soft or hard mask, and wet or dry etch processing. In at least one embodiment, conductive material layer 406 is patterned and etched to form global bit lines GBL1, GBL2, GBL3. Example widths for global bit lines GBL1, GBL2, GBL3 and/or spacings between global bit lines GBL1, GBL2, GBL3 range between about 48 nm and about 100 nm, although other conductor widths and/or spacings may be used.
After global bit lines GBL1, GBL2, GBL3 have been formed, a first dielectric material layer 408 is formed over substrate 402 to fill the voids between global bit lines GBL1, GBL2, GBL3. For example, approximately 300-700 nm of silicon dioxide may be deposited on the substrate 402 and planarized using chemical mechanical polishing or an etchback process to form a planar surface 500. Other dielectric materials such as silicon nitride, silicon oxynitride, low K dielectrics, etc., and/or other dielectric material layer thicknesses may be used. Example low K dielectrics include carbon doped oxides, silicon carbon layers, or the like.
In other embodiments, global bit lines GBL1, GBL2, GBL3 may be formed using a damascene process in which first dielectric material layer 408 is formed, patterned and etched to create openings or voids for global bit lines GBL1, GBL2, GBL3. The openings or voids then may be filled with conductive layer 406 (and/or a conductive seed, conductive fill and/or barrier layer if needed). Conductive material layer 406 then may be planarized to form planar surface 500.
Following planarization, the semiconductor material used to form vertically-oriented bit line select transistors Q11-Q33 is formed over planarized top surface 500 of substrate 402. In some embodiments, each vertically-oriented bit line select transistor is formed from a polycrystalline semiconductor material such as polysilicon, an epitaxial growth silicon, a polycrystalline silicon-germanium alloy, polygermanium or any other suitable material. Alternatively, vertically-oriented bit line select transistors Q11-Q33 may be formed from a wide band-gap semiconductor material, such as ZnO, InGaZnO, or SiC, which may provide a high breakdown voltage, and typically may be used to provide junctionless FETs. Persons of ordinary skill in the art will understand that other materials may be used.
In some embodiments, each vertically-oriented bit line select transistor Q11-Q33 may include a first region (e.g., n+ polysilicon), a second region (e.g., p polysilicon) and a third region (e.g., n+ polysilicon) to form drain/source, body, and source/drain regions, respectively, of a vertical FET. For example, a heavily doped n+ polysilicon layer 502 may be deposited on planarized top surface 500. In some embodiments, n+ polysilicon layer 502 is in an amorphous state as deposited. In other embodiments, n+ polysilicon layer 502 is in a polycrystalline state as deposited. CVD or another suitable process may be employed to deposit n+ polysilicon layer 502.
In an embodiment, n+ polysilicon layer 502 may be formed, for example, from about 10 nm to about 50 nm, of phosphorus or arsenic doped silicon having a doping concentration of about 1021 cm−3. Other layer thicknesses, doping types and/or doping concentrations may be used. N+ polysilicon layer 502 may be doped in situ, for example, by flowing a donor gas during deposition. Other doping methods may be used (e.g., implantation).
After deposition of n+ silicon layer 502, a doped p-type silicon layer 504 may be formed over n+ polysilicon layer 502. P-type silicon may be either deposited and doped by ion implantation or may be doped in situ during deposition to form a p-type silicon layer 504. For example, an intrinsic silicon layer may be deposited on n+ polysilicon layer 502, and a blanket p-type implant may be employed to implant boron a predetermined depth within the intrinsic silicon layer. Example implantable molecular ions include BF2, BF3, B and the like. In some embodiments, an implant dose of about 1-10×1013 ions/cm2 may be employed. Other implant species and/or doses may be used. Further, in some embodiments, a diffusion process may be employed. In an embodiment, the resultant p-type silicon layer 504 has a thickness of from about 80 nm to about 400 nm, although other p-type silicon layer sizes may be used.
Following formation of p-type silicon layer 504, a heavily doped n+ polysilicon layer 506 is deposited on p-type silicon layer 504. In some embodiments, n+ polysilicon layer 506 is in an amorphous state as deposited. In other embodiments, n+ polysilicon layer 506 is in a polycrystalline state as deposited. CVD or another suitable process may be employed to deposit n+ polysilicon layer 506.
In an embodiment, n+ polysilicon layer 506 may be formed, for example, from about 10 nm to about 50 nm of phosphorus or arsenic doped silicon having a doping concentration of about 1021 cm−3. Other layer thicknesses, doping types and/or doping concentrations may be used. N+ polysilicon layer 506 may be doped in situ, for example, by flowing a donor gas during deposition. Other doping methods may be used (e.g., implantation). Persons of ordinary skill in the art will understand that silicon layers 502, 504 and 506 alternatively may be doped p+/n/p+, respectively, or may be doped with a single type of dopant to produce junctionless-FETs.
Following formation of n+ polysilicon layer 506, silicon layers 502, 504 and 506 are patterned and etched to form vertical transistor pillars. For example, silicon layers 502, 504 and 506 may be patterned and etched using conventional lithography techniques, with wet or dry etch processing. In an embodiment, silicon layers 502, 504 and 506 are patterned and etched to form vertical transistor pillars disposed above global bit lines GBL1, GBL2, GBL3. The vertical transistor pillars will be used to form vertically-oriented bit line select transistors Q11-Q33.
Silicon layers 502, 504 and 506 may be patterned and etched in a single pattern/etch procedure or using separate pattern/etch steps. Any suitable masking and etching process may be used to form vertical transistor pillars . For example, silicon layers may be patterned with about 1 to about 1.5 micron, more preferably about 1.2 to about 1.4 micron, of photoresist (“PR”) using standard photolithographic techniques. Thinner PR layers may be used with smaller critical dimensions and technology nodes. In some embodiments, an oxide hard mask may be used below the PR layer to improve pattern transfer and protect underlying layers during etching.
In some embodiments, after etching, the vertical transistor pillars may be cleaned using a dilute hydrofluoric/sulfuric acid clean. Such cleaning may be performed in any suitable cleaning tool, such as a Raider tool, available from Semitool of Kalispell, Mont. Example post-etch cleaning may include using ultra-dilute sulfuric acid (e.g., about 1.5 1.8 wt %) for about 60 seconds and/or ultra-dilute hydrofluoric (“HF”) acid (e.g., about 0.4-0.6 wt %) for 60 seconds. Megasonics may or may not be used. Other clean chemistries, times and/or techniques may be employed.
A gate dielectric material layer 432 is deposited conformally over substrate 402, and forms on sidewalls of the vertical transistor pillars. For example, between about 3 nm to about 10 nm of silicon dioxide may be deposited. Other dielectric materials such as silicon nitride, silicon oxynitride, low K dielectrics, etc., and/or other dielectric material layer thicknesses may be used.
Gate electrode material is deposited over the vertical transistor pillars and gate dielectric material layer 432 to fill the voids between the vertical transistor pillars. For example, approximately 10 nm to about 20 nm of titanium nitride or other similar metal, a highly-doped semiconductor, such as n+ polysilicon, p+ polysilicon, or other similar conductive material may be deposited. The as-deposited gate electrode material is subsequently etched back to form row select lines SG1, SG2, SG3.
A second dielectric material layer 410 is deposited over substrate 402. For example, approximately 500 nm to about 800 nm of silicon dioxide may be deposited and planarized using chemical mechanical polishing or an etch-back process to form planar top surface 508, resulting in the structure shown in FIGS. 5A1-5A3. Other dielectric materials and/or thicknesses may be used.
Planar surface 508 includes exposed top surfaces of vertically-oriented bit line select transistors Q11-Q33 and gate dielectric material layer 432 separated by second dielectric material layer 410. Other dielectric materials such as silicon nitride, silicon oxynitride, low K dielectrics, etc., and/or other dielectric material layer thicknesses may be used. Example low K dielectrics include carbon doped oxides, silicon carbon layers, or the like.
Next, a first etch stop layer 412 is formed over substrate 402. First etch stop layer 412 may include any suitable etch stop layer formed by any suitable method (e.g., CVD, PVD, etc.). In an embodiment, first etch stop layer 412 may include between about 5 nm and about 50 nm of silicon nitride. Other etch stop layer materials and/or thicknesses may be used.
Alternating layers of third dielectric material layer 414 and a conductive material layer 510 are formed over substrate 402. In an embodiment, each third dielectric material layer 414 may be between about 20 nm and about 50 nm of SiO2, each conductive material layer 510 may be between about 25 nm and about 40 nm of TiN. Other dielectric materials and/or thicknesses, other conductive materials and/or thicknesses may be used. In an embodiment, four conductive material layers 510 are formed over substrate 402. More or fewer than four conductive material layers 510 may be used.
Next, a second etch stop layer 512 is formed over substrate 402, resulting in the structure shown in FIGS. 5B1-5B2. Second etch stop layer 512 may include any suitable etch stop layer formed by any suitable method (e.g., CVD, PVD, etc.). In an embodiment, second etch stop layer 512 may comprise between about 5 nm and about 50 nm of silicon nitride. Other etch stop layer materials and/or thicknesses may be used.
Next, second etch stop layer 512, third dielectric material layers 414, and conductive material layers 510 are patterned and etched to form rows 514 of multi-layer word lines WL10, WL11, . . . , WL43, resulting in the structure shown in
Next, an etch is performed to form voids 516 at ends of conductive material layers 510, resulting in the structure shown in FIGS. 5D1-5D2. Each of voids 516 may have a depth D of between about 10 nm and about 20 nm, although other depths may be used.
A semiconductor material layer 418, a conductive oxide material layer 420, and a conductive material layer 422 are deposited conformally over rows 514, filling voids 516. In an embodiment, semiconductor material layer 418 is between about 3 nm and about 8 nm of amorphous silicon, conductive oxide material layer 420 is between about 6 nm and about 12 nm of TiO2, and conductive material layer 422 between about 5 nm and about 20 nm of TiN. Other materials and/or thicknesses may be used. A barrier material layer (e.g., between about 0.5 nm to about 2 nm of Al2O3) may be disposed between semiconductor material layer 418 and conductive oxide material layer 420.
An anisotropic etch is used to remove lateral portions of semiconductor material layer 418, conductive oxide material layer 420, and conductive material layer 422, leaving only sidewall portions of semiconductor material layer 418, conductive oxide material layer 420, and conductive material layer 422 in voids 516, resulting in the structure shown in FIG. 5E1-5E2.
A semiconductor material 424 and a barrier material 426 are deposited conformally over rows 514. In an embodiment, semiconductor material 424 is between about 5 nm and about 15 nm of α-silicon-germanium (α-SixGe1-x, with x between about 0.3 to about 0.7), and barrier material 426 is between about 1 nm and about 5 nm TaN. Other and/or thicknesses may be used.
An anisotropic etch is used to remove lateral portions of semiconductor material 424 and a barrier material 426, leaving only sidewall portions of semiconductor material 424 and a barrier material 426, resulting in the structure shown in FIG. 5F1-5F2.
First etch stop layer 316 is patterned and etched to form cavities 518 and expose top surfaces of bit line select transistors Q11-Q31, resulting in the structure shown in FIGS. 4G1-4G2.
A conductive material 428 is deposited over substrate 402. In an embodiment, conductive material layer 428 is between about 10 nm and about 50 nm of Cu deposited by any suitable method (e.g., CVD, PVD, etc.). Other conductive materials and/or thicknesses may be used.
Semiconductor material layer 418, conductive oxide material layer 420, conductive material layer 422, semiconductor material 42, barrier material 426 and conductive material 428 are then patterned and etched to form vertical bit lines LBL11-LBL33, and strips of semiconductor material layer 418, conductive oxide material layer 420, conductive material layer 422, semiconductor material 424 and barrier material 426.
A dielectric material 430, such as silicon dioxide, may then be deposited over substrate 402, filling the voids between vertical bit lines LBL11-LBL33, and then planarized using chemical mechanical polishing or an etch-back process, resulting in the structure shown in FIGS. 5H1-5H3.
Thus, as described above, one embodiment of the disclosed technology includes a method that includes forming a bit line above a substrate; forming a word line above the substrate, and forming a non-volatile memory cell between the bit line and the word line. The non-volatile memory cell includes a non-volatile memory material coupled in series with an isolation element. The isolation element includes a first electrode, a second electrode, and a semiconductor layer and a barrier layer disposed between the first electrode and the second electrode.
One embodiment of the disclosed technology includes a method including forming a bit line disposed in a first direction above a substrate, forming a word line disposed in a second direction above the substrate, the second direction perpendicular to the first direction, forming a void at an end of the word line, and forming a non-volatile memory cell at an intersection of the bit line and the word line. Forming the non-volatile memory cell includes forming a non-volatile memory material in the void, and forming an isolation element adjacent the non-volatile memory material. The isolation element includes a first electrode, a second electrode, and a semiconductor layer and a barrier layer disposed between the first electrode and the second electrode.
One embodiment of the disclosed technology includes a method that includes forming an isolation element by forming a first electrode above a substrate, forming a semiconductor layer above the first electrode, forming a barrier layer above the semiconductor layer, and forming a second electrode above the barrier layer. The method further includes applying a voltage bias to the first electrode while applying one or more voltage pulses to the second electrode until the isolation element conducts a desired current. The isolation element has an ON-state current density of greater than about 1-5 MA/cm2, an OFF-state leakage current of less than about 10-20 nA@1V, and an ON/OFF current ratio of greater than about 500.
For purposes of this document, each process associated with the disclosed technology may be performed continuously and by one or more computing devices. Each step in a process may be performed by the same or different computing devices as those used in other steps, and each step need not necessarily be performed by a single computing device.
For purposes of this document, reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “another embodiment” may be used to described different embodiments and do not necessarily refer to the same embodiment.
For purposes of this document, a connection can be a direct connection or an indirect connection (e.g., via another part).
For purposes of this document, the term “set” of objects may refer to a “set” of one or more of the objects.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.
