Patent Application
20250112145
This disclosure relates generally to integrated circuits and, more particularly, to methods and apparatus to improve interconnect structures in integrated circuit packages.
In many integrated circuit (IC) packages, one or more semiconductor dies are mechanically and electrically coupled to an underlying package substrate. During an IC fabrication process, devices (e.g., transistors, capacitors, etc.) within the semiconductor die are interconnected. Further, the die is typically mounted to a package substrate that enables the die to be connected to a printed circuit board and/or other electrical components. As integrated circuit (IC) chips and/or dies reduce in size and interconnect densities increase, alternatives to traditional interconnects within the dies themselves as well interconnects within package substrates supporting such dies are needed for providing stable transmission of high frequency data signals between different circuitry and/or increased power delivery.
In general, the same reference numbers will be used throughout the drawing(s) and accompanying written description to refer to the same or like parts. The figures are not necessarily to scale. Instead, the thickness of the layers or regions may be enlarged in the drawings. Although the figures show layers and regions with clean lines and boundaries, some or all of these lines and/or boundaries may be idealized. In reality, the boundaries and/or lines may be unobservable, blended, and/or irregular.
As used herein, unless otherwise stated, the term “above” describes the relationship of two parts relative to Earth. A first part is above a second part, if the second part has at least one part between Earth and the first part. Likewise, as used herein, a first part is “below” a second part when the first part is closer to the Earth than the second part. As noted above, a first part can be above or below a second part with one or more of: other parts therebetween, without other parts therebetween, with the first and second parts touching, or without the first and second parts being in direct contact with one another.
Notwithstanding the foregoing, in the case of referencing a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and/or an integrated circuit (IC) package containing a semiconductor die during fabrication or manufacturing, “above” is not with reference to Earth, but instead is with reference to an underlying substrate on which relevant components are fabricated, assembled, mounted, supported, or otherwise provided. Thus, as used herein and unless otherwise stated or implied from the context, a first component within a semiconductor die (e.g., a transistor or other semiconductor device) is “above” a second component within the semiconductor die when the first component is farther away from a substrate (e.g., a semiconductor wafer) during fabrication/manufacturing than the second component on which the two components are fabricated or otherwise provided. Similarly, unless otherwise stated or implied from the context, a first component within an IC package (e.g., a semiconductor die) is “above” a second component within the IC package during fabrication when the first component is farther away from a printed circuit board (PCB) to which the IC package is to be mounted or attached. It is to be understood that semiconductor devices are often used in orientation different than their orientation during fabrication. Thus, when referring to a semiconductor device (e.g., a transistor), a semiconductor die containing a semiconductor device, and/or an integrated circuit (IC) package containing a semiconductor die during use, the definition of “above” in the preceding paragraph (i.e., the term “above” describes the relationship of two parts relative to Earth) will likely govern based on the usage context.
As used in this patent, stating that any part (e.g., a layer, film, area, region, or plate) is in any way on (e.g., positioned on, located on, disposed on, or formed on, etc.) another part, indicates that the referenced part is either in contact with the other part, or that the referenced part is above the other part with one or more intermediate part(s) located therebetween.
As used herein, connection references (e.g., attached, coupled, connected, and joined) may include intermediate members between the elements referenced by the connection reference and/or relative movement between those elements unless otherwise indicated. As such, connection references do not necessarily infer that two elements are directly connected and/or in fixed relation to each other. As used herein, stating that any part is in “contact” with another part is defined to mean that there is no intermediate part between the two parts.
Unless specifically stated otherwise, descriptors such as “first,” “second,” “third,” etc., are used herein without imputing or otherwise indicating any meaning of priority, physical order, arrangement in a list, and/or ordering in any way, but are merely used as labels and/or arbitrary names to distinguish elements for ease of understanding the disclosed examples. In some examples, the descriptor “first” may be used to refer to an element in the detailed description, while the same element may be referred to in a claim with a different descriptor such as “second” or “third.” In such instances, it should be understood that such descriptors are used merely for identifying those elements distinctly within the context of the discussion (e.g., within a claim) in which the elements might, for example, otherwise share a same name.
As used herein, “approximately” and “about” modify their subjects/values to recognize the potential presence of variations that occur in real world applications. For example, “approximately” and “about” may modify dimensions that may not be exact due to manufacturing tolerances and/or other real world imperfections as will be understood by persons of ordinary skill in the art. For example, “approximately” and “about” may indicate such dimensions may be within a tolerance range of +/−10% unless otherwise specified in the below description.
As used herein “substantially real time” refers to occurrence in a near instantaneous manner recognizing there may be real world delays for computing time, transmission, etc. Thus, unless otherwise specified, “substantially real time” refers to real time+1 second.
As used herein, “substantially vertically” or “substantially perpendicular” means perfectly vertical or perpendicular or within +/−5 degrees of perfectly vertical or perpendicular. As used herein, “substantially horizontally” or “substantially parallel” means perfectly parallel or horizontal or within +/−5 degrees of perfectly horizontal or parallel.
As used herein, the phrase “in communication,” including variations thereof, encompasses direct communication and/or indirect communication through one or more intermediary components, and does not require direct physical (e.g., wired) communication and/or constant communication, but rather additionally includes selective communication at periodic intervals, scheduled intervals, aperiodic intervals, and/or one-time events.
As used herein, “programmable circuitry” is defined to include (i) one or more special purpose electrical circuits (e.g., an application specific circuit (ASIC)) structured to perform specific operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), and/or (ii) one or more general purpose semiconductor-based electrical circuits programmable with instructions to perform specific functions(s) and/or operation(s) and including one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuitry include programmable microprocessors such as Central Processor Units (CPUs) that may execute first instructions to perform one or more operations and/or functions, Field Programmable Gate Arrays (FPGAs) that may be programmed with second instructions to cause configuration and/or structuring of the FPGAs to instantiate one or more operations and/or functions corresponding to the first instructions, Graphics Processor Units (GPUs) that may execute first instructions to perform one or more operations and/or functions, Digital Signal Processors (DSPs) that may execute first instructions to perform one or more operations and/or functions, XPUs, Network Processing Units (NPUs) one or more microcontrollers that may execute first instructions to perform one or more operations and/or functions and/or integrated circuits such as Application Specific Integrated Circuits (ASICs). For example, an XPU may be implemented by a heterogeneous computing system including multiple types of programmable circuitry (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and/or any combination(s) thereof), and orchestration technology (e.g., application programming interface(s) (API(s)) that may assign computing task(s) to whichever one(s) of the multiple types of programmable circuitry is/are suited and available to perform the computing task(s).
As used herein integrated circuit/circuitry is defined as one or more semiconductor packages containing one or more circuit elements such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit may be implemented as one or more of an ASIC, an FPGA, a chip, a microchip, programmable circuitry, a semiconductor substrate coupling multiple circuit elements, a system on chip (SoC), etc.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from devices (e.g., transistors, etc.) of a semiconductor die through one or more interconnect layers. Typically, the interconnect layers include an insulating or dielectric material disposed between the interconnect structures. For example, the interconnect structures can include conductive material (e.g., lithographically patterned) defining traces, pads, and the like in metal layers between adjacent dielectric layers. Further, the interconnect structures can include conductive vias traversing through the dielectric layers to electrically couple different ones of the metal layers. The traces and associated vias define electrical wiring (e.g., signaling lines) to transfer signals or information between various components (e.g., transistors, capacitors, resistors, backend layers, etc. and/or other circuitry) of the semiconductor package and/or power traces for transferring or carrying power to the various components of the semiconductor package. The interconnect structures are arranged to route the electrical signals according to a wide variety of designs.
In low-loss, high bandwidth, high density interconnect substrates, increased power delivery and signaling requirements require dense signaling process areas. As electronic systems become more complex and electrical interfaces in the electrical systems operate at higher frequencies, dense signal processing areas can cause significant crosstalk or unwanted signal cross-over between adjacent signal paths in such densely packed spaces. For example, crosstalk may be noise induced by one signal that interferes with another signal, which reduces the performance of an IC package (e.g., within the semiconductor die in the IC package and/or within a package substrate of the IC package). Crosstalk between conductive layers of the IC package (e.g., within a die and/or within a package substrate supporting the die) can limit the bandwidth of data that can be transmitted through the IC package.
An amount of crosstalk between the interconnects is at least partially dependent on a dielectric material (e.g., inter-metal dielectric) used in the dielectric layers. Each dielectric material is associated with a dielectric constant (k) or relative permittivity (ε). As used herein, a material's k-value refers to a dielectric constant(s) associated with that material. In some examples, a relatively high dielectric constant (k) (e.g., a dielectric constant above 2) is associated with higher capacitive coupling between interconnect structures and, consequently, increased levels of crosstalk. Thus, inter-metal dielectric materials are often selected for low capacitance to improve signal routing. Efforts to reduce a dielectric constant of a dielectric filling in spaces between interconnect structures is important for increasing signal bandwidth for a dense bundle of traces by reducing crosstalk between the traces.
Typically filled and/or unfilled organic dielectric materials are used for wafer-level and panel-level packaging (e.g., a substrate package(s), an organic interposer(s), a redistribution layer(s) (RDL), etc.). In many instances, polymer dielectric materials are used during signal routing, some of which are filled with silica to adjust the mechanical properties of the polymer dielectric material. Silica-filled dielectric materials are associated with dielectric constants ranging from approximately 2.0 to 3.4. When used as an inter-metal dielectric, certain dielectric materials result in undesired levels of metal capacitive coupling and crosstalk issues. For filled dielectric materials, such as dry and liquid buildup films, a major contributor to its dielectric constant is the silica (also known as silicon dioxide) filler. This is in part because silicon is associated with a relatively high dielectric constant. For example, silicon dioxide (SiO2) is a common dielectric, and has a dielectric constant of approximately 3.9. In some examples, hollow fillers are used to lower the dielectric constant associated with these films. However, buildup films having hollow fillers cause concerns regarding filler reliability. For example, the fillers can crack. In some examples, the hollow cavity inside can collapse due to mechanical stresses and/or pressure during manufacturing and/or use.
Unfilled dielectric materials are associated with dielectric constants ranging from approximately 2.5 to 3.0. For example, polyimide-based (PI-based) dielectrics are associated with dielectric constants ranging from approximately 2.8 to 3.0. To lower the dielectric constants further, fluorinated monomers can be used to create the polymers. This may lower the dielectric constants to approximately 2.0 to 2.3. However, unfilled organic materials are typically associated with a high coefficient of thermal expansion (CTE). For example, a CTE for unfilled organic materials is approximately 2.5 times to 4 times higher than for copper. This mismatch between the interconnect structures (typically made of copper) and the dielectric material causes significant stresses at low copper density vias, necessitating large vias to survive repeated thermal stresses (e.g., thermal cycling) without cracking or otherwise being disconnected from the interconnect structure(s) below and/or above (e.g., typically the via bottom cracks due to the tapered nature of vias in PI-based dielectrics). Fluorinating the organic dielectric leads to larger issues as the CTE typically grows. For instance, a fluorinated material such as Teflon is associated with a CTE larger than 100 parts per million (ppm) per degree Celsius (C) (ppm/° C.). Further, adhesion properties of the polymer typically degrade with the degree of fluorination.
In some examples, carbon-doped oxides (CDO) or dielectrics with a given porosity are used to reduce a dielectric constant of an inter-metal dielectric. For example, CDO materials can be used in semiconductor damascene interconnects, such as used in silicon interposers or silicon bridges, to obtain a lower dielectric constant. In some examples, CDOs or dielectrics with a given porosity are used, which are associated with a dielectric constant of approximately 2.6. However, such dielectric constants are relatively high (e.g., greater than 2), resulting in undesired levels of parasitic capacitance and crosstalk.
A vacuum provides a substantially lower dielectric constant, closely followed by air, which is associated with a dielectric constant of approximately 1. In some examples, process integration schemes for dual-damascene interconnects allow for the generation of pockets of air or airgaps (also referred to herein as voids, trenches, and openings) between adjacent interconnect structures to reduce a dielectric constant between the interconnect structures. However, these processes cannot be used for die-to-die (D2D) or Tile-to-Tile (e.g., Chiplet-to-Chiplet) interconnects. Further, creating an air-gap dielectric using dual-damascene processing is expensive as it requires additional process steps, masks, barrier layers, and cure steps as well as sacrificial materials. Moreover, the placement of air gaps compromises the mechanical stability of the integrated circuit making it impractical to build an IC composed substantially or entirely of air as the insulating material.
As integrated circuit (IC) chips and/or dies reduce in size and interconnect densities increase, alternatives to traditional dielectric materials are needed for providing stable transmission of high frequency data signals between different circuitry and/or increased power delivery.
Example dielectric structures and methods of manufacturing the same are disclosed herein. Examples disclosed herein enable a dielectric structure having a relatively low dielectric constant (e.g., a dielectric constant less than approximately 2). Example dielectric structures disclosed herein include a first dielectric material that surrounds or otherwise encloses a second dielectric material. The first dielectric material is associated with a first dielectric constant that is higher than a second dielectric material associated with the second dielectric material. In some examples, the second dielectric material is air. In particular, examples disclosed herein enable fabrication of a dielectric structure having an airgap. By combining this airgap with the first dielectric material, the example dielectric structure disclosed herein is associated with a dielectric constant that is lower relative to that of a space filled with the first dielectric material.
Example dielectric structures disclosed herein include airgaps that are enclosed by the first dielectric material. In particular, after a planarization process and/or an etching process (e.g., to reveal a via) of a dielectric layer containing such dielectric structures, the resulting (e.g., exposed) exterior surfaces of the dielectric layer remain closed off such that the airgaps remain contained in (e.g., surrounded by) the material of the dielectric layer. As such, a subsequent layer can be processed directly onto the dielectric layer containing the airgaps without the need for additional hard-masks, barriers, curing, and/or outgassing. In other words, examples disclosed herein enable stacking two or more layers having airgaps no more costly or complex than creating layers without airgaps.
Example dielectric structures disclosed herein can be integrated between metal lines (e.g., traces) to reduce cross and/or capacitive coupling. In particular, disclosed examples enable fabrication of example dielectric structures between adjacent interconnect structures. Certain examples enable an increase of bandwidth provided by a semiconductor die and/or an IC device.
Example dielectric structures disclosed herein can be used adjacent to or on a glass core to enable highest signaling per line applications and/or lowest losses for critical interconnects. For high speed input/output (HSIO) interconnects, example interconnect structures do not need to be roughened to achieve good adhesion to the solid-state dielectric material of example dielectric structures disclosed herein. This further increases or improves bandwidth advantage of these interconnect structures, especially when compared to current redistribution layers (e.g., current wafer-level package solutions).
Example dielectric structures disclosed herein are compatible with hybrid bonding processes. This is an advantage with respect to currently used organic interposers or interconnect layers that degrade significantly when exposed to prolonged temperatures required for hybrid bonding.
Example dielectric structures disclosed herein reduce or eliminate copper migration issues because ion migration paths are reduced due to the presence of the airgap. Examples disclosed herein enable cost efficient dielectric structures, even for dielectric layers in the 4-10 μm thick (e.g., for high density high-bandwidth D2D or Tile-2-Tile interconnectivity). Examples disclosed herein can be utilized in HSIO signaling using approximately 40 μm thick dielectric layers (e.g., 15 μm trace, 25 μm via, etc.).
In some examples, the die 102 may include and/or implement a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive-bridging RAM (CBRAM) device, etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuitry. Multiple ones of these devices may be combined on a single die 102. For example, a memory array formed by multiple memory circuits may be formed on a same die 102 as programmable circuitry (e.g., the processor circuitry 1602 of
The IC device 200 may include a device layer(s) 204 disposed on or above the die substrate 202. The device layer 204 may include features of one or more transistors 240 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 202. The device layer 204 may include, for example, one or more source and/or drain (S/D) regions 220, a gate 222 to control current flow between the S/D regions 220, and one or more S/D contacts 224 to route electrical signals to/from the S/D regions 220. The transistors 240 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 240 are not limited to the type and configuration depicted in
Each transistor 240 may include a gate 222 formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material. The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some examples, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 240 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer. For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
In some examples, when viewed as a cross-section of the transistor 240 along the source-channel-drain direction, the gate electrode may include a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate 202 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 202. In other examples, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate 202 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 202. In other examples, the gate electrode may include a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may include one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some examples, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some examples, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
The S/D regions 220 may be formed within the die substrate 202 adjacent to the gate 222 of each transistor 240. The S/D regions 220 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate 202 to form the S/D regions 220. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate 202 may follow the ion-implantation process. In the latter process, the die substrate 202 may first be etched to form recesses at the locations of the S/D regions 220. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 220. In some implementations, the S/D regions 220 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some examples, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some examples, the S/D regions 220 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further examples, one or more layers of metal and/or metal alloys may be used to form the S/D regions 220.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 240) of the device layer 204 through one or more interconnect layers disposed on the device layer 204 (illustrated in
The interconnect structures 228 may be arranged within the interconnect layers 206-210 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 228 depicted in
In some examples, the interconnect structures 228 may include traces 228a (e.g., lines, interconnect wires, metal layers, etc.) and/or vias 228b (e.g., conductive vias, electrical vias, etc.). The traces 228a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate 202 upon which the device layer 204 is formed. For example, the traces 228a may route electrical signals in a direction in and out of the page from the perspective of
The interconnect layers 206-210 may include a dielectric material 226 (e.g., an inter-metal dielectric material) disposed between the interconnect structures 228, as shown in
A first interconnect layer 206 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 204. In some examples, the first interconnect layer 206 may include traces 228a and/or vias 228b, as shown. The traces 228a of the first interconnect layer 206 may be coupled with contacts (e.g., the S/D contacts 224) of the device layer 204.
A second interconnect layer 208 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 206. In some examples, the second interconnect layer 208 may include vias 228b to couple the traces 228a of the second interconnect layer 208 with the traces 228a of the first interconnect layer 206. Although the traces 228a and the vias 228b are structurally delineated with a line within each interconnect layer (e.g., within the second interconnect layer 208) for the sake of clarity, the traces 228a and the vias 228b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some examples.
A third interconnect layer 210 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 208 according to similar techniques and configurations described in connection with the second interconnect layer 208 or the first interconnect layer 206. In some examples, the interconnect layers that are “higher up” in the metallization stack 219 in the IC device 200 (i.e., further away from the device layer 204) may be thicker.
The IC device 200 may include a solder resist material 234 (e.g., polyimide or similar material) and one or more conductive contacts 236 formed on the interconnect layers 206-210. In
The IC package 300 may include a die 306 coupled to the package substrate 302 via conductive contacts 304 of the die 306, first-level interconnects 308, and conductive contacts 310 of the package substrate 302. The conductive contacts 310 may be coupled to conductive pathways 312 through the package substrate 302, allowing circuitry within the die 306 to electrically couple to various ones of the conductive contacts 314 or to other devices included in the package substrate 302, not shown. The first-level interconnects 308 illustrated in
In some examples, an underfill material 316 may be disposed between the die 306 and the package substrate 302 around the first-level interconnects 308, and a mold compound 318 may be disposed around the die 306 and in contact with the package substrate 302. In some examples, the underfill material 316 may be the same as the mold compound 318. Example materials that may be used for the underfill material 316 and the mold compound 318 are epoxy mold materials, as suitable. Second-level interconnects 320 may be coupled to the conductive contacts 314. The second-level interconnects 320 illustrated in
In
The die 306 may take the form of any of the examples of dies discussed herein (e.g., may include any of the examples of the die 102, the IC device 200, etc.). In some examples, the IC package 300 includes example dielectric structure(s) associated with airgap(s) between interconnect structures as discussed further herein. In some examples, the dielectric structures are implemented in the example die 306 of the IC package 300. For example, the die 306 can include one or more of the interconnect layers having interconnect structures (e.g., electrical routing) with example dielectric structures associated with airgaps disposed between different conductive traces and/or vias as discussed further herein. Additionally or alternatively, in some examples, the dielectric structures are implemented in the package substrate 302 of the example IC package 300. For example, the package substrate 302 can include conductive layers defining electrical routing (e.g., traces) interconnected by vias extending between different conductive layers to define the pathways 312 with example dielectric structures associated with airgaps disposed between different the traces and/or vias as discussed further herein.
Although a single die 306 is illustrated in the IC package 300 of
In some examples, the circuit board 402 may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 402. In other examples, the circuit board 402 may be a non-PCB substrate.
The IC device assembly 400 illustrated in
The package-on-interposer structure 436 may include an IC package 420 coupled to an interposer 404 by coupling components 418. The coupling components 418 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 416. Although a single IC package 420 is shown in
In some examples, the interposer 404 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some examples, the interposer 404 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some examples, the interposer 404 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 404 may include metal interconnects 408 and vias 410, including but not limited to through-silicon vias (TSVs) 406. The dielectric material may be selected to prevent or otherwise reduce electrical coupling between ones of the metal interconnect 408, the TSVs 406, and/or the vias 410. In some examples, the dielectric material in one or more of the includes example dielectric structures associated with airgaps as discussed further herein. In some examples, the dielectric structures and associated air gaps are positioned between adjacent ones of the metal interconnect 408, the TSVs 406, and/or the vias 410.
The interposer 404 may further include embedded devices 414, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 404. The package-on-interposer structure 436 may take the form of any of the package-on-interposer structures known in the art.
The IC device assembly 400 may include an IC package 424 coupled to the first face 440 of the circuit board 402 by coupling components 422. The coupling components 422 may take the form of any of the examples discussed above with reference to the coupling components 416, and the IC package 424 may take the form of any of the examples discussed above (e.g., the IC package 300 of
The IC device assembly 400 illustrated in
Many of the components of the example IC device 500 of
The first interconnect layer 504 is disposed on a first surface 506 of an example first (e.g., lower) portion 508 (e.g., an underlying substrate) of the IC device 500. In some examples, the first portion 508 includes a carrier (e.g., a silicon or glass wafer or panel). In some examples, the first portion 508 includes a core (e.g., a glass core, an organic core, etc.) of a package substrate (e.g., the package substrate 302 of
The first interconnect layer 504 of the illustrated example includes a first insulation or dielectric material 510 and interconnect structures 512 (e.g., lithographically patterned conductive material). Specifically, the interconnect structures 512 are positioned on and extend from the first surface 506 of the first portion 508 of the IC device 500. In some examples, the interconnect structures 512 are manufactured using a semi additive processing (SAP).
The interconnect structures 512 are arranged to electrically connect components of the IC device 500 and/or components coupled to the IC device 500. In particular, the interconnect structures 512 include plurality of example traces (e.g., lines) 514 and example electrically conductive vias 516 (e.g., a self-aligned via(s), a zero-misaligned via(s), a via-on-pad(s), etc.). In some examples, one or more of the interconnect structures 512 are electrically coupled to other interconnect structures (e.g., traces, vias, etc.) in the first portion 508 of the IC device 500. Such interconnect structures in the first portion 508 have been omitted in
The traces 514 define signal traces (e.g., signaling lines) to transfer signals or information between various components (e.g., transistors, capacitors, resistors, backend layers, etc. and/or other circuitry) and/or power traces for transferring or carrying power to the various components. The vias 516 (e.g., copper plated vias) extend through the first dielectric material 510 within the first interconnect layer 504 to electrically interconnect adjacent interconnect structures (e.g., in upper and/or lower interconnect layers). The interconnect structures 512 can include copper, gold, aluminum and/or any other electrically conductive material(s). Although a particular number of interconnect structures 512 is depicted in
In this example, each interconnect structure 512 of
As illustrated in
The vias 516 extend between two or more adjacent metal layers. The vias 516 include the conductive material 520 within an aperture (e.g., a through hole) generated within the first dielectric material 510. In particular, the vias are filled or plated with the electrically conductive material 520 along a longitudinal length of the aperture. In some examples, the conductive material 520 of one or more of the vias 516 is the same conductive material 520 as one or more of the traces 514. In some examples, the conductive material 520 of one or more of the vias 516 is a different conductive material 520 from one or more of the traces 514. The conductive material 520 within the vias 516 define example via wall(s) 530 formed of an electrically conductive material 520. In other words, the vias 516 extend through the first dielectric material 510 and electrically interconnect conductive layers of the IC device 500. Thus, the first dielectric material 510 surrounds the via wall(s) 530 of the vias 516.
In the illustrated example of
The interconnect structures 512 are associated with outer (e.g., exterior, etc.) surfaces 534. In this example, the outer surfaces 534 correspond to the barrier material 532. The outer surfaces 534 are those surfaces not disposed on the first surface 506 of the first portion 508 and/or a second (e.g., upper) surface 536 of the first interconnect layer 504. In other examples, such as those in which the barrier material 532 is omitted, the outer surfaces 534 may correspond to one or more walls 522, 524, 526 of the traces 514 and/or the via walls 530 of the via 516. As illustrated in
As illustrated in
An example second dielectric material 542 is disposed within the trench 540. In particular, in some examples, air is disposed within the trench 540. In other words, the dielectric structures 502 includes airgaps defined by the first dielectric material 510 and the trenches 540 within the first dielectric material 510. In some examples, a different gas other than air is disposed within the trench 540. In some examples, the trench 540 has a pressure less than atmospheric pressure (e.g., a vacuum, under-pressured, etc.). Stated generally, the trench 540 is substantially devoid of solid matter. As used herein, substantially devoid means at least 99% devoid of solid matter.
In some examples, the trenches 540 extend to a height at least as great or greater than a height 544 of the traces 514 (e.g., a height of the first and/or second walls 522, 524). In other examples, the trenches 540 may have a height less than the height of the traces 514. In some examples, the trench 540 is elongate and has a length (into and out of the drawing from the perspective of
As illustrated in
The second interconnect layer 602 of the illustrated example is similar to the first interconnect layer 504. In particular, the second interconnect layer 602 includes interconnect structures 512, including example traces 514 and example vias 516, as well as example dielectric structures 502 in accordance with teachings disclosed herein. However, examples disclosed herein are not limited thereto. Rather, the first interconnect layer 504 and/or the second interconnect layer 602 may be arranged according to a wide variety of designs (in particular, the arrangement is not limited to the particular configurations of depicted in
The second interconnect layer 602 includes the example dielectric structures 502 positioned within spaces 538 between the interconnect structures 512. As illustrated in
Although the interconnect structures 512 and the trenches 540 in the different layers 504, 602 of
An example dielectric structure 502 disclosed herein is positioned in a space 538 between the first trace 514a and the second trace 514b. As discussed above, the dielectric structure 502 includes a trench 540 enclosed by the first dielectric material 510. The material properties of the first dielectric material 510 and a second dielectric material 542 (which, in some cases, is air) disposed within the trench 540 define a dielectric constant of the dielectric structure 502. In other words, a combination of the first dielectric material 510 and a second dielectric material 542 result in dielectric constant for dielectric structure 502 provided between the first and second traces 514a, 514b that is different than the dielectric constant for either of the first or second dielectric materials 510, 542 individually.
As illustrated in
The base 706 of the dielectric structure 502 can have a rectangular shape and/or any other shape. In some examples, the base 706 can be larger or smaller than shown in the illustrated example of
As illustrated in
As illustrated, each trace 514c, 514d in
Each trace 514 of
The dielectric structure 502 is formed of a solid-state dielectric material (e.g., the first dielectric material 510, the third dielectric material 802, and/or another dielectric material) and a trench 540 positioned therein. The trench 540 includes a width defined by second distance (d2) 904 extending from a first lateral wall 704a to a second lateral wall 704b. Further, each lateral wall 704a, 704b is associated with a third distance (d3) 906 extending from a respective wall 522a, 524b to the trench 540. In particular, the first lateral wall 704a is associated with a third distance (d3) 906 and the second lateral wall 704b is associated with another third distance (d3) 906. In the illustrated example of
For the sake of simplicity and for illustrative purposes only, the third distances (d3) 906 associated with respective ones of the lateral walls 704a, 704b are substantially similar. However, one or more of the third distances (d3) 906 can differ in other examples. Further, in this example, the second distance (d2) 904 is twice as large as each one of the third distances (d3) 906 for the sake of simplicity and for illustrative purposes only. In other examples, the distances (d1, d2, d3) 902, 904, 906 can differ.
As illustrated in
As illustrated in
Based on the foregoing distances associated with the illustrated example of
As discussed above, the dielectric structure 502 disclosed herein is associated with relatively low dielectric constant. This can be achieved even when the solid-state dielectric material 510, 802 is associated with a relatively high dielectric constant (e.g., a higher k than SiO2). As illustrated in Table 1, the inter-interconnect dielectric constants are each below two, allowing for improved signal isolation from interconnect structure 512 to interconnect structure 512. These relative inter-interconnect dielectric constants also enable relatively low time-delay constants for such interconnect structures 512. This increases (e.g., maximizes) the bandwidth per line and the bandwidth density that can be achieved per unit length for high-density die-to-die interconnects and for classical package-based HSIO (high-speed IO) interconnects (e.g., relative to redistribution layer HSIO interconnects or interconnects on package substrates). It must be noted that the values in Table 1 do not take stray fields into account which may slightly increase real-world inter-interconnect dielectric constants. Further, the values provided in Table 1 assume the particular geometric shape for the trench 540 (e.g., rectangular) and the associated dimensions or distances 902, 904, 906 shown in
Turning in detail to the drawings,
In some examples, as discussed above, the lateral walls 704 are narrower nearer the first surface 506 of the lower portion 508 of the IC device 500, and wider as they approach the third wall 526 of the trace 514a, 514b. The slanted (narrowing) shape of the lateral walls 704 of the dielectric structure 502 is achieved by manipulation of adjustable parameters of the deposition process, including (but not limited to) deposition rate, gas flow, an amount of material, temperature, pressure, power, etc. For example, adjusting a gas flow rate and/or one or more other parameters noted above during the deposition process enables adjustment of a shape of the lateral walls 704 and, consequently, a shape of the trench 540. To achieve the cross-section illustrated in
In some examples, experiments can be conducted to determine deposition parameters that will achieve a desired trench 540. For example, experiments may be conducted using a dedicated high rate deposition tool (e.g., dielectric gap-fill tool). Optimization of deposition parameters will yield very similar values for the dielectric number k for such shapes.
In some examples, an aspect ratio of the space 538 between interconnect structures 512 can be determinative of whether a trench 540 will form. For example, an aspect ratio of the space 538 between the first trace 514a and the second trace 514b corresponds to a height (h) of the traces 514a, 514b relative to a distance (d) between the traces 514a, 514b. If this aspect ratio is relatively low (e.g., below 0.5), the distance (d) between the traces 514a, 514b is more than twice the height (h) of the traces 514a, 514b. In some such examples, the trench 540 may be difficult to form as the overhang 1002 formed at corners 1004 of the traces 514a, 514b may not grow fast enough to pinch off at the top when the opposing overhangs 1002 meet before the space 538 between the interconnect structures 512 (e.g., below the overhangs 1002) fill up with the dielectric material 510 associated with the base 706. Accordingly, in some examples, the aspect ratio of the space 538 is at least 0.5 (e.g., at least 0.75, at least 1, at least 1.25, etc.).
While an example manner of fabricating the example dielectric structures 502 has been illustrated in 10A-10D, one or more of the steps and/or processes illustrated in
While an example manner of fabricating the example IC device 500 has been illustrated in 11A-11C, one or more of the steps and/or processes illustrated in
In this example, the interconnect structures 512 include the barrier material 532 surrounding or encapsulating the first, second, and third walls 522, 524, 256 of the traces 514e, 514f and the first, second, and third walls 1204, 1206, 1208 of the via pad 1202. In other examples, the barrier material 532 may be omitted.
While an example manner of fabricating the example IC device 500 has been illustrated in 12A-12D, one or more of the steps and/or processes illustrated in
The IC device 1300 of
The IC device 1300 of
As illustrated in
In particular, the IC device 1300 includes an example recess 1310 in spaces 538 between adjacent ones of the interconnect structures 512 in the third and fifth interconnect layers 1302, 1306. In this example, the recesses 1310 in the third interconnect layer 1302 extend from the third surface 1308 of the fourth interconnect layer 1304 into at least a portion of the fourth interconnect layer 1304. The recesses 1310 in the fifth interconnect layer 1306 extend from the second surface 536 of the first interconnect layer 504 into at least a portion of the first interconnect layer 504. Further, the recesses 1310 in the illustrated example of
As illustrated in
In this example, ones of the dielectric structures 502 in the third and fifth interconnect layers 1302, 1306 extend into respective ones of the recesses 1310. In other words, the ones of the dielectric structures 502 in the third and fifth interconnect layers 1302, 1306 extend into the dielectric material 510, 802 below to extend the trench 540 (e.g., airgap). Thus, in some examples, the trenches 540 extend both below and above adjacent interconnect structures 512 (at least the traces 514). In other words, in some examples, the trenches 540 are closer to an underlying surface of an underlying substrate than the adjacent interconnect structures 512 are to the surface of the underlying substrate. Further, in some examples, the trenches 540 extend farther away from the underlying surface of the underlying substrate than the adjacent interconnect structures 512 extend away from the surface of the underlying substrate. Providing trenches 540 that extend beyond (e.g., lower than) base surfaces of the adjacent the interconnect structures further lowers a dielectric constant associated with these dielectric structures 502. In some examples, a cost associated with extending the dielectric structures 502 is marginal or limited.
As illustrated in
While an example manner of fabricating the example IC device 1300 has been illustrated in 14A-14D, one or more of the steps and/or processes illustrated in
At block 1502, the method includes providing a first interconnect structure 512 and a second interconnect structure 512 on the first surface of the underlying structure. For example, the interconnect structures 512 can include one or more traces 514 and/or one or more vias 516. A space 538 is provided between the first and second interconnect structures 512. In some examples, more than two interconnect structures 512 are added to the underlying structure. The interconnect structures 512 can be patterned on the first surface 506 of the lower portion 508 of the IC device 500, 800, 900, 1300 via lithography and/or deposited and patterned on the surface 506 of the lower portion 508 of the IC device 500, 800, 900, 1300 via deposition. In some examples, a barrier material 532 can encapsulate or surround the interconnect structures 512.
At block 1504, the method includes determining whether to fabricate a recess 1310 into the first surface 506 between the first and second interconnect structures 512. When the answer to block 1504 is YES, the method 1500 goes to block 1506. At block 1506, the method includes forming the recess into the first surface between the first and second interconnect structures. When the answer to block 1504 is NO, the method 1500 advances to block 1508.
At block 1508, the method includes forming a first dielectric structure 502 that includes a closed-off trench 540 between the first and second interconnect structures 512. For example, the method includes depositing a first dielectric material 510, 802 to form a base 706 and lateral walls 704 of the dielectric structure 502. In some examples, the first dielectric material 510, 802 is deposited using a chemical vapor deposition (CVD) process. However, any suitable process to deposit the first dielectric material 510, 802 can be used. Further, the method includes adjusting the deposition process such that the first dielectric material 510, 802 grows (e.g., is deposited) faster near the top surface of the interconnect structures (e.g., at locations farthest from the surface of the underlying structure) so that the lateral walls 704 defines overhangs that eventually meet one another to form the closed-off region 712.
At block 1510, the method includes depositing additional first dielectric material to surround the first and second interconnect structures and the first dielectric structure. For example, the method can include deposition of the first dielectric material 510, 802 to cover the trench 540 and the interconnect structures 512. In particular, excess first dielectric material 510, 802 may be deposited to cover each trench 540 in the layer and/or to a desired via length. Thus, the trenches 540 of the dielectric structure 502 and the interconnect structures 512 are encapsulated by the first dielectric material 510, 802. In some examples, the deposition process to add the additional first dielectric is a continuation of the deposition process at block 1506 to form the first dielectric structure. That is, in some examples, blocks 1506 and 1508 correspond to a single deposition process. In other examples, blocks 1506 and 1508 are implemented in separate stages.
At block 1512, the method includes removing excess first dielectric material above the dielectric structure. In particular, the method includes removal of unwanted or excess portions of the dielectric material 510, 802. For example, a planarization and/or a via reveal process may be applied.
At block 1514, the method includes determining whether to add another layer of dielectric structures. When the answer to block 1514 is YES, example method of
While an example method of manufacturing the example dielectric structures 502 disclosed herein, one or more of the blocks in
Additionally, in various examples, the electrical device 1600 may not include one or more of the components illustrated in
The electrical device 1600 may include programmable circuitry 1602 (e.g., one or more processing devices). The programmable circuitry 1602 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 1600 may include a memory 1604, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some examples, the memory 1604 may include memory that shares a die with the programmable circuitry 1602. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
In some examples, the electrical device 1600 may include a communication chip 1612 (e.g., one or more communication chips). For example, the communication chip 1612 may be configured for managing wireless communications for the transfer of data to and from the electrical device 1600. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some examples they might not.
The communication chip 1612 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip 1612 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1612 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1612 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip 1612 may operate in accordance with other wireless protocols in other examples. The electrical device 1600 may include an antenna 1622 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some examples, the communication chip 1612 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip 1612 may include multiple communication chips. For instance, a first communication chip 1612 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1612 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some examples, a first communication chip 1612 may be dedicated to wireless communications, and a second communication chip 1612 may be dedicated to wired communications.
The electrical device 1600 may include battery/power circuitry 1614. The battery/power circuitry 1614 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1600 to an energy source separate from the electrical device 1600 (e.g., AC line power).
The electrical device 1600 may include a display 1606 (or corresponding interface circuitry, as discussed above). The display 1606 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 1600 may include an audio output device 1608 (or corresponding interface circuitry, as discussed above). The audio output device 1608 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds.
The electrical device 1600 may include an audio input device 1624 (or corresponding interface circuitry, as discussed above). The audio input device 1624 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
The electrical device 1600 may include GPS circuitry 1618. The GPS circuitry 1618 may be in communication with a satellite-based system and may receive a location of the electrical device 1600, as known in the art.
The electrical device 1600 may include any other output device 1610 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1610 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 1600 may include any other input device 1620 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1620 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
The electrical device 1600 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, etc.), a desktop electrical device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some examples, the electrical device 1600 may be any other electronic device that processes data.
The foregoing examples of the dielectric structures 502 teach or suggest different features. Although each example dielectric structures 502 disclosed above has certain features, it should be understood that it is not necessary for a particular feature of one example to be used exclusively with that example. Instead, any of the features described above and/or depicted in the drawings can be combined with any of the examples, in addition to or in substitution for any of the other features of those examples. One example's features are not mutually exclusive to another example's features. Instead, the scope of this disclosure encompasses any combination of any of the features.
“Including” and “comprising” (and all forms and tenses thereof) are used herein to be open ended terms. Thus, whenever a claim employs any form of “include” or “comprise” (e.g., comprises, includes, comprising, including, having, etc.) as a preamble or within a claim recitation of any kind, it is to be understood that additional elements, terms, etc., may be present without falling outside the scope of the corresponding claim or recitation. As used herein, when the phrase “at least” is used as the transition term in, for example, a preamble of a claim, it is open-ended in the same manner as the term “comprising” and “including” are open ended. The term “and/or” when used, for example, in a form such as A, B, and/or C refers to any combination or subset of A, B, C such as (1) A alone, (2) B alone, (3) C alone, (4) A with B, (5) A with C, (6) B with C, or (7) A with B and with C. As used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, items, objects and/or things, the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase “at least one of A and B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the performance or execution of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” is intended to refer to implementations including any of (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.
As used herein, singular references (e.g., “a”, “an”, “first”, “second”, etc.) do not exclude a plurality. The term “a” or “an” object, as used herein, refers to one or more of that object. The terms “a” (or “an”), “one or more”, and “at least one” are used interchangeably herein. Furthermore, although individually listed, a plurality of means, elements, or actions may be implemented by, e.g., the same entity or object. Additionally, although individual features may be included in different examples or claims, these may possibly be combined, and the inclusion in different examples or claims does not imply that a combination of features is not feasible and/or advantageous.
From the foregoing, it will be appreciated that example systems, apparatus, articles of manufacture, and methods have been disclosed that improve interconnect structures in integrated circuit packages. Examples disclosed herein have lower dielectric constants of dielectrics between interconnect structures relative to known dielectrics due to an airgap within the dielectric material.
Example methods, apparatus, systems, and articles of manufacture to provide improved interconnect structures in integrated circuit packages for semiconductor packages are disclosed herein. Further examples and combinations thereof include the following:
Example 1 includes an integrated circuit (IC) package comprising a first interconnect structure positioned on a first surface of an underlying substrate, a second interconnect structure positioned on the first surface of the underlying substrate, the second interconnect structure adjacent to the first interconnect structure, and a first dielectric material between the first and second interconnect structures, the first dielectric material including an enclosed trench within a space between the first and second interconnect structures.
Example 2 includes the IC package of example 1, wherein the enclosed trench includes a second dielectric material that is different than the first dielectric material.
Example 3 includes the IC package of example 1, wherein at least one of the first interconnect structure or the second interconnect structure is a trace.
Example 4 includes the IC package of example 1, wherein at least one of the first interconnect structure or the second interconnect structure is a via that extends through the first dielectric material.
Example 5 includes the IC package of example 1, wherein the first interconnect structure has a width and a height, the enclosed trench to extend away from the first surface of the underlying substrate beyond the height of the first interconnect structure.
Example 6 includes the IC package of example 1, wherein the enclosed trench includes a first portion and a second portion, the second portion having an arched cross-section.
Example 7 includes the IC package of example 1, wherein the first and second interconnect structures are in a first interconnect layer of the IC package, the first interconnect layer including a second surface facing away from the first surface of the underlying substrate.
Example 8 includes the IC package of example 7, wherein the space is a first space, the enclosed trench is a first enclosed trench, the IC package further including a second interconnect layer, the second interconnect layer including a third interconnect structure positioned on the second surface of the first interconnect layer, a fourth interconnect structure positioned on the second surface of the first interconnect layer, the fourth interconnect structure adjacent to the third interconnect structure, and a second dielectric material between the third and fourth interconnect structures, the second dielectric material including a second enclosed trench within a second space between the third and fourth interconnect structures.
Example 9 includes the IC package of example 8, further including transistors, and multiple additional interconnect layers closer to the transistors than the first and second interconnect layers are to the transistors.
Example 10 includes an integrated circuit (IC) package comprising a first interconnect structure and a second interconnect structure, and a dielectric structure positioned between the first and second interconnect structures, the dielectric structure defining a cavity substantially devoid of solid matter.
Example 11 includes the IC package of example 10, wherein the cavity occupies approximately half of a space between the first and second interconnect structures.
Example 12 includes the IC package of example 10, further including a package substrate, the first and second interconnect structures in the package substrate.
Example 13 includes the IC package of example 10, further including an interposer, the first and second interconnect structures in the interposer within the IC package.
Example 14 includes the IC package of example 10, further including a semiconductor die, the first and second interconnect structures in the semiconductor die within the IC package.
Example 15 includes the IC package of example 10, wherein the first and second interconnect structures are disposed on a first surface of an adjacent interconnect layer, the IC package further including a recess extending from the first surface into second dielectric material in the adjacent interconnect layer, the recess positioned between the first and second interconnect structures.
Example 16 includes the IC package of example 15, wherein the cavity of the dielectric structure extends into the recess.
Example 17 includes a method comprising providing, on a first surface of an underlying substrate, a first interconnect structure and a second interconnect structure adjacent to the first interconnect structure, a space disposed between the first and second interconnect structures, depositing a first portion of dielectric material on a first outer surface associated with the first interconnect structure and a second portion of the dielectric material on a second outer surface associated with the second interconnect structure, and generating an enclosed cavity within the space by connecting the first portion of the dielectric material with the second portion of the dielectric material, the first and second portions of the dielectric material defining overhangs over the space.
Example 18 includes the method of example 17, further including removing excess dielectric material above the enclosed cavity to generate a third surface.
Example 19 includes the method of example 18, wherein the space is a first space and the enclosed cavity is a first enclosed cavity, further including providing, on the third surface, a third interconnect structure and a fourth interconnect structure adjacent to the third interconnect structure, a second space disposed between the third and fourth interconnect structures, depositing a third portion of the dielectric material on a third outer surface of the third interconnect structure and a fourth portion of the dielectric material on a fourth outer surface on the fourth interconnect structure, and generating a second enclosed cavity within the second space by connecting the third portion of the dielectric material with the fourth portion of the dielectric material, the third and fourth portions of the dielectric material defining overhangs over the second space.
Example 20 includes the method of example 17, further including generating, prior to depositing the dielectric material, a recess that extends from the first surface into the underlying substrate, the recess positioned between the first interconnect structure and the second interconnect structure.
The following claims are hereby incorporated into this Detailed Description by this reference. Although certain example systems, apparatus, articles of manufacture, and methods have been disclosed herein, the scope of coverage of this patent is not limited thereto. On the contrary, this patent covers all systems, apparatus, articles of manufacture, and methods fairly falling within the scope of the claims of this patent.
