Claims
- 1. A method for fabricating a multichip semiconductor stack having input/output (I/O) nodes with customizable electrostatic discharge protection, said method comprising the steps of:
- (a) providing a plurality of semiconductor device chips, each semiconductor device chip comprising an integrated circuit connected to an I/O node and an electrostatic discharge suppression circuit designed to have an electrical connection to said I/O node;
- (b) laminating said plurality of integrated circuit chips such that a planar main surface of each semiconductor device chip is parallel and structurally coupled to a planar main surface of an adjacent semiconductor device chip of said plurality of semiconductor device chips, thereby defining a multichip stack having a side surface;
- (c) establishing a conductive pattern on said side surface of said multichip stack, said conductive pattern electrically connecting to each of the I/O nodes from the plurality of semiconductor device chips, at least some of said I/O nodes being electrically connected by said conductive pattern as a common I/O node; and
- (d) disrupting the electrical connection of at least one of said electrostatic discharge suppression circuits to a respective I/O node comprising part of said common I/O node.
- 2. The method of claim 1 wherein said disrupting step comprises turning off a switch, said switch interconnecting said at least one of said electrostatic discharge suppression circuits to a respective I/O node.
- 3. The method of claim 2 wherein said switch comprises a switch of low capacitive loading and low leakage current.
- 4. The method of claim 2 wherein said switch comprises a pass gate.
- 5. The method of claim 1 wherein said disrupting step comprises opening a fuse, said fuse interconnecting said at least one of said electrostatic discharge suppression circuits to a respective I/O node.
- 6. A method for fabricating a multichip semiconductor stack having input/output (I/O) nodes with customizable electrostatic discharge protection, said method comprising the steps of:
- (a) providing a plurality of semiconductor device chips, each semiconductor device chip comprising an integrated circuit connected to an I/O node and an electrostatic discharge suppression circuit designed to have an electrical connection to said I/O node;
- (b) laminating said plurality of integrated circuit chips such that a planar main surface of each semiconductor device chip is parallel and structurally coupled to a planar main surface of an adjacent semiconductor device chip of said plurality of semiconductor device chips, thereby defining a multichip stack having a side surface;
- (c) establishing a conductive pattern on said side surface of said multichip stack, said conductive pattern electrically connecting to each of the I/O nodes from the plurality of semiconductor device chips; and
- (d) modifying an electrical connection of at least one of said electrostatic discharge suppression circuits to at least one of said I/O nodes of said multichip stack.
- 7. The method of claim 6 wherein said modifying step is performed to customize electrostatic discharge suppression protection to said at least one of said I/O nodes.
- 8. The method of claim 7 wherein said modifying step comprises disrupting the electrical connection of said at least one of said electrostatic discharge suppression circuits to a respective I/O node in order to reduce electrostatic discharge protection to said respective I/O node.
- 9. The method of claim 7 wherein said modifying step comprises redirecting the electrical connection of said at least one of said electrostatic discharge suppression circuits in order to increase electrostatic discharge protection to said at least one I/O node.
- 10. The method of claim 6 wherein said modifying step serves to isolate at least one redundant electrostatic discharge suppression circuit from said I/O nodes.
- 11. The method of claim 6 wherein said modifying step serves to balance electrostatic discharge suppression circuitry loading on the I/O nodes of said multichip stack.
- 12. The method of claim 6 wherein said at least one of said I/O nodes comprises a common I/O node formed by electrically connecting with said conductive pattern at least some of said I/O nodes.
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a division of application Ser. No. 08/532,451 filed Sep. 22, 1995 which application is now: abandoned, which is a continuation-in-part of a commonly assigned U.S. patent application Ser. No. 392,461, filed Feb. 22, 1995 now U.S. Pat. No. 5,703,747, entitled "Multichip Semiconductor Structures With Interchip Electrostatic Discharge Protection, and Fabrication Methods Therefore."
US Referenced Citations (17)
Non-Patent Literature Citations (4)
Entry |
"Partitioning Function and Packaging of Integrated Circuits for Physical Security of Data", IBM Technical Buelletin, vol. 32 No. 1 (Jun. 1989). |
"Chip-on-Chip DSP/SRAM Multichip Module" K. L. Tai et al., 1995 International Conf. on Multichip Modules (SPIE vol. 2575), pp. 466-471, (1995). |
"Active Silicon Chip Carrier", D. J. Bodendorf et al., IBM Technical Disclosure Bulletin, vol. 15 No. 2, (Jul. 1972). |
"A GaAs on Si PLL Frequency Synthesizer IC Using Chip on Chip Technology", S. Sekine et al., IEEE 1994 Custom Integrated Circuits Conference (Cat. No. 94CH3427-2), pp. 563-565, (1994). |
Divisions (1)
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Number |
Date |
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Parent |
532451 |
Sep 1995 |
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Continuation in Parts (1)
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Number |
Date |
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392461 |
Feb 1995 |
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