Patent Application
20160079094
This disclosure relates generally to semiconductor wafers and methods of protecting semiconductor wafers. More specifically, disclosed embodiments relate to methods of protecting peripheries of semiconductor wafers during processing, and to related in-process wafers.
Active surfaces of in-process semiconductor wafers, and semiconductor devices comprising stacks of semiconductor dice located on those active surfaces, may be at least partially encapsulated in encapsulation materials. For example, encapsulation material may be dispensed over a portion of the active surface of a thinned semiconductor wafer supported by a carrier to cover and protect semiconductor devices located on the active surface. More specifically, a mold body having a smaller inner diameter than an outer diameter of the wafer may be used to contact a major surface, such as the active surface, of the wafer around a periphery of the wafer. Encapsulation material in the form of a so-called molding compound may flow into the mold, over the active surface, and over and around each semiconductor device. The encapsulation material may be cured, and the mold may be removed from contact with the periphery of the wafer. Contact of the mold body with the wafer surface prevents contamination by preventing the mold compound from reaching the edge of the wafer.
However, the above approach results, after debonding of the wafer from the carrier, exposure of the wafer edge, which is vulnerable to edge chipping and cracking, causing handling issues.
While this disclosure concludes with claims particularly pointing out and distinctly claiming specific embodiments, various features and advantages of embodiments within the scope of this disclosure may be more readily ascertained from the following description when read in conjunction with the accompanying drawings, in which:
The illustrations presented in this disclosure are not meant to be actual views of any particular semiconductor device, wafer of semiconductor material, act in a method of protecting a wafer, or component thereof, but are merely idealized representations employed to describe illustrative embodiments. Thus, the drawings are not necessarily to scale.
Disclosed embodiments relate generally to methods of protecting peripheries of semiconductor wafers and related systems and apparatuses. More specifically, disclosed are embodiments of methods of protecting peripheries of wafers of semiconductor material that may involve more fully encapsulating active surfaces of the wafers, and semiconductor devices on the active surfaces, in encapsulation materials, such that the encapsulation materials protect the peripheries of the semiconductor wafers.
As noted above, when the mold body used for encapsulation contacts a major surface, such as the active surface at the periphery of a wafer, the periphery may not be encapsulated in encapsulation material because it is covered by the mold. The unencapsulated periphery of the wafer may then be vulnerable to damage. For example, the wafer may be thin, on the order of about 40 μm to about 60 μm thickness, and of brittle semiconductor material, typically silicon. As the wafer requires additional processing, shipping, and other handling after it has been detached from the carrier substrate, the periphery of the wafer may crack, chip, or otherwise become damaged. The damage to the periphery may even affect other areas of the wafer, as cracks propagate from the periphery radially inward. As a result, semiconductor devices on the active surface of the wafer may become damaged, reducing yield.
In addition, forcing the mold against the periphery of the wafer may introduce unnecessary stress into the wafer. For example, the mold may press with a force of 100 kN or greater (e.g., 200 kN or greater) against the active surface at the periphery of the wafer. Stress within the wafer may exceed 2 MPa, 4 MPa, or even 9 MPa, which may introduce cracks that subsequently may propagate to damage the wafer.
Referring to
At least one semiconductor device 108 may be located on the active surface 102 of the wafer 100. For example, the wafer 100 may include a plurality of semiconductor devices 108 distributed on the active surface 102 of the wafer 100. At least one semiconductor device 108 may include, for example, integrated circuitry 110 embedded within the active surface 102 of the wafer 100. More specifically, each semiconductor device 108 may include, for example, integrated circuitry 110 confined within a predetermined area on the active surface 102 of the wafer 100. Streets 112 may be defined between the semiconductor devices 108 on the active surface 102. At least one semiconductor device 108 may include, for example, at least one semiconductor die 114 located on the active surface 102. More specifically, each semiconductor device 108 may include a stack of semiconductor dice 114 positioned over the active surface 102. The semiconductor dice 114 may be electrically connected to each other and to the integrated circuitry 110 of an unsingulated semiconductor die 114 of the wafer 100, and may be physically secured to the wafer 100.
The wafer 100 may be secured to a carrier substrate 116 to reinforce the wafer 100. The carrier substrate 116 may be, for example, a rigid sheet of material (e.g., semiconductor material or glass material) configured to support and protect the wafer 100. In some embodiments, the carrier substrate may be larger than the wafer 100. For example, a surface area of an upper surface 118 of the carrier substrate 116 may be greater than a surface area of the active surface 102 of the wafer 100. More specifically, a diameter D of the carrier substrate 116 may be greater than the outer diameter OD of the wafer 100 in embodiments where a cross section of each of the carrier substrate 116 and the wafer 100 is circular. As a specific, nonlimiting example, the diameter D of the carrier substrate 116 may be between about 1 mm and about 50 mm (e.g., about 5 mm) greater than the outer diameter OD of the wafer 100. In other embodiments, the diameter of the carrier substrate 116 may be at least substantially equal to the outer diameter OD of the wafer 100.
An adhesive material 120 may be positioned between the wafer 100 and the carrier substrate 116. More specifically, the adhesive material 120 may contact the back side surface 104 of the wafer 100 and the upper surface 118 of the carrier substrate 116 to secure the wafer 100 to the carrier substrate 116. As specific, nonlimiting examples, the adhesive material 120 may be WaferBOND® HT-10.10 or BrewerBOND™ 220 from Brewer Science, Inc. of Rolla, Mo.; LC3200, LC5300, or LC5320 from 3M of Murray, Utah; Tri-layer temporary bonding material from Shin-Etsu Chemical Co. of Tokyo, Japan; or A4004 or A4007 from TOK of Hillsboro, Oreg. A thickness TA of the adhesive material 120 may be, for example, between about 20 microns and about 200 microns. More specifically, the thickness TA of the adhesive material 120 may be, for example, between about 40 microns and about 100 microns. As a specific, nonlimiting example, the thickness TA of the adhesive material 120 may be between about 50 microns and about 80 microns (e.g., about 65 microns).
The mold 122 may include, for example, an upper mold member 124 and a lower mold member 126. The upper mold member 124 may define a recess 128 (e.g., a concavity) within the upper mold member 124 sized to receive the wafer 100, the semiconductor devices 108 on the active surface 102 of the wafer 100, and at least a portion of the adhesive material 120 within the recess 128. More specifically, the upper mold member 124 may define a recess 128 sized and shaped to receive the wafer 100, the semiconductor devices 108, the adhesive material 120, and at least a portion of the carrier substrate 116 (e.g., the entire carrier substrate 116) may be positioned in the mold 122.
An inner diameter ID of the recess 128 defined by the upper mold member 124 may be greater than the outer diameter OD of the wafer 100. For example, the inner diameter ID of the recess 128 may be between about 0.001% and about 10% greater than the outer diameter OD of the wafer 100. More specifically, the inner diameter ID of the recess 128 may be, for example, between about 0.002% and about 5% greater than the outer diameter OD of the wafer 100. As a specific, nonlimiting example, the inner diameter ID of the recess 128 may be between about 0.003% and about 1% (e.g., about 0.05%) greater than the outer diameter OD of the wafer 100. The inner diameter ID of the recess 128 may be, for example, about 30 mm or less greater than the outer diameter OD of the wafer 100. More specifically, the inner diameter ID of the recess 128 may be, for example, about 10 mm or less greater than the outer diameter OD of the wafer 100. As a specific, nonlimiting example, the inner diameter ID of the recess 128 may be about 5 mm or less (e.g., about 1 mm) greater than the outer diameter OD of the wafer 100.
The inner diameter ID of the recess 128 defined by the upper mold member 124 may be greater than the diameter D of the carrier substrate 116. For example, the inner diameter ID of the recess 128 may be between about 0.001% and about 9% greater than the diameter D of the carrier substrate 116. More specifically, the inner diameter ID of the recess 128 may be, for example, between about 0.002% and about 4% greater than the diameter D of the carrier substrate 116. As a specific, nonlimiting example, the inner diameter ID of the recess 128 may be between about 0.003% and about 0.09% (e.g., about 0.09%) greater than the diameter D of the carrier substrate 116. The inner diameter ID of the recess 128 may be, for example, about 10 mm or less greater than the diameter D of the carrier substrate 116. More specifically, the inner diameter ID of the recess 128 may be, for example, about 5 mm or less greater than the diameter D of the carrier substrate 116. As a specific, nonlimiting example, the inner diameter ID of the recess 128 may be about 2.5 mm or less (e.g., about 1 mm) greater than the diameter D of the carrier substrate 116.
The upper mold member 124 may not contact the wafer 100 when enclosing the semiconductor devices 108 within the recess 128, which may eliminate the imposition of stress on the wafer 100 in comparison to use of a conventional mold body. More specifically, the upper mold member 124 may not contact the active surface 102 of the wafer 100 at a periphery of the wafer 100 when enclosing the semiconductor devices 108 within the recess 128. In some embodiments, the upper mold member 124 may not contact the wafer 100, the adhesive material 120, or the carrier substrate 116. For example, the upper mold member 124 may contact the lower mold member 126 to enclose the wafer 100, adhesive material 120, and carrier substrate 116 within the recess 128. More specifically, the carrier substrate 116 may be supported on the lower mold member 126, and the upper mold member 124 may contact and be pressed against the lower mold member 126 to enclose the wafer 100, adhesive material 120, and carrier substrate 116 within the recess 128.
Surfaces of the upper mold member 124 and the lower mold member 126 facing the recess 128 may be lined with a release material 130. For example, the release material 130 may coat the surfaces of the upper mold member 124 defining the recess 128 and the surface of the lower mold member 126 on which the carrier substrate 116 may be supported. The release material 130 may enable easier subsequent release from the mold 122. The release material 130 may be, for example, ETFE film 50MW 390NT or ETFE film 50HK 390NT from AGC of Exton, Pa. In some embodiments, the release material 130 on the upper mold member 124 may be different from the release material 130 on the lower mold member 126. In other embodiments, the release material 130 on the upper mold member 124 may be the same as the release material 130 on the lower mold member 126.
A width W1 of the encapsulation material 132 proximate a periphery of the wafer 100 may be, for example, between about 0.001% and about 10% of the outer diameter OD of the wafer 100. More specifically, the width W1 of the encapsulation material 132 proximate the periphery of the wafer 100 may be, for example, between about 0.002% and about 5% of the outer diameter OD of the wafer 100. As a specific, nonlimiting example, the width W1 of the encapsulation material 132 proximate the periphery of the wafer 100 may be between about 0.003% and about 1% (e.g., about 0.05%) of the outer diameter OD of the wafer 100. The width W1 of the encapsulation material 132 proximate the periphery of the wafer 100 may be, for example, about 30 mm or less. More specifically, the width W1 of the encapsulation material 132 proximate the periphery of the wafer 100 may be, for example, about 10 mm or less. As a specific, nonlimiting example, the width W1 of the encapsulation material 132 proximate the periphery of the wafer 100 may be about 5 mm or less (e.g., about 1 mm).
The width W2 of the encapsulation material 132 proximate a periphery of the carrier substrate 116 may be, for example, between about 0.001% and about 9% of the diameter D of the carrier substrate 116. More specifically, the width W2 of the encapsulation material 132 proximate the periphery of the carrier substrate 116 may be, for example, between about 0.002% and about 4% of the diameter D of the carrier substrate 116. As a specific, nonlimiting example, the width W2 of the encapsulation material 132 proximate the periphery of the carrier substrate 116 may be between about 0.003% and about 0.09% (e.g., about 0.09%) of the diameter D of the carrier substrate 116. The width W2 of the encapsulation material 132 proximate the periphery of the carrier substrate 116 may be, for example, about 10 mm or less. More specifically, the width W2 of the encapsulation material 132 proximate the periphery of the carrier substrate 116 may be, for example, about 5 mm or less. As a specific, nonlimiting example, the width W2 of the encapsulation material 132 proximate the periphery of the carrier substrate 116 may be about 2.5 mm or less (e.g., about 1 mm).
At least one side surface 138 of the encapsulation material 132 may be at least substantially flush with at least one corresponding side surface 106 of the wafer 102. For example, each side surface 138 of the encapsulation material 132 may be at least substantially flush with a corresponding side surface 106 of the wafer 102. More specifically, a single, annular side surface 138 defined by the encapsulation material 132, which may exhibit a circular cross-sectional shape, may be at least substantially flush with a corresponding, annular side surface 106 of the wafer 102, which may similarly exhibit a circular cross-sectional shape. In other words, the side surface 138 defined by the encapsulation material 132 and the side surface 106 defined by the wafer 102 may cooperatively define a contiguous, uninterrupted side surface. More specifically, there may be no ledge defined by the periphery of the wafer 100, which may not project laterally beyond the side surface 138 of the encapsulation material 132.
When only a portion of an edge of the adhesive material 120 is exposed, the adhesive material 120 may be exposed to a depth D of, for example, between about 1% and about 80% of the thickness TA of the adhesive material 120. More specifically, the adhesive material 120 may be exposed to a depth D of for example, between about 25% and about 65% of the thickness TA of the adhesive material 120. As a specific, nonlimiting example, the adhesive material 120 may be exposed to a depth D of, for example, between about 40% and about 60% (e.g., about 50%) of the thickness TA of the adhesive material 120. The adhesive material 120 may be exposed to a depth D of, for example, between about 0.2 microns and about 160 microns, as measured from the back side surface 104 of the wafer 100. More specifically, the adhesive material 120 may be exposed to a depth D of, for example, between about 20 microns and about 80 microns. As a specific, nonlimiting example, the adhesive material 120 may be exposed to a depth D of, for example, between about 40 microns and about 60 microns (e.g., about 50 microns).
In some embodiments, a portion of the adhesive material 120 may be removed to expose an underlying portion of the adhesive material 120. For example, as the removal device moves radially inward and encounters the side surface 134 of the adhesive material 120, the removal device may begin removing some of the adhesive material 120 at the periphery and define a new side surface 134. More specifically, the removal device may leave a ledge (e.g., a notch) in the adhesive material 120 at the periphery of the adhesive material 120.
In some embodiments, a portion of the semiconductor material of the wafer 100 may be removed when exposing the adhesive material 120. For example, as the removal device moves radially inward and encounters the side surface 106 of the wafer 100, the removal device may begin removing some of the semiconductor material at the periphery of wafer 100 and define a new side surface 106. More specifically, the removal device may reduce the outer diameter OD of the wafer 100 as it exposes the adhesive material 120 and renders the encapsulation material 132 at least substantially flush with the side surface 106 of the wafer. The outer diameter OD of the wafer 100 may be reduced, for example, by between about 0.01% and about 10%. More specifically, the outer diameter OD of the wafer 100 may be reduced, for example, by between about 0.05% and about 5%. As a specific, nonlimiting example, the outer diameter OD of the wafer 100 may be reduced by between about 0.1% and about 2.5% (e.g., about 1%). The outer diameter OD of the wafer 100 may be reduced, for example, by about 20 mm or less. More specifically, the outer diameter OD of the wafer 100 may be reduced, for example, by about 10 mm or less. As a specific, nonlimiting example, the outer diameter OD of the wafer 100 may be reduced by between about 5 mm or less (e.g., about 4 mm).
In some embodiments, encapsulation material 132 may remain on at least a portion of side surface 136 of the carrier substrate 116. For example, the encapsulation material 132 may be removed from the periphery inward only to a position within the thickness TA of the adhesive material 120, leaving encapsulation material 132 below that position in place. More specifically, the encapsulation material 132, any semiconductor material of the wafer 100, and any adhesive material 120 may be removed from the periphery inward to a position within the thickness TA of the adhesive material 120, leaving encapsulation material 132 on the upper surface 118 and the side surface 136 of the carrier substrate 116. In some embodiments, the encapsulation material 132 may then be removed from the carrier substrate 116 after debonding of wafer 100, and the carrier substrate 116 may be reused with another wafer.
In other words, methods of processing semiconductor wafers may involve, for example, encapsulating an active surface and each side surface of a wafer of semiconductor material, a plurality of semiconductor devices located on the active surface of the wafer, an exposed side surface of an adhesive material located on a back side surface of the wafer, and at least a portion of a side surface of a carrier substrate secured to the wafer by the adhesive material in an encapsulation material. At least a portion of the side surface of the adhesive material may be exposed by removing at least a portion of the encapsulation material. The carrier substrate may be detached from the wafer. In some embodiments, the wafer, the plurality of semiconductor devices, the adhesive material, and at least a portion of the carrier substrate may be positioned within a mold recess exhibiting an inner diameter greater than a diameter of the carrier substrate.
In-process semiconductor wafers produced by such methods may include, for example, a wafer of semiconductor material and a plurality of semiconductor devices located on an active surface of the wafer. An encapsulation material may be located on the active surface of the wafer and may surround at least side surfaces of each semiconductor device of the plurality of semiconductor devices. A side surface of the encapsulation material may be at least substantially flush with a side surface of the wafer.
Systems for processing semiconductor wafers may include, for example, a wafer of semiconductor material and a plurality of semiconductor devices located on an active surface of the wafer. A mold member may include a recess extending into the mold member, the recess being sized and shaped to at least partially receive the wafer into the recess. An inner diameter of the mold member defining the recess may be greater than an outer diameter of the wafer. In some embodiments, a carrier substrate may be secured to the wafer on a side of the wafer opposing the active surface by an adhesive material positioned between the wafer and the carrier substrate, and the inner diameter of the mold member defining the recess may be greater than a diameter of the carrier substrate.
Encapsulation material 132 may be positioned in the mold 140 over exposed surfaces of the wafer 100 and exposed surfaces of the semiconductor devices 108 on the active surface 102. More specifically, encapsulation material 132 in a flowable state may be dispensed into the mold 140 on the active surface 102 to surround the semiconductor devices 108, each side surface 106 of the wafer 100, each side surface 134 of the adhesive material 120, and the carrier substrate 116 remaining free from contact with the encapsulation material 132. As a specific, nonlimiting example, encapsulation material 132 may flow into the recess 146 of the mold 140 under vacuum to contact and cover the active surface 102 of the wafer 100 and to surround the exposed side and, optionally, top surfaces of the semiconductor devices 108, each side surface 106 of the wafer 100, each side surface 134 of the adhesive material 120, and the carrier substrate 116 remaining free from encapsulation material 132. The encapsulation material 132 may subsequently be cured to an at least substantially solid state.
The encapsulation material 132 may remain at least substantially flush with at least one side surface 106 of the wafer 100. For example, each side surface 138 of the encapsulation material 132 may be at least substantially flush with a corresponding side surface 106 of the wafer 102. More specifically, a single, annular side surface 138 defined by the encapsulation material 132, which may exhibit a circular cross-sectional shape, may be at least substantially flush with a corresponding, annular side surface 106 of the wafer 102, which may similarly exhibit a circular cross-sectional shape. In other words, the side surface 138 defined by the encapsulation material 132 and the side surface 106 defined by the wafer 102 may cooperatively define a contiguous, uninterrupted side surface. More specifically, there may be no ledge defined by the periphery of the wafer 100, which may not project from the side surface 138 of the encapsulation material 132. By confining the encapsulation material 132 to remain flush with the side surface 106 of the wafer 100 when positioning the encapsulation material 132 on the active surface 102, none of the encapsulation material 132 may require removal before detaching the wafer 100 from the carrier substrate 116.
The wafer 100, the semiconductor devices 108 on the active surface 102 of the wafer 100, and the encapsulation material 132 covering the active surface 102 of the wafer 100 may be removed from the adhesive material 120 and the carrier substrate 116. For example, the adhesive material 120 may be heated to weaken its attachment to the wafer 100. The wafer 100 and carrier substrate 116 may then be detached from one another by sliding one or both of the wafer 100 and the carrier substrate 116 laterally with respect to one another until they are no longer secured to one another.
In other words, methods of processing semiconductor wafers may involve, for example, encapsulating an active surface and a plurality of semiconductor devices located on the active surface of the wafer in an encapsulation material to cause a side surface defined by the encapsulation material to be at least substantially flush with a side surface of the wafer. The wafer may be secured to a carrier substrate on a side of the wafer opposing the active surface by an adhesive material positioned between the wafer and the carrier substrate. The carrier substrate may subsequently be detached from the wafer. In some embodiments, the wafer and the plurality of semiconductor devices may be positioned within a mold recess exhibiting an inner diameter greater than an outer diameter of the wafer and less than a diameter of the carrier substrate.
Systems for processing semiconductor wafers may include, for example, a wafer of semiconductor material and a plurality of semiconductor devices located on an active surface of the wafer. A mold member may include a recess extending into the mold member, the recess being sized and shaped to at least partially receive the wafer into the recess. An inner diameter of the mold member defining the recess may be greater than an outer diameter of the wafer. In some embodiments, a carrier substrate may be secured to the wafer on a side of the wafer opposing the active surface by an adhesive material positioned between the wafer and the carrier substrate, and the inner diameter of the mold member defining the recess may be less than a diameter of the carrier substrate.
While certain illustrative embodiments have been described in connection with the figures, those of ordinary skill in the art will recognize and appreciate that the scope of this disclosure is not limited to those embodiments explicitly shown and described in this disclosure. Rather, many additions, deletions, and modifications to the embodiments described in this disclosure may be made to produce embodiments within the scope of this disclosure, such as those specifically claimed, including legal equivalents. In addition, features from one disclosed embodiment may be combined with features of another disclosed embodiment while still being within the scope of this disclosure, as contemplated by the inventors.
