DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view illustrating a conventional micro BGA package having multi-chip stack.
FIG. 2 is a cross-sectional view illustrating a micro BGA package having multi-chip stack in accordance with the first embodiment of the present invention.
FIG. 3 is a plan view illustrating the micro BGA package prior to encapsulation in accordance with the first embodiment of the present invention.
FIG. 4 is a cross-sectional view illustrating another micro BGA package having multi-chip stack in accordance with the second embodiment of the present invention.
FIG. 5 is a plan view illustrating the micro BGA package prior to encapsulation in accordance with the second embodiment of the present invention.
FIG. 6 is a perspective view illustrating the micro BGA package prior to encapsulation in accordance with the second embodiment of the present invention.
DETAILED DESCRIPTION OF THE PRESENT INVENTION
FIG. 2 shows a cross-sectional view of a micro BGA package having multi-chip stack and FIG. 3 shows a plan view of the micro BGA package having multi-chip stack according to the first embodiment of the present invention.
Referring to FIG. 2 and FIG. 3, the micro BGA package 200 typically comprises a first chip 210, a second chip 220, a single-layer PCB 230, a plurality of first bonding wires 241, a plurality of second bonding wires 242, an encapsulant 250 and a plurality of solder balls 260.
Referring now to FIG. 2, the first chip 210 has a first active surface 211 and a rear surface 212 opposing to the first active surface 211, further has a plurality of first bonding pads 213 disposed about the periphery of the first active surface 211. However, there is no need to use the multi-layer PCB of conventional BGA as a chip carrier, an adhesive tape or thermal spreader is adapted to carry chip during fabricating processes.
The second chip 220 also has a second active surface 221 and an opposing rear surface 222. A plurality of second bonding pads 223 is disposed about the periphery of the second active surface 221 of the second chip 220. The second chip 220 faces up in the same direction with the first chip 210, which is attached to and stacked on the first active surface 211 of the first chip 210 by an adhesive layer 281. Moreover, the second chip 220 is smaller than the first chip 210 so that the first bonding pads 213 are uncovered by the second chip 220. Compared with the first chip 210, the second chip 220 has a smaller size to expose the first bonding pads 213 prior to encapsulation as shown in FIG. 3. In this embodiment, both the first and second chips 210, 220 can be flash memory, such as NAND flash or NOR flash. Furthermore in this embodiment, the memory capacity of the second chip 220 is smaller than that of the first chip 210, for example the first chip 210 may have 2 G memory capacity and the second chip 220 may have 1 G only memory capacity.
The single-layer PCB 230 is disposed on the second active surface 221 of the second chip 220 and smaller than the second chip 220. Referring now to FIG. 3, the second bonding pads 223 located on the second chip 220 are uncovered by the single-layer PCB 230 and the single-layer PCB 230 is attached to the second active surface 221 of the second chip 220 by applying an adhesive layer 282. The single-layer PCB 230 has single-layer wiring pattern 231 that further includes a plurality of wire-connecting pads 232 and a plurality of ball pads 233. In this embodiment, the single-layer PCB 230 is lack of PTH (Plated Through Hole) thereby lowering substrate-fabricating cost.
Besides applying wire-bonding technique, the first bonding wires 241 are used to electrically connect the first bonding pads 213 on the first chip 210 to the corresponding wire-connecting pads 232 on the single-layer PCB 230, and the second bonding wires 242 are also used to electrically connect the second bonding pads 223 on the second chip 220 to the corresponding wire-connecting pads 232 on the single-layer PCB 230.
The encapsulant 250 is formed around the first chip 210, the second chip 220 and the single-layer PCB 230 to seal the first bonding wires 241 and the second bonding wires 242 but expose the ball pads 233 and the rear surface 212 of the first chip 210. A transfer molding technique can be utilized to form the encapsulant 250. Referring now to FIG. 2, the encapsulant 250 substantially covers the first bonding wires 213, the second bonding wires 223, the wire-connecting pads 232 and the sides 214 of the first chip 210. The solder balls 260 are disposed on the ball pads 233 of the single-layer PCB 230.
The micro BGA package 200 desirably may further include a thermal spreader 270 that is attached to the rear surface 212 of the first chip 210 and the coplanar surface of the encapsulant 250 to improve thermal dissipation. Besides, the thermal spreader 270 may further have a plurality of thermal fins 271 to enhance thermal dissipation more effectively.
Therefore the micro BGA package 200 integrates multiple chips 210 and 220 into a BGA package, minimizes package footprint of multi-chip stack without increasing package thickness, solves thermal resistance problem of the encapsulant 250, enables the solder balls 260 to be concentrated, as well as saves substrate-fabricating cost. Particularly, if a flexible PCB having a thinner thickness is used as the single-layer PCB 230, there is an extra space to form an adhesive layer 282 with a thicker buffer resin to protect the solder balls 260 located at the substrate corners from directly taking thermal stress.
According to the second embodiment of the present invention, FIG. 4 shows a cross-sectional view of another micro BGA package, FIG. 5 shows a plan view of the micro BGA package prior to encapsulation, and FIG. 6 shows a perspective view of the micro BGA package prior to encapsulation.
Referring now to FIG. 4, a micro BGA package 300 typically comprises a first chip 310, a second chip 320, a single-layer PCB 330, a plurality of first bonding wires 341, a plurality of second bonding wires 342, an encapsulant 350 and a plurality of solder balls 360. A plurality of first bonding pads 313 is disposed about the periphery of a first active surface 311 of the first chip 310 and a plurality of second bonding pads 323 is disposed about the periphery of a second active surface 321 of the second chip 320. The second chip 320 is disposed on the first active surface 311 of the first chip 310. Referring now to FIG. 5 and FIG. 6, in this embodiment, the second chip 320 has a same size with the first chip 310 and is crisscross stacked on the first chip 310 to expose the first bonding pads 313 prior to encapsulation. Both the first and the second chips 310, 320 can be flash memory and have same memory capacity. The single-layer PCB 330 only has a wiring pattern (not showed in the drawings) including a plurality of wire-connecting pads 331 and a plurality of ball pads 332, which is disposed on the second chip 320 and smaller than the second chip 320. The first bonding wires 341 are applied to electrically connect the first bonding pads 313 to the wire-connecting pads 331, and also the second bonding wires 342 are applied to electrically connect the second bonding pads 323 to the wire-connecting pads 331. The encapsulant 350 is formed around the first chip 310, the second chip 320 and the single-layer PCB 330 to seal the first bonding wires 341 and the second bonding wires 342 but expose the rear surface 312 of the first chip 310. The encapsulant 350 substantially covers the first bonding pads 313, the second bonding pads 323, the wire-connecting pads 331 and the sides 314 of the first chip 310. The solder balls 360 are disposed on the ball pads 332 located on the single-layer PCB 330.
Accordingly, multiple chip 310, 320 having same size can be stacked and packaged into the micro BGA package 300, which has some merits such as reducing package size, eliminating thermal resistance of encapsulation, concentrating solder balls and saving substrate-fabricating cost.
While the present invention has been particularly illustrated and described in detail with respect to the preferred embodiments thereof, it will be clearly understood by those skilled in the art that various changed in form and details may be made without departing from the spirit and scope of the present invention.
Patent Application
20080087999
