Patent Grant
11828729
The technology described herein relates to complementary metal oxide semiconductor (CMOS) transducers and methods for forming the same.
Capacitive Micromachined Ultrasonic Transducers (CMUTs) are known devices that include a membrane above a micromachined cavity. The membrane may be used to transduce an acoustic signal into an electric signal, or vice versa. Thus, CMUTs can operate as ultrasonic transducers.
Two types of processes can be used to fabricate CMUTs. Sacrificial layer processes form the membrane of the CMUT on a first substrate above a sacrificial layer. Removal of the sacrificial layer results in the membrane being suspended above a cavity. Wafer bonding processes bond two wafers together to form a cavity with a membrane.
Aspects of the present application relate to fabrication and integration of CMUTs with CMOS wafers, thereby forming CMOS ultrasonic transducers (CUTs). According to an aspect of the present application, a wafer-level process is presented involving two wafer bonding steps. A first wafer bonding step may form sealed cavities by bonding together two silicon-on-insulator (SOI) wafers, the resulting bonded structure being considered an engineered substrate. Relatively high temperatures may be used, for example during an anneal, to facilitate achieving a strong bond. A handle layer of one of the two SOI wafers of the engineered substrate may then be removed, after which a second wafer bonding step may be performed to bond the engineered substrate with a CMOS wafer having integrated circuits (ICs) formed thereon. The second wafer bonding step may use a relatively low temperature to avoid damage to the ICs on the CMOS wafer. The handle layer of the second SOI wafer of the engineered substrate may then be removed, leaving a membrane over the cavities of the engineered substrate. Electrical connections between the CMOS IC and the engineered substrate allow for controllable ultrasonic transducers to be realized.
The wafer-level process described above may produce an ultrasound device with integrated CMUTs and CMOS ICs. The cavities of the CMUTs may be formed between two silicon layers representing the silicon device layers of the two SOI wafers used to form the engineered substrate. Yet, the handle layers of the two SOI wafers may be absent in the completed device, which facilitates achieving thin device dimensions and therefore a small size, among other benefits. Thus, the process may, in some aspects, include suitable steps for removing the handle layers while allowing for bonding of the engineered substrate with the CMOS wafer. The use of thru-silicon vias (TSVs) may also be absent in the final device, with suitable alternative structures being used to provide electrical connection to the resulting ultrasonic transducers.
According to another aspect of the present application, a bulk silicon wafer may be used in place of one or both of the SOI wafers described above. In such an instance, rather than removing a handle layer of the wafer, the wafer may be thinned to a desired point, for example using an etch stop represented by a doped layer of the bulk silicon wafer or using a timed etch. Thus, substantially the same structure may be achieved using either SOI or bulk silicon wafers or a combination of the two.
Accordingly, an aspect of the present application provides a wafer-level process including a first wafer bonding step to form sealed cavities by bonding together an SOI wafer and a bulk silicon wafer with cavities between them, the resulting bonded structure being considered an engineered substrate. Relatively high temperatures may be used, for example during an anneal, to facilitate achieving a strong bond. The bulk silicon wafer may be thinned, after which a second wafer bonding step may be performed to bond the engineered substrate with a CMOS wafer having integrated circuits (ICs) formed thereon. The second wafer bonding step may use a relatively low temperature to avoid damage to the ICs on the CMOS wafer. The handle layer of the SOI wafer of the engineered substrate may then be removed, leaving a membrane over the cavities of the engineered substrate.
According to an aspect of the present application, a method is provided comprising forming a plurality of cavities in a layer of silicon oxide on a first silicon device layer of a first SOI wafer, bonding the first SOI wafer with a second SOI wafer and then annealing the first and second SOI wafers, and removing a handle layer and a buried oxide layer of the first SOI wafer. The method further comprises bonding the first silicon device layer to a third wafer having at least one metal layer formed thereon, and removing a handle layer of the second SOI wafer subsequent to bonding the first silicon device layer to the third wafer.
According to an aspect of the present application, a method is provided comprising forming an engineered substrate having a plurality of sealed cavities by bonding a first wafer having open cavities formed therein with a second wafer and then thinning the first wafer to a thickness less than approximately 30 microns. The method further comprises bonding the engineered substrate with a third wafer at a temperature not exceeding 450° C., and subsequent to bonding the engineered substrate with the third wafer, thinning the second wafer to a thickness less than approximately 30 microns. In some embodiments, the second wafer, or a portion thereof, is configured to function as a membrane of an ultrasonic transducer, and therefore its thickness after being thinned is suitable to allow vibration. By contrast, in such instances it may be desirable for the first wafer not to vibrate, and thus its thickness after being thinned may be sufficiently great to minimize or prevent vibration. In a further embodiment, both the first and second wafers may be configured to vibrate, for example at different frequencies, to create a multi-frequency transducer. For example, the first membrane may be configured to resonate at half the center frequency of the second membrane.
According to an aspect of the present application, a method is provided, comprising forming a layer of silicon oxide on a first silicon device layer of a first SOI wafer, the first SOI wafer including a handle layer, a buried oxide (BOX) layer, and the first silicon device layer having a backside proximate the handle layer and a front side distal the handle layer. The method further comprises forming a plurality of cavities in the layer of silicon oxide, and bonding a second SOI wafer with the first SOI wafer such that a second silicon device layer of the second SOI wafer contacts the layer of silicon oxide and seals the plurality of cavities in the layer of silicon oxide. The method further comprises annealing the first and second SOI wafers after bonding them together, the annealing utilizing a temperature above 500° C. The method further comprises removing the handle layer of the first SOI wafer, etching a plurality of trenches in the first silicon device layer defining a plurality of electrode regions of the first silicon device layer corresponding to the plurality of cavities, and filling the plurality of trenches with an insulating material. The method further comprises forming metal contacts on the backside of the first silicon device layer, at least some of the metal contacts corresponding to the plurality of electrode regions. The method further comprises bonding the first silicon device layer with a CMOS wafer having integrated circuitry formed therein using the metal contacts on the backside of the first silicon device layer to contact bonding points on the CMOS wafer, wherein bonding the first silicon device layer with the CMOS wafer is performed below 450° C. The method further comprises removing a handle layer of the second SOI wafer.
According to an aspect of the present application, an apparatus is provided, comprising a CMOS wafer having an integrated circuit formed therein, and a substrate monolithically integrated with the CMOS wafer and including fewer than three silicon layers. A first silicon layer of the substrate and a second silicon layer of the substrate are arranged with a plurality of cavities therebetween.
According to an aspect of the present application, an apparatus is provided, comprising a CMOS wafer having an integrated circuit formed therein, and a substrate monolithically integrated with the CMOS wafer, the substrate having a first side proximate the CMOS wafer and a second side distal the CMOS wafer. The substrate comprises, in order from the first side to the second side, a first silicon layer, a layer of silicon oxide directly contacting the first silicon layer and having a plurality of cavities formed therein, and a second silicon layer directly contacting the silicon oxide and forming a membrane for the plurality of cavities.
The term “SOI wafer” as used herein has its conventional meaning, including a handle layer, a buried oxide (BOX) layer, and a silicon device layer separated from the handle layer by the BOX layer.
The term “engineered substrate” as used herein refers to a substrate engineered to differ from a basic silicon wafer or standard SOI wafer. An engineered substrate may also be a “composite substrate” formed by combining multiple distinct elements (e.g., multiple distinct wafers).
Throughout this disclosure, the use of the term “approximately” includes “exactly” unless context dictates otherwise. For example, describing a distance as being less than approximately 10 microns is to be understood to include the scenario in which the distance is less than 10 microns.
Various aspects and embodiments of the application will be described with reference to the following figures. It should be appreciated that the figures are not necessarily drawn to scale. Items appearing in multiple figures are indicated by the same reference number in all the figures in which they appear.
Aspects of the present application relate to fabrication and integration of CMUTs with CMOS wafers, thereby forming CMOS ultrasonic transducers (CUTs). The methods described provide scalable, low cost, high yield solutions to the challenge of integrating CMUTs with CMOS wafers using techniques available in commercial semiconductor foundries, thus utilizing a readily available supply chain. In some embodiments, piezoelectric micromachined ultrasonic transducers (PMUTs) are used instead of, or in addition to, CMUTs.
According to an aspect of the present application, a wafer-level process is presented involving two wafer bonding steps, at least one of which may take advantage of wafer level packaging techniques. A first wafer bonding step may form sealed cavities by bonding together two silicon-on-insulator (SOI) wafers, the resulting bonded structure being considered an engineered substrate, and representing a buried cavity SOI wafer. Relatively high temperatures may be used, for example during an anneal, to facilitate achieving a strong bond. A handle layer of one of the two SOI wafers of the engineered substrate may then be removed, after which a second wafer bonding step may be performed to bond the engineered substrate with a CMOS wafer having integrated circuits (ICs) formed thereon. The second wafer bonding step may use a relatively low temperature to avoid damage to the ICs on the CMOS wafer. The handle layer of the second SOI wafer of the engineered substrate may then be removed.
In some embodiments, the bonding used to form the engineered substrate with sealed cavities may include fusion bonding. In some such embodiments, the bonding may be performed at a low temperature. However, a relatively high temperature anneal may be performed to ensure a strong bond. The fabrication of sealed cavities is decoupled from the thermal budget of CMOS IC fabrication since the engineered substrate is fabricated prior to integrating such structures with a CMOS wafer, thus allowing for use of a relatively high temperature anneal without damaging ICs in the final device.
In some embodiments, the bonding performed to integrate the engineered substrate having sealed cavities with the CMOS wafer may include thermal compression (also referred to herein as “thermocompression”), eutectic bonding, or silicide bonding (which is a bond formed by bringing silicon of one substrate into contact with metal on a second substrate under sufficient pressure and temperature to form a metal silicide, creating a mechanical and electrical bond), as non-limiting examples. Such bonding may be performed at temperatures sufficiently low to avoid damage to the ICs on the CMOS wafer, while still providing for a strong bond and also facilitating electrical interconnection of the ICs on the CMOS wafer with the sealed cavities of the engineered substrate. Accordingly, aspects of the present application implement low temperature (e.g., below 450° C.) wafer bonding to form ultrasonic transducer membranes on CMOS wafers. Low temperature in this context may, in some embodiments, be below 450° C., below 400° C., below 350° C., between 200° C. and 450° C., any temperature within that range, or any suitable temperature for preserving structures on a CMOS wafer. Thus, the bonding processes as well as other fabrication steps for integrating the sealed cavities with CMOS ICs to form CUTs may avoid any anneals above 450° C.
According to an aspect of the present application, an apparatus including an engineered substrate is bonded with a CMOS wafer having a CMOS IC formed thereon. The engineered substrate may include multiple wafers bonded together to form sealed cavities. The engineered substrate may then be bonded with the CMOS wafer. The engineered substrate may include one substrate configured to serve as a membrane which vibrates and another substrate serving as a support, and which is not meant to vibrate. This latter substrate may be sufficiently thick (e.g., greater than approximately 5 microns) to prevent unwanted vibration, but also sufficiently thin (e.g., less than approximately 30 microns) to contribute to small device dimensions.
According to an aspect of the present application, an apparatus including an engineered substrate is bonded with a CMOS wafer having a CMOS IC formed thereon and the engineered substrate includes multiple wafers bonded together to form sealed cavities and configured to vibrate. One wafer of the engineered substrate may be configured to resonate at a first frequency and a second wafer of the engineered substrate may be configured to resonate at a different frequency. Thus, a multi-frequency ultrasound transducer may be created. One frequency may be used for transmit operations and the other for receive operations, as a non-limiting example. For example, a first, lower frequency may be used for transmit operations and a second, higher frequency (e.g., twice the frequency of the lower frequency) may be used for receive operations, as a non-limiting example.
The aspects and embodiments described above, as well as additional aspects and embodiments, are described further below. These aspects and/or embodiments may be used individually, all together, or in any combination of two or more, as the application is not limited in this respect.
As described, aspects of the present application provide a process for fabricating CUTs having integrated CMUTs and CMOS ICs and utilizing two separate bonding steps. The process may allow for a resulting structure to include a relatively thin engineered substrate having cavities formed between two silicon layers monolithically integrated with a CMOS wafer having CMOS ICs thereon.
As shown, the method 100 may begin at stage 102 with the formation of an engineered substrate having sealed cavities. Two SOI wafers may be bonded together, for example with the silicon device layers of the two SOI wafers facing each other. One or both of the two SOI wafers may have a plurality of cavities formed therein, such that bonding the two SOI wafers together may result in sealed cavities suitable for use as the cavities of CMUTs. To ensure a strong bond between the two SOI wafers, high temperature processing may be used. For example, a high temperature anneal may be used subsequent to a low temperature wafer bond, such as a low temperature fusion bond. Thus, a combination of high and low temperatures may be used in forming the engineered substrate in some embodiments. High temperature in this context may, in some embodiments, be above 450° C., a temperature threshold above which CMOS ICs would typically be damaged.
The bonding of the two SOI wafers may be performed in vacuum so that the resulting sealed cavities have a low pressure (e.g., a pressure between approximately 1×10−3 Torr and approximately 1×10−5 Torr, a pressure less than approximately 1 atmosphere, or any other suitable pressure). In some embodiments, the bond is performed in an inert ambient, for example using N2.
At stage 104, a handle layer of a first of the two SOI wafers may be removed, in any suitable manner, such as by a combination of grinding followed by etching. As a result, the engineered substrate may, at this point in the process, include three silicon layers: the silicon device layer of the first SOI wafer, the silicon device layer of the second SOI wafer, and the handle layer of the second SOI wafer. Although the silicon device layers of the SOI wafers may be thin, for example being 20 microns or less in thickness (e.g., 10 microns, 5 microns, 2.5 microns, 2 microns, 1 micron, or less, including any range or value within the range less than 20 microns), Applicants have appreciated that the handle layer of the second SOI wafer may provide sufficient structural support to allow for further processing of the engineered substrate.
At stage 106, the engineered substrate may be bonded with a CMOS wafer having integrated circuitry to form an integrated device. The bonding may be performed at temperatures below 450° C. to prevent damage to the circuitry of the CMOS wafer. In some embodiments, thermocompression bonding is used, although alternatives including eutectic bonding and silicide bonding are also possible, among others. The silicon device layer of the first SOI wafer may be arranged proximate the bonding surface of the CMOS wafer, for example by bonding a backside of the silicon device layer of the first SOI wafer with the CMOS wafer. Thus, the resulting structure may include, in order, a CMOS wafer, a first silicon device layer, a second silicon device layer of the second SOI wafer, and the handle layer of the second SOI wafer.
At stage 108, the handle layer of the second SOI wafer of the engineered substrate may be removed, in any suitable manner, for example by a combination of grinding followed by etching. As a result, in some embodiments, the engineered substrate may include only two silicon layers (the two silicon device layers of the SOI wafers used to form the engineered substrate) between which are the cavities. Having only two silicon layers may, among other benefits, facilitate achieving thin dimensions for the engineered substrate. For example, the engineered substrate at this stage may be relatively thin, for example being less than 100 microns in total thickness, less than 50 microns in total thickness, less than 30 microns in total thickness, less than 20 microns in total thickness, less than 10 microns in total thickness (e.g., approximately 8 microns or approximately 5 microns), or any other suitable thickness. Structures with such small thicknesses lack sufficient structural rigidity to survive many fabrication processes, including wafer bonding. Thus, according to some embodiments of the present application, the engineered substrate is not reduced to such dimensions until after bonding with the CMOS wafer, which can provide mechanical support to the engineered substrate. Moreover, as described further below in connection with
Electrical connections may be made between the ICs on the CMOS wafer and the sealed cavities of the engineered substrate to provide functioning ultrasonic transducers. For example, the silicon device layer of the engineered substrate proximate the CMOS wafer may serve as a bottom electrode for the ultrasonic transducers while the silicon device layer distal the CMOS wafer may serve as a membrane, and electrical connections may be made to these structures as appropriate to control operation of the membrane (e.g., to actuate (or induce vibration of) the membrane by applying a voltage). In some embodiments, electrical connection may be made (or may be at least partially completed) by the bonding of stage 106. For example, bonding the engineered substrate with the CMOS wafer may involve using conductive bonding materials (e.g., metals) which serve as both bonding materials and electrical connections. Alternatively, or additionally, electrical connections may be made subsequent to bonding of the engineered substrate with the CMOS wafer. For example, bonding the engineered substrate with the CMOS wafer may form electrical connections to a bottom electrode of the ultrasonic transducer, and on-chip metal interconnect and/or wire bonds may be formed subsequently to provide electrical connection to top electrodes or membrane of the ultrasonic transducer.
At stage 204, cavities may be formed in the thermal oxide of the first SOI wafer, for example by any suitable etching. In some embodiments, the cavities do not completely reach the silicon device layer, such that a (thin) layer of oxide defines the cavity boundaries. However, in other embodiments the cavities may extend to the surface of the silicon device layer or further. In some embodiments, the thermal oxide may be etched to the surface of the silicon device layer and then an additional layer of thermal oxide may be formed such that the cavities are defined by a layer of oxide.
At stage 206, the first SOI wafer, having the cavities formed in the thermal oxide thereon, may be bonded with a second SOI wafer, for example using a low temperature fusion bond. In some embodiments, the second SOI wafer includes a handle layer (e.g., a handle silicon layer), a BOX layer, and a silicon device layer, and the bonding involves making direct contact between the thermal oxide layer of the first SOI wafer and the silicon device layer of the second SOI wafer, thus forming a Si—SiO2 bond. In an alternative embodiment, the second SOI wafer may include an oxide layer on the silicon device layer, such that bonding the first and second SOI wafers together may involve making direct contact with oxide layers of the two SOI wafers, thus forming a SiO2—SiO2 bond.
As a result of bonding the two SOI wafers together, the cavities in the first SOI wafer may be sealed. For example, the cavities may be vacuum sealed in some embodiments, although in other embodiments a vacuum seal may not be formed.
At stage 208, an anneal may be performed to facilitate formation of a strong bond between the two SOI wafers. As described previously, in some embodiments the anneal may be a high temperature anneal, for example being performed between approximately 500° C. and approximately 1,500° C. (e.g., 500° C., 750° C., 1,000° C., 1,250° C.), including any temperature or range of temperatures within that range (e.g., between approximately 500° C. and approximately 1,200° C.), although other temperatures may alternatively be used. In some embodiments, an anneal may be performed between approximately 300° C. and approximately 1,200° C.
The device 300 includes an engineered substrate 302 integrated with a CMOS wafer 304. The engineered substrate 302 includes a plurality of cavities 306 formed between a first silicon device layer 308 and a second silicon device layer 310. A silicon oxide layer 312 (e.g., a thermal silicon oxide—a silicon oxide formed by thermal oxidation of silicon) may be formed between the first and second silicon device layers 308 and 310, with the cavities 306 being formed therein. In this non-limiting example, the first silicon device layer 308 may be configured as a bottom electrode and the second silicon device layer 310 may be configured as a membrane. Thus, the combination of the first silicon device layer 308, second silicon device layer 310, and cavities 306 may form an ultrasonic transducer (e.g., a CMUT), of which six are illustrated in this non-limiting cross-sectional view. To facilitate operation as a bottom electrode or membrane, one or both of the first silicon device layer 308 and second silicon device layer 310 may be doped to act as conductors, and in some cases are highly doped (e.g., having a doping concentration greater than 1015 dopants/cm3 or greater).
The engineered substrate 302 may further include an oxide layer 314 on top of the second silicon device layer 310, which may represent the BOX layer of an SOI used to form the engineered substrate. The oxide layer 314 may function as a passivation layer in some embodiments and, as shown, may be patterned to be absent over the cavities 306. Contacts 324, described further below, and passivation layer 330 may be included on the engineered substrate. The passivation layer 330 may be patterned to allow access to one or more contacts 324, and may be formed of any suitable passivating material. In some embodiments, the passivation layer 330 is formed of Si3N4 and in some embodiments is formed by a stack of SiO2 and Si3N4, although alternatives are possible.
The engineered substrate 302 and CMOS wafer 304 may be bonded together at bond points 316a and 316b. The bond points may represent eutectic bond points, for example formed by a eutectic bond of a layer on engineered substrate 302 with a layer on CMOS wafer 304, or may be any other suitable bond type described herein (e.g., a silicide bond or thermocompression bond). In some embodiments, the bond points 316a and 316b may be conductive, for example being formed of metal. The bond points 316a may function solely as bond points in some embodiments, and in some embodiments may form a seal ring, for example hermetically sealing the ultrasonic transducers of the device 300 as described further below in connection with
The CMOS wafer 304 includes a base layer (e.g., a bulk silicon wafer) 318, an insulating layer 320, and a metallization 322. The metallization 322 may be formed of aluminum, copper, or any other suitable metallization material, and may represent at least part of an integrated circuit formed in the CMOS wafer. For example, metallization 322 may serve as a routing layer, may be patterned to form one or more electrodes, or may be used for other functions. In practice, the CMOS wafer 304 may include multiple metallization layers and/or post-processed redistribution layers, but for simplicity only a single metallization is illustrated.
The bond points 316b may provide electrical connection between the metallization 322 of CMOS wafer 304 and the first silicon device layer 308 of the engineered substrate. In this manner, the integrated circuitry of the CMOS wafer 304 may communicate with (e.g., send electrical signals to and/or receive electrical signals from) the ultrasonic transducer electrodes and/or membranes of the engineered substrate. In the illustrated embodiments, a separate bond point 316b is illustrated as providing electrical connection to each sealed cavity (and therefore for each ultrasonic transducer), although not all embodiments are limited in this manner. For example, in some embodiments, the number of electrical contacts provided may be less than the number of ultrasonic transducers.
Electrical contact to the ultrasonic transducer membranes represented by second silicon device layer 310 is provided in this non-limiting example by contacts 324, which may be formed of metal or any other suitable conductive contact material. In some embodiments, an electrical connection may be provided between the contacts 324 and the bond pad 326 on the CMOS wafer. For example, a wire bond 325 may be provided or a conductive material (e.g., metal) may be deposited over the upper surface of the device and patterned to form a conductive path from the contacts 324 to the bond pad 326. However, alternative manners of connecting the contacts 324 to the IC on the CMOS wafer 304 may be used. In some embodiments an embedded via may be provided from the first silicon device layer 308 to a bottom side of the second silicon device layer 310, thus obviating any need for the contacts 324 on the topside of the second silicon device layer 310. An example is described below in connection with
The device 300 also includes isolation structures (e.g., isolation trenches) 328 configured to electrically isolate groups of ultrasonic transducers (referred to herein as “ultrasonic transducer elements”) or, as shown in
Various features of the device 300 are now noted. For instance, it should be appreciated that the engineered substrate 302 and CMOS wafer 304 wafer may be monolithically integrated, thus providing for monolithic integration of ultrasonic transducers with CMOS ICs. In the illustrated embodiment, the ultrasonic transducers are positioned vertically (or stacked) relative to the CMOS IC, which may facilitate formation of a compact ultrasound device by reducing the chip area required to integrate the ultrasonic transducers and CMOS IC.
Additionally, the engineered substrate 302 includes only two silicon layers 308 and 310, with the cavities 306 being formed between them. The first silicon device layer 308 and second silicon device layer 310 may be thin, for example each being less than 50 microns in thickness, less than 30 microns in thickness, less than 20 microns in thickness, less than 10 microns in thickness, less than 5 microns in thickness, less than 3 microns in thickness, or approximately 2 microns in thickness, among other non-limiting examples. Such dimensions contribute to achieving a small device and may facilitate making electrical contact to the ultrasonic transducer membrane (e.g., second silicon device layer 310) without the need for TSVs. TSVs are typically complicated and costly to implement, and thus avoiding use of them may increase manufacturing yield and reduce device cost. Moreover, forming TSVs requires special fabrication tools not possessed by many commercial semiconductor foundries, and thus avoiding the need for such tools can improve the supply chain for forming the devices, making them more commercially practical than if TSVs were used.
The engineered substrate 302 as shown in
Also, the silicon device layers 308 and 310 may be formed of single crystal silicon. The mechanical and electrical properties of single crystal silicon are understood, and thus the use of such materials in an ultrasonic transducer (e.g., as the membrane of a CMUT) may facilitate design and control of the ultrasonic transducer behavior.
Another feature worth noting is that there is a gap between parts of the CMOS wafer 304 and the first silicon device layer 308 since the two are bonded at discrete bond points 316b rather than by a bond covering the entire surface of the CMOS wafer 304. The significance of this gap is that the first silicon device layer 308 may vibrate if it is sufficiently thin. Such vibration may be undesirable, for instance representing unwanted vibration in contrast to the desired vibration of the second silicon device layer 310. Accordingly, it is beneficial in at least some embodiments for the first silicon device layer 308 to be sufficiently thick to minimize or avoid such vibration.
In alternative embodiments, it may be desirable for both the first and second silicon device layers 308 and 310 to vibrate. For instance, they may be constructed to exhibit different resonance frequencies, thus creating a multi-frequency device. The multiple resonance frequencies (which may be related as harmonics in some embodiments) may be used, for example, in different operating states of an ultrasound transducer. For example, the first silicon device layer 308 may be configured to resonant at half the center frequency of the second silicon device layer 310.
Initially, the formation of the engineered substrate is described, beginning as shown in
The first silicon device layer 308 may be formed of single crystal silicon and, as previously described, may be doped in some embodiments. As previously described in connection with
In some embodiments, the first silicon device layer 308 may be formed of polysilicon or amorphous silicon. In either case the first silicon device layer 308 may be doped or not as appropriate to provide desired electrical behavior.
As shown in
As shown in
Any suitable number and configuration of cavities 306 may be formed, as the aspects of the application are not limited in this respect. Thus, while only six cavities 306 are illustrated in the non-limiting cross-sectional view of
The cavities 306 may have a depth D designed for desired operation of the ultrasonic transducers ultimately formed, for example in terms of frequency of operation. In some embodiments, the depth D may be approximately 2 microns, approximately 0.5 microns, approximately 0.25 microns, between approximately 0.05 microns and approximately 10 microns, between approximately 0.1 microns and approximately 5 microns, between approximately 0.5 microns and approximately 1.5 microns, any depth or range of depths in between, or any other suitable depth.
The cavities 306 may have a width W, also illustrated in
The cavities 306 may take one of various shapes (viewed from a top side) to provide a desired membrane shape when the ultrasonic transducers are ultimately formed. For example, the cavities 306 may have a circular contour or a multi-sided contour (e.g., a rectangular contour, a hexagonal contour, an octagonal contour). An example of a circular contour is illustrated in
As shown in
As with the first silicon device layer 308, the second silicon device layer 310 may be single crystal silicon, polysilicon, or amorphous silicon, and may be doped in some embodiments. The doping may avoid the need to form TSVs to provide electrical connectivity, and may be of any suitable type and level.
As shown in
Then, as shown in
As previously described in reference to isolation structures 328 of
In
As shown in
In
Bonding material 426 may then be formed on the engineered substrate in preparation for bonding the engineered substrate with a CMOS wafer, as shown in
As shown in
In
As shown in
In the non-limiting example illustrated, the bond may be a eutectic bond, such that the bonding material 426 and bonding material 436 may in combination form bond points 316a and 316b. As a further non-limiting example, a thermocompression bond may be formed using Au as the bonding material. For instance, the bonding material 426 may include a seed layer (formed by sputtering or otherwise) of Ti/TiW/Au with plated Au formed thereon, and the bonding material 436 may include a seed layer (formed by sputtering or otherwise) of TiW/Au with plated Ni/Au formed thereon. The layers of titanium may serve as adhesion layers. The TiW layers may serve as adhesion layers and diffusion barriers. The nickel may serve as a diffusion barrier. The Au may form the bond. Other bonding materials may alternatively be used.
Next, the second handle layer 410 and oxide layer 414 may be removed in any suitable manner as shown in
As shown in
The device 300 may then be achieved by depositing and patterning the passivation layer 330. As described previously in connection with
Various features of the fabrication sequence of
Additionally, the process does not utilize chemical mechanical polishing (CMP). For example, CMP is not used in preparation for either of the bonding stages described, and thus the bonding reliability (and therefore yield) may be increased while cost may be decreased compared to if CMP steps were performed. Similarly, it is noteworthy that the illustrated fabrication sequence does not include any densification anneals for the low temperature bond of the engineered substrate with the CMOS wafer. The use of such anneals reduces bonding reliability and therefore yield. Further still, and as previously described, the fabrication of the sealed cavities for the ultrasonic transducers is decoupled from the CMOS thermal budget, thus allowing for use of high temperature processing (e.g., a high temperature anneal) when bonding together the wafers of the engineered substrate.
The process for forming the sealed cavities 306 may also facilitate forming cavities of desired dimensions and spacing. For example, the cavities 306 may have widths W (see
The spacing between cavities 306 may also be made small despite the fact that the amount of space between cavities 306 impacts the bondable area when forming the engineered substrate. That is, the smaller the distances are between the cavities 306 the less bonding surface is available which increases the difficulty of bonding. However, the processes of forming the engineered substrate described herein in connection with
The device 300 may be further packaged and/or encapsulated in some embodiments. For example, as shown by the packaged device 500 in
The clear out region 424, previously described in connection with
Alternatives to the fabrication sequence of
From the foregoing, it should be appreciated that the method of
One or both of the two wafers used in stage 702 may have a plurality of cavities formed therein, such that bonding the two wafers together may result in sealed cavities suitable for use as the cavities of CMUTs. To ensure a strong bond between the two wafers, high temperature processing may be used. For example, a high temperature anneal may be used subsequent to a low temperature wafer bond, such as a low temperature fusion bond. Thus, a combination of high and low temperatures may be used in forming the engineered substrate in some embodiments. As described in connection with
At stage 704, the thickness of the first wafer is altered. If the first wafer is an SOI wafer, then a handle layer of a first wafer is removed. If the first wafer is instead a bulk silicon wafer, then it may be thinned, for example by etching. A timed etch may be used or the bulk silicon wafer may include a doping gradation functioning as an etch stop, as described previously herein.
As a result of stage 704, the first wafer may have a relatively small thickness. For example, the thickness of the first wafer after stage 704 may be less than 50 microns, less than 30 microns, less than 20 microns, or less than 10 microns. As will be described further below, the first wafer will, in some embodiments, subsequently be bonded with a CMOS wafer such that it is disposed between the CMOS wafer and the second wafer. A gap may exist between the first wafer and the CMOS wafer in the manner described previously with respect to the gap between CMOS wafer 304 and first silicon device layer 308 of
At stage 706, the engineered substrate may be bonded with a CMOS wafer having integrated circuitry to form an integrated device, in the same manner described in connection with stage 106 of
At stage 708, the thickness of the second wafer is altered. If the second wafer is an SOI wafer, then the handle layer of the second wafer of the engineered substrate is removed, in any suitable manner, for example by a combination of grinding followed by etching. If the second wafer is instead a bulk silicon wafer, then it may be thinned, for example by etching. A timed etch may be used or the bulk silicon wafer may include a doping gradation functioning as an etch stop.
As with the method 100 of
Electrical connections may be made between the ICs on the CMOS wafer and the sealed cavities of the engineered substrate to provide functioning ultrasonic transducers in the same manner described in connection with
In accordance with the method 700, an alternative to the fabrication sequence of
The bulk silicon wafer with cavities may then be bonded with an SOI wafer, such as SOI wafer 408. Thus, the present embodiment may differ from the structure of
Thereafter, processing in the present embodiment may proceed in the same manner as illustrated in
Yet another alternative to the fabrication sequence of
Next, as shown in
Next, as shown in
Thereafter, fabrication may proceed in substantially the same manner as shown with respect to
Various parameters associated with the device may be selected to optimize performance of the device. Examples of such parameters include the depth D of the cavities (determined by the thickness of silicon oxide layer 312 in the non-limiting embodiment of
Another alternative to the fabrication sequence of
The device 900 of
One suitable doping scheme is for regions 902 to be lightly doped N-type, regions 904 to be heavily doped P-type, and regions 906 to be lightly doped P-type. However, in an alternative embodiment regions 902 may be lightly doped P-type, regions 904 may be heavily doped N-type, and regions 906 may be lightly doped N-type. Under either scenario, boron may serve as the P-type dopant and phosphorous or arsenic may serve as the N-type dopant, although are alternatives are possible. The doping concentrations of the regions 902, 904, and 906 may be selected to provide desired electrical behavior.
The doping of regions 902, 904, and 906 may be created in any suitable manner. According to some embodiments, a combination of ion implantation and diffusion (e.g., via high temperature anneal) may be used. As shown in
The sizing of the regions 902, 904, and 906 may be selected to provide desired electrical behavior. For example, the sizing may be optimized to reduce parasitic capacitance, for example between distinct electrode regions 904. Since regions 904 represent electrode regions corresponding to the cavities 306, they may be sized to provide a desired electrode size. For example, the regions 904 may have widths substantially equal to the width W of the cavities 306, although in alternative embodiments regions 904 may have a smaller width than the width W of the cavities (see
As previously described, the regions 906 are optional and thus may be omitted in some embodiments. The regions 906 may reduce dead capacitance between the electrode regions 904, and thus when included may have any suitable sizing to perform such a function. For example, in some embodiments the regions 904 may be relatively large compared with the widths of the electrode regions 904. Thus, the locations of regions 904 and 906 may be controlled to provide desired sizing and spacing relative to the cavities 306.
The regions 902 may be electrically connected to any suitable voltage. In some embodiments, the regions 902 may be floating. In other embodiments, the regions 902 may be tied to a bias voltage. For example, regions 902 may be electrically grounded when doped P-type, or may be tied to a high voltage (e.g., a high voltage rail) when doped N-type. In some embodiments, the regions 902 may be tied to a voltage between approximately 20-300 Volts (e.g., between approximately 30-120 Volts, between approximately 50-250 Volts, between approximately 60-90 Volts, or any value or any range of values within these ranges) as may be used in the context of ultrasound imaging applications, as a non-limiting example. In some embodiments, the regions 902 may be biased at the same (or substantially the same) voltage as used to bias the second silicon device layer 310 serving as a membrane for the ultrasonic transducers.
While
In those embodiments in which both the first and second silicon device layers 308 and 310 are doped, the relative doping between the two layers may be selected to provide desirable electrical behavior. For example, regions 904 and the second silicon device layer 310 may be oppositely doped and doped to different concentrations to amplify a bias voltage. For example, the regions 904 may be doped P+ and the second silicon device layer 310 may be doped N—. Such a configuration may produce an extra voltage drop across the cavities 306 (e.g., on the order of 1 Volt) arising from the different work functions of the N and P doping. If the regions 904 are doped N-type, it may be advantageous to also dope the second silicon device layer 310 N-type to avoid losing a voltage drop due to the work functions.
A further alternative to the fabrication sequence of
A further alternative relates to the manner of making electrical contact to the second silicon device layer 310. As described previously, in the embodiment of
It should be appreciated that the via 1002 is not a traditional TSV because the thickness through which it passes, namely the thickness of the second silicon device layer 310, the silicon oxide layer 312, and the first silicon device layer 308 may be relatively small, for example having any of the dimensions previously described herein with respect to such structures.
As a further alternative, the via 1002 representing an embedded contact may not pass through the second silicon device layer 310, but rather may extend between the bond point 316a and the bottom side of the second silicon device layer 310 proximate the cavity 306, while again being insulated from the first silicon device layer 308 by a suitable insulating feature (e.g., an insulating liner). An example is illustrated in
In a configuration like that in
A further alternative to the device 300 combines features of the devices of
A further alternative to the device 300 and fabrication sequence of
The device 1200 is similar to the device 300 of
The openings 1202 and/or 1204 may be formed in any suitable manner and at any suitable stage of processing of the device 300. For example, the openings 1202 and/or 1204 may be formed after the fabrication stage illustrated in
The presence of openings 1202 and/or 1204 may impact the loss and stiffening of the ultrasonic transducers, and ultimately the frequency of operation. For example, the openings 1202 and/or 1204 will result in the device acting more as a broadband device than if the openings were not included, and result in improved ranging behavior. The size of the openings 1202 and/or 1204 impacts the frequency characteristics, and in some embodiments may be selected to match a Helmholtz resonance frequency for the device 1200.
Thus, openings 1202 and/or 1204 may be beneficial to providing desired ultrasonic transducer frequency characteristics. For example, openings 1202 and/or 1204 may facilitate achieving desired frequency behavior for the ultrasonic transducers in open-air applications (lacking a transducing medium).
In some embodiments, the isolation structures 328 may have a multi-sided contour. For example, an octagonal contour is shown in
A further alternative to the device 300 and fabrication sequence of
In some embodiments, a wafer having TSVs may be used in forming an engineered substrate.
An embodiment involving use of a wafer with TSVs, as just described in connection with
The aspects of the present application may provide one or more benefits, some of which have been previously described. Now described are some non-limiting examples of such benefits. It should be appreciated that not all aspects and embodiments necessarily provide all of the benefits now described. Further, it should be appreciated that aspects of the present application may provide additional benefits to those now described.
Aspects of the present application provide manufacturing processes suitable for formation of monolithically integrated ultrasonic transducers and CMOS structures (e.g., CMOS ICs). Thus, single substrate devices operating as ultrasound devices (e.g., for ultrasound imaging and/or high intensity focused ultrasound (HIFU)) are achieved.
In at least some embodiments, the processes may be reliable (e.g., characterized by high yield and/or high device reliability), scalable to large quantities, and relatively inexpensive to perform, thus contributing to a commercially practical fabrication process for CUTs. The use of complex and costly processing techniques such as the formation of TSVs, the use of CMP, and the use of densification anneals of low temperature oxide bonds may be avoided. Moreover, the processes may provide for the fabrication of small ultrasound devices, facilitating the creation of portable ultrasound probes.
Having thus described several aspects and embodiments of the technology of this application, it is to be appreciated that various alterations, modifications, and improvements will readily occur to those of ordinary skill in the art. Such alterations, modifications, and improvements are intended to be within the spirit and scope of the technology described in the application. For example, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the function and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the embodiments described herein. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described. In addition, any combination of two or more features, systems, articles, materials, kits, and/or methods described herein, if such features, systems, articles, materials, kits, and/or methods are not mutually inconsistent, is included within the scope of the present disclosure.
As a non-limiting example, various embodiments have been described as including CMUTs. In alternative embodiments, PMUTs may be used instead of, or in addition to, CMUTs.
Also, as described, some aspects may be embodied as one or more methods. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.
All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and/or ordinary meanings of the defined terms.
The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.”
The phrase “and/or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and/or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Elements other than those specifically identified by the “and/or” clause may optionally be present, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and/or B”, when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.
As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and/or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.
Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having,” “containing,” “involving,” and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items.
In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of” and “consisting essentially of” shall be closed or semi-closed transitional phrases, respectively.
This application is a continuation, claiming the benefit under 35 U.S.C. § 120, of U.S. application Ser. No. 16/109,703, entitled “Microfabricated Ultrasonic Transducers and Related Apparatus and Methods”, filed Aug. 22, 2018, which is herein incorporated by reference in its entirety. U.S. patent application Ser. No. 16/109,703 is a continuation, claiming the benefit under 35 U.S.C. § 120, of U.S. application Ser. No. 15/689,863, entitled “Microfabricated Ultrasonic Transducers and Related Apparatus and Methods,” filed on Aug. 29, 2017, which is herein incorporated by reference in its entirety. U.S. patent application Ser. No. 15/689,863 is a continuation, claiming the benefit under 35 U.S.C. § 120, of U.S. application Ser. No. 15/648,187, entitled “Microfabricated Ultrasonic Transducers and Related Apparatus and Methods,” filed on Jul. 12, 2017, which is herein incorporated by reference in its entirety. U.S. patent application Ser. No. 15/648,187 is a continuation, claiming the benefit under 35 U.S.C. § 120, of U.S. application Ser. No. 15/177,899, entitled “Microfabricated Ultrasonic Transducers and Related Apparatus and Methods,” filed on Jun. 9, 2016, which is herein incorporated by reference in its entirety. U.S. patent application Ser. No. 15/177,899 is a continuation, claiming the benefit under 35 U.S.C. § 120, of U.S. patent application Ser. No. 14/716,152 entitled “Microfabricated Ultrasonic Transducers and Related Apparatus and Methods,” filed May 19, 2015, which is incorporated herein by reference in its entirety. U.S. patent application Ser. No. 14/716,152 is a continuation, claiming the benefit under 35 U.S.C. § 120, of U.S. patent application Ser. No. 14/635,197 entitled “Microfabricated Ultrasonic Transducers and Related Apparatus and Methods,” filed Mar. 2, 2015, which is incorporated herein by reference in its entirety. U.S. patent application Ser. No. 14/635,197 claims the benefit under 35 U.S.C. § 119(e) of U.S. Provisional Patent Application Ser. No. 62/024,179 filed Jul. 14, 2014, and entitled “Microfabricated Ultrasonic Transducers and Related Apparatus and Methods,” which is incorporated herein by reference in its entirety.
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| WO 2012017978 | Feb 2012 | WO |
| WO 2014151525 | Sep 2014 | WO |
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| Number | Date | Country | |
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| 20200400620 A1 | Dec 2020 | US |
| Number | Date | Country | |
|---|---|---|---|
| 62024179 | Jul 2014 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 16109703 | Aug 2018 | US |
| Child | 16986067 | US | |
| Parent | 15689863 | Aug 2017 | US |
| Child | 16109703 | US | |
| Parent | 15648187 | Jul 2017 | US |
| Child | 15689863 | US | |
| Parent | 15177899 | Jun 2016 | US |
| Child | 15648187 | US | |
| Parent | 14716152 | May 2015 | US |
| Child | 15177899 | US | |
| Parent | 14635197 | Mar 2015 | US |
| Child | 14716152 | US |
