Patent Application
20220208765
The present invention is related to a semiconductor technology, and specifically, related to a structure of multi-bit storage in power MOS (and IGBT), methods of making the same, and simultaneous read methods.
Multiple-valued logic (MVL) (or multi-bit) transistor, which has two or more possible threshold voltages (Vt's) for logical calculation, may be used for applications, for example a method of solving the binary problems more effectively, and the designing of electrical circuits (by using multi-bit transistors) in multiple-threshold-voltage (multi-Vt) memory, arithmetic circuitry, field programmable gate array (FPGA), etc.
MVL circuit has been implemented with bipolar technologies (e.g. integrated injection logic (IIL), emitter-coupled logic (ECL)), and metal-oxide-semiconductor (MOS) technology (e.g. Charge-coupled device (CCD), metal-oxide-semiconductor field-effect transistor (MOSFET), fin-type field-effect transistor (FINFET), multi-Vt memory (flash, DRAM, NAND, RRAM)), and others (e.g. single electron transistor (SET), carbon nanotube field-effect transistor (CNTFET), etc.)
Please refer to
However, although multi-Vt logic transistors are more effective and faster than conventional binary logic transistors, the complexity and cost to make multi-Vt logic transistors are higher. Further, the current multi-level or multi-Vt logic MOS transistors may be used for multi-level logic computing or high density memory storage, but seldom for vertical power MOS devices (for storing useful information in power circuits).
Therefore, it is needed to develop a structure of multi-bits storage in power MOS (and IGBT), methods of making the same, and simultaneous read methods for digital information storage without process complexity.
In one aspect of the invention, an embodiment of the invention is provided that a vertical power MOSFET (or VDMOSFET) with built-in multiple threshold voltage (or multi-Vt) can provide capability of information storage, a method of making the same, and a simultaneous read method without process complexity and cost.
A multi-Vt vertical power MOSFET device may comprise: an epitaxial layer of a first conductivity type; a well region of a second conductivity type, the well region of the second conductivity type being within the epitaxial layer of the first conductivity type; a source region of the first conductivity type, the source region of the first conductivity type being within the well region of the second conductivity type; trench gate structure, the trench gate structure comprising a gate dielectric layer and a gate conductive layer, the trench gate structure being within the epitaxial layer of the first conductivity type and passing through the source region of the first conductivity type and the well region of the second conductivity type; and contact structures, passing through the source region of the first conductivity type to be in mutual contact with the well region of the second conductivity type, and comprising a contact portion of the second conductivity type; wherein the contact structures form a contact structure array, the contact structure array has a shared trench gate structure, the contact structure array is constructed by a plurality of sets of the contact structures, each of the sets of the contact structures comprises at least two contact structures, and in the contact structure array, the same traversal gaps (or spacing) are formed between an edge of the contact portion of the second conductivity type of the same set of the contact structures and an edge of a trench, and different traversal gaps are formed between an edge of the contact portion of the second conductivity type of the different sets of the contact structures and an edge of a trench.
Optionally, the contact portions of the second conductivity type of all sets of the contact structures within one multi-Vt transistor have the same doping concentration; and the contact portions of the second conductivity type of the contact structures in different (or separate) multi-Vt transistor may have different doping concentration.
Optionally, in the contact structure array, the doping concentration within the traversal gap of the contact portions of the second conductivity type of their respective sets of the contact structures may decrease along with increment of the traversal gaps. Or reversely, the doping concentration within the traversal gap of the contact portions of the second conductivity type increases along with a decrease of the traversal gap.
Optionally, the contact structures may comprise the contact portion of the second conductivity type within the well region of the second conductivity type and a metal contact portion passing through the source region of the first conductivity type and being in mutual contact with the contact portion of the second conductivity type.
Optionally, a shape of the contact structures may comprise one or a combination of square and rectangle, and a shape of the trench gate structure may comprise one or a combination of square and rectangle.
Optionally, the first conductivity type may be n type, and the second conductivity type may be p type; or the first conductivity type may be p type, and the second conductivity type may be n type.
Optionally, the multi-Vt vertical power device may comprise a multi-Vt vertical MOSFET (or VDMOSFET) or a multi-Vt vertical IGBT and store digital information in the multi-Vt power devices.
A method of making a multi-Vt vertical power device may comprise steps of: providing a semiconductor substrate, the semiconductor substrate comprising an epitaxial layer of a first conductivity type, a well region of a second conductivity type, a source region of the first conductivity type and trench gate structure; wherein the well region of the second conductivity type is positioned in the epitaxial layer of the first conductivity type, the source region of the first conductivity type is positioned in the well region of the second conductivity type, the trench gate structure comprises a gate dielectric layer and a gate conductive layer, the trench gate structure is within the epitaxial layer of the first conductivity type, and passing through the source region of the first conductivity type and the well region of the second conductivity type; and forming a contact mask on the semiconductor substrate and forming contact structures in the semiconductor substrate through the contact mask, the contact structures passing through the source region of the first conductivity type to be in mutual contact with the well region of the second conductivity type, and the contact structures comprising the contact portion of the second conductivity type; wherein the contact structures form a contact structure array, the contact structure array has a shared trench gate structure, the contact structure array is constructed by a plurality of sets of the contact structures, each of the sets of the contact structures comprises at least two contact structures, and in the contact structure array, the same traversal gaps (spacings) are formed between an edge of the contact portion of the second conductivity type of the same set of the contact structures and an edge of a trench, and different traversal gaps are formed between an edge of the contact portion of the second conductivity type of the different sets of the contact structures and an edge of a trench.
Optionally, in the contact structure array, the contact portions of the second conductivity type of the same set of the contact structures in one multi-Vt transistor have the same doping concentration; and the contact portions of the second conductivity type of the contact structures in different (or separate) multi-Vt transistors may have different doping concentration.
Optionally, the step of forming contact structures may comprise: through the contact mask, etching the source region of the first conductivity type to form a the contact trench passing through the source region of the first conductivity type; through the contact mask, implanting a dopant of the second conductivity type in the well region of the second conductivity type to form the contact portion of the second conductivity type; and through the contact mask, forming a metal contact portion filling the contact trench and being in mutual contact with the contact portion of the second conductivity type.
Optionally, the first conductivity type may be n type, and the second conductivity type may be p type; or the first conductivity type may be p type, and the second conductivity type may be n type; the multi-Vt vertical power device may comprise a multi-Vt vertical power MOSFET or a multi-Vt vertical IGBT to store digital information in Vt of the multi-Vt vertical power device.
Optionally, the step of providing a semiconductor substrate may comprise: forming the epitaxial layer of the first conductivity type; forming the trench gate structure in the epitaxial layer of the first conductivity type, the trench gate structure comprising the gate dielectric layer and the gate conductivity layer; through a well region mask, forming the well region of the second conductivity type in the epitaxial layer of the first conductivity type which is between the trench gate structure; and through a source region mask, forming the source region of the first conductivity type in the well region of the second conductivity type.
A simultaneous reading method for reading multiple-threshold-voltage (multi-Vt) simultaneously may comprise steps of: providing a multi-Vt vertical power device; biasing device in a saturation mode (i.e. Vd is large>10V): a gate voltage (Vg) of a shared gate is scanned with a scanning range for all threshold voltages Vt's in the device, when each threshold voltage Vt is passed and the device is turned on, a corresponding drain current (Id) shows a step of increases and a transconductance shows a peak, a bit of “1” is represented (or detected), but when Id fails to show an increment and the transconductance fails to show a peak, a bit of “0” is represented; and biasing power device in a linear mode (e.g. Vd is small <2v): a gate voltage (Vg) of a shared gate is scanned with a scanning range for all threshold voltages Vt's, when each threshold voltage Vt is passed and the device is turned on, a slope of a corresponding drain current (Id) increases and a transconductance shows an increment step, a bit of “1” is represented, but when Id fails to show an increasing slope and the transconductance fails to show the increment step, a bit of “0” is represented.
As mentioned above, the multi-Vt vertical power device providing digital information storage and the method of making the same may bring these benefits: through a contact mask, a contact structure array having a shared trench gate structure may be formed, the same traversal gaps between an edge of a contact portion of a second conductivity type of the same set and an edge of a trench may be formed in the contact structure array, and different traversal gaps between an edge of the contact portion of the second conductivity type of different sets and an edge of the trench may be formed in the contact structure array. As such, multi-Vt vertical states may be implemented for storing digital information. The present invention allows making a multi-Vt vertical power device having different Vt's to be capable for information storage without additional process steps. Therefore, number of Vt levels may vary for storing multi-bit digital information in the power device; the built-in multi-Vt power MOSFET and IGBT are adapted not only for the high power applications but also for digital information storage; simultaneous reading multi-bit information stored in the multi-Vt vertical power device is provided by scanning a voltage of a shared gate and constructing a drain current and a transconductance.
Various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawing, in which:
Reference is now made to the following concrete examples taken in conjunction with the accompanying drawings to illustrate implementation of the present invention. Persons of ordinary skill in the art having the benefit of the present disclosure will understand other advantages and effects of the present invention. The present invention may be implemented with other examples. For various view or application, details in the present disclosure may be used for variation or change for implementing embodiments within the scope of the present invention.
Please note that the drawings provided here are only for examples but not limited to the specific number or scale shown therein. When implementing the examples according to the drawings, condition, number and proportion of each element may be changed and arrangement of the elements may be in a more complex way in three-dimensional sizes such as length, width and depth. Cross-sectional views may be enlarged but not in proportion.
Please also note that terms to illustrate spatial relation used here, such as “below,” “under,” “lower than,” “on,” “above,” etc., are taken to describe a relation between an element or feature and other element(s) or feature(s). It is readily to be understood that such terms comprise other direction(s) of an operating device not shown in the figures. Further, when a layer is described as being between two layers, it may be the only layer or layered along with other layer(s) between the two layers. “Between” comprises values at two ends.
Please further note that when describing a first feature is on a second feature, such description comprises an embodiment in which the first feature is in direct contact with the second feature and another embodiment in which the first feature is in indirect contact with the second feature and another feature is formed therebetween.
Please refer to
For example, the first conductivity type may be n type, and the second conductivity type may be p type; or the first conductivity type may be p type, and the second conductivity type may be n type. In the present embodiment, the first conductivity type is not limited to n type, and the second conductivity type is also not limited to p type.
For example, the multi-Vt vertical power device may comprise a multi-Vt vertical MOSFET or a multi-Vt vertical IGBT, etc. for storing digital information in the multi-Vt vertical power device.
Specifically, type and structure of the multi-Vt vertical power device may be varied to meet a requirement and associated layers may be formed accordingly. In the present embodiment, referring to
A structure of the multi-Vt vertical power device and a method of making the same according to the present embodiment are illustrated with figures as follows.
At first, a semiconductor substrate is provided. The semiconductor substrate may comprise an epitaxial layer of the first conductivity type 102, a well region of the second conductivity type 104, a source region of the first conductivity type 105 and a trench gate structure 103. The well region of the second conductivity type 104 may be positioned in the epitaxial layer of the first conductivity type 102. The source region of the first conductivity type 105 may be positioned in the well region of the second conductive type 104. The trench gate structure 103 may comprise a gate dielectric layer 1031 and a gate conductive layer 1032. The trench gate structure 103 may be positioned in the epitaxial layer of the first conductivity type 102, and passing through the source region of the first conductive type 105 and the well region of the second conductivity type 104, so as to form a vertical dual channel layer 107 next to the physical edge of trench. It is readily to be understood that only one unit of the multi-Vt vertical power device is shown in
For example, steps to make the semiconductor substrate may comprise: providing the substrate of the first conductivity type 101; forming the epitaxial layer of the first conductivity type 102 on the substrate of the first conductivity type 101; forming the trench gate structures 103 in the epitaxial layer of the first conductivity type 102, in which the trench gate structures 103 may comprise the gate dielectric layer 1031 and the gate conductivity layer 1032; through a well region mask, forming the well region of the second conductivity type 104 in the epitaxial layer of the first conductivity type 102 which is between the trench gate structures 103; through a source region mask, forming the source region of the first conductivity type 105 in the well region of the second conductivity type 104.
Please note that above-mentioned steps to form the semiconductor substrate and structure of the semiconductor substrate may not be limited to the disclosure but may be varied to meet a requirement.
Specifically, when providing the substrate of the first conductivity type 101, material of the substrate of the first conductivity type 101 may be but not limited to doped semiconductor materials, such as silicon (Si), silicon-germanium (SiGe), gallium nitride (GaN) or silicon carbide (SiC), etc.
Then, on the substrate of the first conductivity type 101, the epitaxial layer of the first conductivity type 102 is grown through epitaxial (epi) growth.
Then, in the epitaxial layer of the first conductivity type 102, the trench gate structure 103 is formed, and the trench gate structure 103 comprises the gate dielectric layer 1031 and the gate conductivity layer 1032.
In the present embodiment, the trench gate structure 103 may assist in shrinking unit area of the power device. Steps to make the trench gate structure 103 may comprise: etching the epitaxial layer of the first conductivity type 102 to form the gate trench; with a thermal oxidation growth technology, a layer of the gate dielectric layer 1031 covering a bottom and a sidewall of the gate trench is grown on a surface of the gate trench; depositing polysilicon in the gate trench to form the gate conductive layer 1032; wherein the steps to make the trench gate structure 103 may not be limited to what is disclosed here, and in some other embodiment, the trench gate structure may be designed as other structures such as a split gate structure, and actual processes to make the trench gate structure are not limited.
Then, as shown in
Specifically, on a surface of the semiconductor substrate, a layer of mask material may be deposited, in which deposition technologies such as chemical vapor deposition (CVD) may be comprised, and the layer of mask material may be but not limited to silicon dioxide.
Then, on a surface of the layer of mask material, through a photolithography technology, a layer of patterned photoresist defining the contact structures may be formed, and through a dry etching technology, taking the layer of photoresist as an etching mask, the layer of mask material may be dry etched to form the contact mask having a pattern of the contact structures.
Then, through the patterned contact mask, in the source region of the first conductivity type 105, the dopant of the second conductivity type may be implanted to form the contact structures which is in mutual contact with the well region of the second conductivity type 104.
In the present embodiment, the contact structures may be formed through implanting the dopant of the second conductivity type in the source region of the first conductivity type 105. As such, the source region of the first conductivity type 105 may be in short circuit with the contact portion of the second conductive type 106 directly. However, type and structure of the contact structures may not be limited to what is disclosed here, and alternately, the contact structures may be trench contact structures, wherein steps to from the trench contact structures may comprise: through the contact mask, etching the source region of the first conductivity type 105 to form the contact trench passing through the source region of the first conductivity type 105; through the contact mask, in the well region of the second conductivity type 104, implanting the dopant of the second conductivity type to form the contact portion of the second conductivity type 106; through the contact mask, forming the metal contact portion filling the contact trench, and the metal contact portion and the contact portion of the second conductivity type 106 being in mutual contact; wherein through the trench contact structures, the contact portion of the second conductivity type 106 and the metal contact portion may be formed, the contact portion of the second conductivity type 106 may be in the well region of the second conductivity type 104 and the metal contact portion may pass through the source region of the first conductivity type 105 to be in mutual contact with the contact portion of the second conductivity type 106, and the metal contact portion may be tungsten metal (W) for reduced resistance. The trench contact structure can shrink area than the usual planar contact structures. Please note that actual choices in relation to the contact structures may be flexible and not limited to what is disclosed here.
As shown in
For example, the formed contact portion of the second conductivity type 106 in the same set of the contact structure may have the same doping concentrations, and the formed contact portion of the second conductivity type 106 in the different set of the contact structure may have different doping concentrations.
Specifically, through the different doping concentrations, effect of forming multiple Vt's may be enhanced, and actual doping concentration may not be limited here. Dopant of the contact portion of the second conductivity type 106 may comprise but not limited to boron (B), and other dopants, such as dopants with opposite conductive type, which may be chosen to meet actual needs of conductivity type and other requirement.
For example, the doping concentrations of the formed contact portion of the second conductivity type 106 in different sets of contact structure may be not limited to decreased along with increment of the traversal gaps D to further enhance the effect of forming the multiple Vt's. For instance, the doping concentrations of the contact portion of the second conductivity type 106 may be increased or randomly varied along with increment of the traversal gaps D.
For example, in the contact structure array A, the contact portion of the second conductivity type 106 in different sets of contact structure may be distributed in position, i.e. randomly distributed according to requirement, and not limited to what is disclosed here.
For example, a shape of the contact structures may comprise one or a combination of rectangle and square; a shape of the trench gate structure 103 may comprise one or a combination of rectangle and square. Thus, the sizes, shape and appearance of the contact structures and the trench gate structure 103 are not limited to what is disclosed here and may be chosen to meet requirement.
For example, the traversal gaps D between the edge of the contact portion of the second conductivity type 106 and the edge of the trench 107 in the contact structures may be within 0 μm˜3 μm, etc., but not limited to what is disclosed here. The traversal gaps D may be designed (by layout) to meet actual requirement.
For example, steps of forming an interlayered dielectric layer 108, a source metal layer 1091, a gate metal layer 1092 and the drain metal layer 1093 may be further comprised to form a multi-Vt VDMOSFET.
For example, a step of forming the buffer layer of the first conductivity type at a bottom surface of the epitaxial layer of the first conductivity type 102 may be further comprised.
Specifically, the doping concentration of the buffer layer of the first conductivity type at the back side may be between the doping concentration of the substrate of the first conductivity type 101 and the doping concentration of the epitaxial layer of the first conductivity type 102. As such, through the buffer layer of the first conductivity type, in the multi-Vt VDMOSFET, diffusion of impurity atoms the substrate of the first conductivity type 101 to the epitaxial layer of the first conductivity type 102 may be prevented during a high temperature process step. Then, a problem such as lower breakdown voltage due to raised doping concentration of the epitaxial layer of the first conductivity type 102 and tail current occurred during turning off the device may be solved.
A method of making a multi-Vt vertical IGBT is provided in the present embodiment. A major difference between the steps to make the multi-Vt VDMOSFET in
Referring to
Please note that in the above table, a minus value represents the traversal gaps D approaching (near) the trench edge 107 from a reference point, and a positive value represents the traversal gaps D apart (away) from the trench edge 107 from a reference point. Please refer to
As shown in
Specifically, the multi-Vt vertical power device may comprise the epitaxial layer of the first conductivity type 102, the well region of the second conductivity type 104, the source region of the first conductivity type 105, the trench gate structure 103 and the contact structures. The well region of the second conductivity type 104 may be positioned in the epitaxial layer of the first conductivity type 102. The source region of the first conductivity type 105 may be positioned in the well region of the second conductivity type 104. The trench gate structure 103 may comprise the gate dielectric layer 1031 and the gate conductive layer 1032. The trench gate structure 103 may be positioned in the epitaxial layer of the first conductivity type 102, and passing through the source region of the first conductivity type 105 and the well region of the second conductivity type 104. The contact structures may pass through the source region of the first conductivity type 105 to be in mutual contact with the well region of the second conductivity type 104. The contact structures may comprise the contact portion of the second conductivity type 106. The formed contact structures may construct the contact structure array A, the contact structure array A may have a shared trench gate structure 103, the contact structure array A may be constructed by a plurality of sets of the contact structure a, each of the sets of the contact structure a may comprise at least two contact structures, and in the contact structure array A, the same traversal gap D may be formed between an edge of the contact portion of the second conductivity type 106 of the same set of the contact structure a and an edge of the channel layer 107, and different traversal gaps D may be formed between an edge of the contact portion of the second conductivity type 106 of different sets of the contact structure a and an edge of the channel layer 107.
For example, the contact portion of the second conductivity type 106 of the same set of contact structure in the same multi-Vt device may have the same doping concentration, and the contact portion of the second conductivity type 106 of different set of contact structure in different multi-Vt device may have different doping concentrations.
Specifically, through the different doping concentrations, the effect of forming the multiple Vt's may be further enhanced, and the dopant of the contact portion of the second conductivity type 106 may comprise B and not limited to what is disclosed here. Rather, dopants may be chosen to meet the actual conductive and requirement.
For example, in different sets of contact structure, the doping concentration of the contact portion of the second conductivity type 106 may be increased to enhance the effect of forming the multiple Vt's.
For example, in the contact structure array A, distribution of the gap of contact portion of the second conductivity type 106 may be limited to discrete for storing digital information.
For example, a shape of the contact structures may comprise one or a combination of square and rectangle, and a shape of the trench gate structure 103 may comprise one or a combination of square and rectangle. Sizes, appearance of the contact structures and the trench gate structure 103 may be chosen according to requirement and not limited to what is disclosed here.
For example, the contact structures may comprise the contact portion of the second conductivity type 106 positioned in the well region of the second conductivity type 104 and the metal contact portion passing through the source region of the first conductivity type 105 and being in mutual contact with the contact portion of the second conductivity type 106 to provide the trench contact structures, but are not limited to what is disclosed here.
For example, the first conductivity type may be n type, and the second conductivity type may be p type; or the first conductivity type may be p type, and the second conductivity type may be n type.
For example, the multi-Vt vertical power device comprising the multi-Vt vertical power MOSFET or the multi-Vt vertical IGBT, may store digital information.
The present embodiment further provides a simultaneous reading method for detecting multiple bits of digital information simultaneously may comprise steps of: providing a multi-Vt vertical power device; when device is in saturation mode (at larger Vd e.g. ˜10 v): a voltage Vg of a shared gate is scanned with a scanning range for the gate voltage (Vg) covering all threshold voltages Vt's, when each threshold voltage Vt is passed and device is turning on, a corresponding drain current (Id) increases for a step and a transconductance shows a peak value, then a bit of “1” is represented (or detected), but when Id fails to show an increment and the transconductance fails to show a peak value, a bit of “0” is represented; and when device is in a linear mode (at smaller Vd, e.g. <2v): a voltage Vg of a shared gate is scanned with a scanning range for the gate voltage (Vg) covering all threshold voltages Vt's, when each threshold voltage Vt is in on-state, a slope of a corresponding drain current (Id) increases and a transconductance shows an increment step, then a bit of “1” is represented, but when Id fails to show an increasing slope and the transconductance fails to show the increment step, a bit of “0” is represented.
Specifically, with respect to built-in separated multi-Vt's power MOSFET or IGBT, multi-bit information may be stored in power devices. Vt may be designed with gaps between the contact structures and a vertical channel. The information may be read in the way of: (1) when device in the saturation mode, the multi-Vt's may be simultaneously read with: biasing of the drain voltage (Vd) ˜10V, and scanning the gate voltage (Vg) with the scanning range covering all threshold voltages Vt's. When each time the threshold voltage Vt is passed and device turned on, the corresponding drain current (Id) in the Id-Vg curve may increase a step and a bit of “1” is represented, so as to show the peak value of the transconductance δ(Id)/δ(Vg) which shows a bit of “1”. On the contrary, if Id fails to show an increment step and the transconductance fails to show the peak value, a bit of “0” is represented. Please referring to
Please note that the multi-Vt vertical power device may comprise but may be not limited to above-mentioned multi-Vt vertical power device, and may comprise a multi-Vt vertical power device having a FinFET structure.
To sum up, according to the multi-Vt vertical power device providing digital information storage and the method of making the same of the present invention, through a contact mask, a contact structure array having a shared trench gate structure may be formed, the same traversal gaps between an edge of a contact portion of a second conductivity type of the same set and an edge of a trench may be formed in the contact structure array, and different traversal gaps between an edge of the contact portion of the second conductivity type of different sets and an edge of the trench may be formed in the contact structure array. As such, multi-Vt vertical states may be implemented for storing digital information. The present invention allows making a multi-Vt vertical power device having different Vt's to be capable of storing digital information without additional process steps. Therefore, the number of Vt levels allows storing the same number of bits digital information in the power device; the built-in multi-Vt power MOSFET and IGBT are adapted not only for the high power applications but also for information storage; simultaneous reading of multi-bit information stored in the multi-Vt vertical power device is provided by scanning a voltage of a shared gate and constructing a transconductance.
It is to be understood that these embodiments are not meant as limitations of the invention but merely exemplary descriptions of the invention. Indeed, different adaptations may be apparent to those skilled in the art without departing from the scope of the annexed claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202011627542.3 | Dec 2020 | CN | national |
