Patent Application
20180083008
The technical field generally relates to multi-time programmable (MTP) memory cells, and more particularly relates to MTP cells having reduced cell size as compared to conventional MTP cells.
Multi-time programmable (MTP) memory cells have been recently introduced for beneficial use in a number of applications where customization is required for both digital and analog designs. These applications include data encryption, reference trimming, manufacturing identification (ID), security ID, and many other applications. Incorporating MTP memory cells nonetheless also typically comes at the expense of some additional processing.
For example, some of the existing approaches to constructing MTP memories require additional masking processes to achieve sufficiently high junction breakdown voltage (BV). Also, some of the existing approaches result in MTP memories having large cell sizes due to design rule requirements. In order to achieve smaller cell sizes using existing approaches, multiple un-proven sub-design rule techniques have to be applied.
Accordingly, it is desirable to provide a simple and MTP structure that can be created with no added costs with the standard complementary metal oxide semiconductor (CMOS) structure. Further, it is desirable to provide a method for fabricating an improved MTP memory cell. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.
Multi-time programmable (MTP) memory cells, integrated circuits including MTP memory cells, and methods for fabricating MTP memory cells are provided. In an exemplary embodiment, an MTP memory cell includes a semiconductor substrate including a CMOS device region and a DMOS device region. The MTP memory cell further includes a high voltage (HV) p-well in the CMOS device region and in the DMOS device region of the semiconductor substrate. An n-channel transistor is disposed over the HV p-well in the CMOS device region and includes a transistor gate. Also, the MTP memory cell includes an n-well overlying the HV p-well in the DMOS region of the semiconductor substrate. An n-channel capacitor is disposed over the n-well and includes a capacitor gate. The capacitor gate is coupled to the transistor gate.
In another exemplary embodiment, an integrated circuit device is provided. The integrated circuit device includes a semiconductor substrate and a multi-time programmable (MTP) memory cell formed in and/or over the semiconductor substrate. The MTP memory cell includes a high voltage (HV) well of a first dopant type formed in the semiconductor substrate and a transistor disposed over the HV well and including a transistor gate. Further, the MTP memory cell includes a high voltage (HV) double-diffused region of a second dopant type formed in the HV well and a device disposed over the HV double-diffused region and including a device gate. The transistor gate is coupled to the device gate.
In yet another exemplary embodiment, a method for fabricating a multi-time programmable (MTP) memory cell is provided. The method includes providing a semiconductor substrate having a first region and a second region. The method further includes forming a high voltage (HV) p-well in the first region and in the second region of the semiconductor substrate. Also, the method includes forming a high voltage (HV) n-doped double-diffused region in the HV p-well in the second region. The method also includes forming a transistor over the HV p-well and including a transistor gate and forming a capacitor over the HV n-doped double-diffused region and including a capacitor gate. The method includes coupling the capacitor gate to the transistor gate.
This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
The various embodiments will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein:
The following detailed description is merely exemplary in nature and is not intended to limit the MTP memory cells, integrated circuits including MTP memory cells, or methods for fabricating MTP memory cells. Furthermore, there is no intention to be bound by any expressed or implied theory presented in the preceding technical field, background or brief summary, or in the following detailed description.
For the sake of brevity, conventional techniques related to conventional device fabrication may not be described in detail herein. Moreover, the various tasks and processes described herein may be incorporated into a more comprehensive procedure or process having additional functionality not described in detail herein. In particular, various processes in the fabrication of memory cells are well-known and so, in the interest of brevity, many conventional processes will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details. Further, it is noted that memory cells and devices having memory cells include a varying number of components and that single components shown in the illustrations may be representative of multiple components.
As used herein, it will be understood that when an element or layer is referred to as being “over” or “under” another element or layer, it may be directly on the other element or layer, or intervening elements or layers may be present. When an element or layer is referred to as being “on” another element or layer, it is directly on and in contact with the other element or layer. Further, spatially relative terms, such as “upper”, “over”, “lower”, “under” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being “under” other elements or features would then be oriented “above” the other elements or features. Thus, the exemplary term “under” can encompass either an orientation of above or below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
As described herein, an exemplary MTP memory cell is formed with a Transistor plus Capacitor (1T+1C) structure and, accordingly, includes a transistor and a capacitor. Other embodiments may include a CMOS device, which may include a transistor, and a DMOS device, which may include a capacitor. An exemplary MTP memory cell includes an n-channel transistor and an n-channel capacitor, through other arrangements are contemplated. In an exemplary embodiment, the transistor includes a floating gate and the capacitor includes a control gate. Further, the MTP memory cell described herein provides for reduced cell size as compared to conventional MTP memory cells, including conventional 1T+1C structures. For example, conventional memory cells may have a cell size of about 14.5 square micrometers (μm2), whereas an exemplary memory cell described herein has a cell size of about 5.25 μm2.
Exemplary embodiments provide for a reduced memory cell size without reducing the breakdown voltage (BV) of the memory cell. For example, while a conventional 14.5 μm2 1T+1C memory cell has a breakdown voltage of about 10.5 volts (V), an exemplary 5.25 μm2 1T+1C memory cell described herein has a breakdown voltage of about 17.5 V.
The process for forming the described MTP memory cell adds no additional masks to an existing process flow for forming integrated circuits. As described herein, an exemplary MTP memory cell is formed with the transistor over a high voltage (HV) doped well. Generally, HV wells are formed with a higher implant energy, hence have larger junction depths as compared to MV or LV wells. Also, the dopant concentration of HV wells is generally lighter than MV or LV wells. For example, an implant energy of a HV well can be about 1 to about 2 MeV, while an implant energy for a MV or LV well is less than 1 MeV. The dopant concentration of an HV well can be about 1E16 to about 1E17 atoms/cm3 and the dopant concentration of a MV/LV well can be about 1E17 to about 1E18 atoms/cm3. Locating the transistor over an HV doped well facilitates operation with the high junction breakdown voltage noted above in comparison with conventional structures.
Embodiments herein generally relate to semiconductor devices. More particularly, some embodiments relate to memory cells, such as non-volatile memory (NVM) devices. Such memory cells, for example, can be incorporated into standalone memory cells, such as USB or other types of portable storage units, or integrated circuits, such as microcontrollers or system on chips (SoCs). The devices or integrated circuits can be incorporated into or used with, for example, consumer electronic products or relate to other types of devices.
As shown in
An exemplary transistor 12 is a metal oxide semiconductor (MOS) transistor. The exemplary transistor 12 includes a gate 14 between first and second diffusion regions 16 and 18, i.e., source and drain regions 16 and 18. An exemplary capacitor 22 is a MOS capacitor. The exemplary capacitor 22 includes a gate 24. A diffusion region 26 is disposed adjacent to the gate 24.
In the exemplary embodiment, the transistor 12 is a storage transistor and the transistor gate 14 may be considered a storage gate. Further, the capacitor 22 may be a control capacitor and the capacitor gate 24 may be considered a control gate.
As illustrated in
In the embodiment illustrated in
The device 30 may include doped regions having different dopant concentrations formed in the substrate 32. For example, the device 30 may include heavily doped (x+), intermediately doped (x), and lightly doped (x−) regions, where x is the p-type or n-type dopant polarity type. A lightly doped (x−) region may have a dopant concentration of from about 1E11 to about 1E13 atoms/cm3, an intermediately doped (x) region may have a dopant concentration of from about 1E13 to about 1E19 atoms/cm3, and a heavily doped (x+) region may have a dopant concentration of about 1E20 atoms/cm3 or higher. Providing other dopant concentrations for the different types of doped regions may also be useful. For example, the dopant concentration ranges may be varied, depending on the technology node. P-type dopants may include boron (B), aluminum (Al), indium (In) or a combination thereof, while n-type dopants may include phosphorous (P), arsenic (As), antimony (Sb) or a combination thereof.
As shown in
As shown in
In
The HV double-diffused region 44 may serve as a control well for control gate 24 of control capacitor 22 while the HV well 42 serves as a well for gate 14 of transistor 12. As shown, the HV well 42 and HV double-diffused region 44 are disposed adjacent to each other. The HV well 42 accommodates the transistor 12 and the HV double-diffused region 44 accommodates the control capacitor 22. The HV double-diffused region 44 includes control well dopants and the HV well 42 includes transistor well dopants. The HV double-diffused region 44 may have a light dopant concentration. For example, the dopant concentration of the HV double-diffused region 44 may be from about 1E16 to about 1E18 atoms/cm3. The HV well 42 may be lightly doped with transistor well dopants. For example, the dopant concentration of storage well dopants in the HV well 42 may be from about 1E16 to about 1E17 atoms/cm3. Other control and/or storage well dopant concentrations may also be useful.
The polarity type of the HV double-diffused region 44 depends on the desired polarity type of the control capacitor 22. In the case of control capacitors, control wells are formed with the same polarity as the capacitor type. Herein, the control capacitor 22 is an n-type capacitor. Therefore, the control well dopant is n-type. The polarity type of transistor wells is the opposite of the desired polarity of the transistor. Herein, the transistor 12 is an n-type transistor. Therefore, the storage transistor well dopants are n-type.
A cell isolation region 46, as shown, separates the HV well 42 and the HV double-diffused region 44, as well as the other device regions. The cell isolation region 46 sufficiently isolates the differently doped regions. For example, the cell isolation region 46 provides sufficient overlap to the different wells/regions. The cell isolation region 46 defines the active region in the HV well 42 and the HV double-diffused region 44. For example the cell isolation region 46 defines the active transistor region of the transistor 12 in the HV well 42 and active capacitor region of the capacitor 22 in the HV double-diffused region 44. The cell isolation region 46 is, for example, a shallow trench isolation region. Other types of isolation regions may also be useful.
In
Exemplary diffusion regions 16 and 18 of transistor 12 are heavily doped regions with first polarity type dopants. The polarity type determines the type of transistor. Herein, the first polarity, i.e., the polarity of first and second diffusion regions 16 and 18, is n-type and the transistor 12 is an n-type transistor.
As shown in
Dielectric spacers (not shown) may be provided on the sidewalls of the gate 14 of transistor 12. The spacers may be used to facilitate forming the LDD regions 36 and 38 and transistor diffusion regions 16 and 18. For example, spacers may be formed after LDD regions 36 and 38 are formed. Spacers may be formed by, for example, forming a spacer layer on the substrate and anisotropically etching it to remove horizontal portions, leaving the spacers on sidewalls of the gates. After forming the spacers, an implant may be performed to form the transistor diffusion regions 16 and 18.
The LDD regions 36 and 38, as described, may be formed by a second implantation process. The second implantation process, for example, may be an implant used to form halo and LDD regions of other devices, such as HV and/or LV devices of the same polarity type. For example, a first LDD implant may be a second implant of other devices elsewhere on the IC, such as MV devices. This enables the same mask used to form regions of other devices to be used to form the LDD regions 36 and 38 of the storage transistor. The use of the same mask enables the device to be formed without the need of extra masks, reducing costs.
As shown in
In
As shown in
Capacitor diffusion region 26 is disposed in the semiconductor substrate 32 adjacent to the control gate 24. The capacitor diffusion region 26, in one embodiment, is heavily doped with control or capacitor type dopants. The capacitor diffusion region 26 serves as a contact region to a well capacitor plate while the gate electrode serves as the other (or gate capacitor) plate. In one embodiment, the capacitor gate electrode 62 is doped before forming the capacitor diffusion region 26. For example, a gate electrode layer deposited on the substrate is pre-doped with control dopants and patterned to form the capacitor gate electrode 62. Because the diffusion regions of the capacitor and transistor are doped with dopants of the same polarity, the diffusion regions 16, 18 and 26 may be formed at the same time.
In one embodiment, the transistor gate 14 and capacitor gate 24 are commonly coupled, as indicated schematically by line 65 in
Metal silicide contacts (not shown) may be provided on contact regions of the memory cell. The metal silicide contacts, for example, may be nickel or nickel-based metal silicide contacts. Other types of metal silicide contacts may also be useful. In one embodiment, metal silicide contacts are provided on the diffusion regions of the transistor and capacitor. A silicide block 68 (shown in
In
As further shown in
The various lines 86, 87, 88, and 89 of the memory cell 10 may be disposed in metal levels (M) of the device 30. The conductive lines disposed in the same direction may be provided in the same metal level. For example, bit line 86 and source line 87 may be disposed on the same level while control gate line 88 and well line 89 are disposed on a different level. Other configurations of conductive lines and metal levels may also be useful.
As an illustration, the device 30 and memory cell 10 as described in
A gate dielectric layer is deposited on the substrate and across the device regions to form gate dielectric layers of the various devices. For example, a silicon oxide layer is formed on the semiconductor substrate 32 to form gate dielectric layers. The gate dielectric layer is formed with different thicknesses for different device regions. A gate dielectric layer of a MV device, for example, may be thicker than a gate dielectric layer of a LV device. For example, an exemplary gate oxide layer of an MV device may be sufficiently thick to prevent electron leakage. In one embodiment, a gate electrode layer, such as a polysilicon layer, is deposited on the gate dielectric layer and the gate electrode layer and gate dielectric layer are patterned to form gate electrodes 52 and 62 and gate dielectric 54 and 64 of the various devices. In one embodiment, the gate electrode layer is a doped polysilicon layer. For example, a gate electrode layer of a control gate is pre-doped with control or capacitor type dopants to form the control gate. Other gate electrodes may also be suitably doped to form gates of other devices. The gate electrode and gate dielectric layers are patterned to form transistor gates of devices, such as HV, MV and/or LV devices.
As described, HV, MV and/or LV devices may be formed on the same semiconductor substrate 32 over the HV well 42 and HV double-diffused region 44. The process may continue to form a memory cell 10, such as a MTP memory cell. The memory cell 10, in one embodiment, is made of MV device. For example, a transistor 12 of the memory cell is an MV transistor and a capacitor 22 of the memory cell is an MV capacitor.
A dielectric spacer layer may be deposited on the semiconductor substrate 32. The dielectric spacer may be patterned to form gate sidewall spacers. In one embodiment, the exposed substrate regions adjacent to the sidewall spacers are heavily doped with transistor type dopants to form diffusion regions 16 and 18. In one embodiment, diffusion regions 16 and 18 are formed adjacent to the sides of the transistor gate 14 (including the spacers) and diffusion region 26 is formed adjacent to a side of the capacitor gate 24 (including a spacer). A common implant mask may be employed, for example, to form the diffusion regions 16, 18 and 26. N-type dopants may be implanted to form diffusion regions 16, 18 and 26. Further, another implant mask may be employed to form diffusion region 74, where p-type dopants may be implanted. Other techniques may also be used to form the diffusion regions.
The process continues to complete forming the device. The processing may include forming an interlayer dielectric (ILD) layer, contacts to the terminals of the memory cell as well as one or more interconnect levels, final passivation, dicing, assembly and packaging. Other processes to complete forming the device may also be included. Other processes to form the device, as described in
The embodiment of
During fabrication processing, the interface well 90 may be formed by selectively masking the HV well 42 and performing an implant to form the interface well 90 before formation of the HV double-diffused region 44. Alternatively, the interface well 90 may be formed by selectively masking the HV well 42 and the HV double-diffused region 44 and performing an implant to form the interface well 90 after formation of the HV double-diffused region 44.
In each embodiment, the memory cell described has improved performance while providing reduced cell size as compared to conventional processing. Further, fabrication of the memory cell requires no additional masks, as the memory cell may be formed using a conventional process flow. In the described memory cell, programming may be performed by channel hot hole induced hot electron injection. Further, erase may be performed by FN tunneling to channel. Such a process does not depend on the drain-source breakdown voltage (BVdss).
As described herein, memory cells are provided with improved performance at reduced cell sizes. In each embodiment, a transistor is formed over an HV well of the first dopant type and is coupled to a capacitor formed over an HV double-diffused region of the opposite second dopant type. Through this structural arrangement, memory cell size may be reduced while avoiding performance issues related to breakdown voltage.
While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration as claimed in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing the exemplary embodiment or exemplary embodiments. It should be understood that various changes can be made in the function and arrangement of elements without departing from the scope herein as set forth in the appended claims and the legal equivalents thereof.
