Patent Application
20240412924
A certain aspect of the present disclosure relates to a multilayer ceramic electronic device, a manufacturing method of the ceramic electronic device, and a circuit board.
There is a technology that covers a multilayer ceramic capacitor mounted on a circuit board with a mold resin to, for example, relieve stress caused by bending the circuit board and improve moisture resistance (see Japanese Patent Application Publication No. 2022-49987 and Japanese Patent Application Publication No. 2014-187142). The mold resin is poured from above the circuit board onto the top surface of the mounted multilayer ceramic capacitor, flows over the surface of the multilayer ceramic capacitor to cover the entire surface, and is then heated and thermally hardened.
According to an aspect of the embodiments, there is provided a multilayer ceramic electronic device including: a multilayer structure having a substantially rectangular parallelepiped shape in which each of a plurality of internal electrode layers and each of a plurality of dielectric layers are alternately stacked; and a pair of external electrodes that respectively cover a pair of facing end surfaces of the multilayer structure, and are alternately connected to the plurality of internal electrode layers along a stacking direction of the multilayer structure, wherein, among four surfaces of the multilayer structure excluding the pair of end surfaces, a surface roughness of at least one of a pair of first surfaces that face each other in the stacking direction is smaller than a surface roughness of at least one of a pair of second surfaces that face each other in an orthogonal direction approximately orthogonal to a facing direction in which the pair of end surfaces face each other and the stacking directions.
According to another aspect of the embodiments, there is provided a manufacturing method of a multilayer ceramic electronic device including: stacking a plurality of green sheets, each having an internal electrode layer formed on a surface thereof; crimping the plurality of green sheets in a stacking direction with a pressing member; after the crimping, cutting the plurality of green sheets along the stacking direction with a blade so as to divide the plurality of green sheets into a plurality of multilayer structures having a substantially rectangular parallelepiped shape; and forming a pair of external electrodes so as to cover a pair of facing end surfaces of the multilayer structure and so as to be alternately connected to the internal electrode layers along the stacking direction, wherein, in the crimping, among four surfaces of the multilayer structure excluding the pair of end surfaces, a surface roughness of a surface of the pressing member contacting at least one of a pair of first surfaces facing each other in the stacking direction is set so that a surface roughness of at least one of the pair of first surfaces is smaller than a surface roughness of at least one of a pair of second surfaces adjacent to the pair of first surfaces.
According to another aspect of the embodiments, there is provided a manufacturing method of a multilayer ceramic electronic device including: stacking a plurality of green sheets, each having an internal electrode layer formed on a surface thereof; crimping the plurality of green sheets in a stacking direction with a pressing member; after the crimping, cutting the plurality of green sheets along the stacking direction with a blade so as to divide the plurality of green sheets into a plurality of multilayer structures having a substantially rectangular parallelepiped shape; and forming a pair of external electrodes so as to cover a pair of facing end surfaces of the multilayer structure and so as to be alternately connected to the internal electrode layers along the stacking direction, wherein, in the cutting, among four surfaces of the multilayer structure excluding the pair of end surfaces, a cutting edge of the blade is formed with irregularities so that a surface roughness of at least one of a pair of first surfaces facing each other in the stacking direction is smaller than a surface roughness of at least one of a pair of second surfaces adjacent to the pair of first surfaces.
According to another aspect of the embodiments, there is provided a multilayer ceramic electronic device that is covered with a mold material and is mounted on the circuit board, wherein the multilayer ceramic capacitor includes: a multilayer structure having a substantially rectangular parallelepiped shape in which each of a plurality of internal electrode layers and each of a plurality of dielectric layers are alternately stacked; and a pair of external electrodes that respectively cover a pair of facing end surfaces of the multilayer structure, and are alternately connected to the plurality of internal electrode layers along a stacking direction of the multilayer structure, wherein, among four surfaces of the multilayer structure excluding the pair of end surfaces, a surface roughness of a first surface of the multilayer structure facing the circuit board is smaller than a surface roughness of at least one of a pair of second surfaces adjacent to the first surface.
However, since there is only a small gap between the mounting surface of the lower part of the multilayer ceramic capacitor and the surface of the circuit board, it is difficult for the mold resin to flow in, and there is a risk of voids being generated in the mold resin in the gap. If these voids are present, for example, moisture may accumulate in the voids, reducing moisture resistance and thus the reliability of the mold may decrease.
The multilayer ceramic capacitor 1 is an example of a multilayer ceramic electronic device. The multilayer ceramic capacitor 1 has a multilayer chip 2 having a substantially rectangular parallelepiped shape, and the external electrodes 3a and 3b provided on a pair of end surfaces 2A and 2B of the multilayer chip 2 which face each other. The external electrodes 3aand 3b are respectively joined to a pair of pads 90 on a board surface 9S of the circuit board 9 by a solder 8 (see dotted line). The pads 90 are electrodes provided on the board surface 9S. The multilayer chip 2 is an example of a multilayer structure.
The multilayer ceramic capacitor 1 is mounted on the circuit board 9 while covered with a mold resin 4 (see dotted line). As a result, for example, the multilayer ceramic capacitor 1 is able to reduce stress caused by bending the circuit board 9 and has improved moisture resistance. The mold resin 4 is an example of a molding material.
The multilayer chip 2 has a multilayer structure in which dielectric layers 22 containing a ceramic material that functions as a dielectric and internal electrode layers 23 are alternately stacked.
The internal electrode layer 23 is mainly composed of a base metal such as nickel (Ni), copper (Cu), or tin (Sn). The internal electrode layer 23 may be composed of a noble metal such as platinum (Pt), palladium (Pd), silver (Ag), or gold (Au) or alloy including one or more of them.
A main component of the dielectric layer 22 is a ceramic material having a perovskite structure expressed by a general formula ABO3. The perovskite structure includes ABO3−α having an off-stoichiometric composition. For example, the ceramic material is such as BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), MgTiO3 (magnesium titanate), Ba1−x−yCaxSryTi1−zZr2O3 (0≤x≤1, 0≤y≤1, 0≤z≤1) having a perovskite structure. Ba1−x−yCaxSryTi1−zZrzO3 may be barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate, barium calcium titanate zirconate or the like.
The external electrodes 3a and 3b cover the opposing end surfaces 2A and 2B of the multilayer chip 2. The external electrodes 3a and 3b extend to the upper surface 2C, the lower surface 2D, and the two side surfaces 2E and 2F. However, the external electrodes 3a and 3b are spaced apart from each other on the upper surface 2C, the lower surface 2D, and the two side surfaces 2E and 2F.
The external electrodes 3a and 3b are mainly composed of metals such as Cu, Ni, Al (aluminum), Zn (zinc), Au (gold), or Sn (tin), and may contain two or more of these metals or alloys (for example, an alloy of Cu and Ni), and may further contain ceramics such as glass components for densifying the external electrodes 3a and 3b and co-materials for controlling the sinterability of the external electrodes 3a and 3b. The glass component is an oxide of Ba (barium), Sr (strontium), Ca (calcium), Zn (zinc), Al, Si (silicon), B (boron), or the like. The common material is, for example, a ceramic component mainly composed of the same material as the main component of the dielectric layer 22. The external electrodes 3a and 3b may be formed with a plated layer mainly composed of base metals such as Ni, Cu, or Sn. Furthermore, a layer of conductive resin such as epoxy resin or urethane resin may be formed on the surface of the external electrodes 3a and 3b. In this case, for example, the external electrodes 3a and 3b may have a layer structure including a base electrode layer mainly composed of Cu that connects to the internal electrodes, a conductive resin layer formed to cover the base electrode layer, and a Ni-platted layer and a Sn-platted layer formed on the conductive resin layer.
As can be seen from
The upper portion and the lower portion of the multilayer chip 2 in the stacking direction are covered by cover layers 20 and 21, respectively. The cover layers 20 and 21 form the upper surface 2C and the lower surface 2D of the multilayer chip 2, respectively. The cover layers 20 and 21 are mainly made of a ceramic material, and are formed from the same main component material as the dielectric layer 22.
The size of the multilayer ceramic capacitor 1 differs between the shorter type and taller type. In the shorter type multilayer ceramic capacitor 1, the height T is the shortest among the height T, length L, and width W of the multilayer chip 2. In other words, the size relationship of the shorter type multilayer ceramic capacitor 1 is L>W>T or W>L>T.
The length L, the width W, and the height T of the shorter multilayer ceramic capacitor 1 are, for example, 0.6 mm, 0.3 mm, and 0.20 mm, or 1.0 mm, 0.5 mm, and 0.3 mm, or 3.2 mm, 1.6 mm, and 1.2 mm, or 3.2 mm, 2.5 mm, and 1.6 mm, or 4.5 mm, 3.2 mm, and 2.5 mm, but are not limited to these sizes. The numerical values given as sizes include typical manufacturing tolerances and are not limited to the above numerical values.
On the other hand, the taller multilayer ceramic capacitor 1 has a height T of the multilayer chip 2 that is longer than its width (W). The size of the taller type multilayer ceramic capacitor 1 satisfies the relationship L>T>W or the relationship T>L≥W. The taller type multilayer ceramic capacitor 1 generally has a greater number of the internal electrode layers 23 than the shorter type multilayer ceramic capacitor 1, and can achieve a larger electrostatic capacity.
The length L, the width W, and the height T of the taller type multilayer ceramic capacitor 1 are, for example, 0.6 mm, 0.3 mm, and 0.40 mm, or 1.0 mm, 0.5 mm, and 0.7 mm, or 3.2 mm, 1.6 mm, and 1.8 mm, or 3.2 mm, 2.5 mm, and 3.6 mm, or 4.5 mm, 3.2 mm, and 4.5 mm, but are not limited to these sizes. The numerical values given as sizes include typical manufacturing tolerances and are not limited to the above numerical values.
After the multilayer ceramic capacitor 1 is mounted on the circuit board 9 by a reflow process, the entire outer surface of the multilayer ceramic capacitor 1 is covered with the mold resin 4 poured from a dispenser above. The viscosity of the mold resin 4 is, for example, 6700 (Pa·s). The circuit board 9 is then heated for 8 to 10 minutes in a batch furnace at 130 to 150 (° C.) to harden the mold resin 4.
However, since there is only a small gap S (for example, 20 μm) between the lower surface 2D, which is the mounting surface of the multilayer ceramic capacitor 1, and the board surface 9S of the circuit board 9, it is difficult for the mold resin 4 to flow in, and there is a risk of a void forming in the mold resin 4 in the gap S. If this void exists, for example, moisture may accumulate in the void, reducing the moisture resistance, and thus reducing the reliability of the mold.
Therefore, the surface roughness Ra of the side surfaces 2E and 2F and the lower surface 2D of the multilayer chip 2 is set so that the mold resin 4 can easily flow into the gap S. Specifically, the multilayer ceramic capacitor 1 is formed so that the surface roughness Ra of the upper surface 2C and the lower surface 2D is smaller than the surface roughness Ra of the side surfaces 2E and 2F so that the wettability of the mold resin 4 on the lower surface 2D is greater than that on the side surfaces 2E and 2F. Here, the surface roughness Ra is specified in “JIS (Japan Industrial Standards) B 0601 (1994)”. The upper surface 2C and the lower surface 2D are an example of a pair of the first surfaces that face each other, and the side surfaces 2E and 2F are an example of a pair of second surfaces that are adjacent to the upper surface 2C and the lower surface 2D. The flow of the mold resin 4 will be described in detail below.
(Molding process)
A dispenser 7 that dispenses the mold resin 4 is disposed above the multilayer ceramic capacitor 1 so that the outlet of the mold resin 4 faces the upper surface 2C. The mold resin 4 dispensed from the dispenser 7 spreads over the upper surface 2C as indicated by the reference symbol M1. At this time, the smaller the surface roughness Ra of the upper surface 2C is, the higher the wettability and the easier it is for the mold resin 4 to flow over the upper surface 2C. Therefore, the multilayer chip 2 may be formed so that the surface roughness Ra of the upper surface 2C is smaller than the surface roughness Ra of both of the side surfaces 2E and 2F. This allows the mold resin 4 to flow smoothly from the upper surface 2C to both of the side surfaces 2E and 2F.
After the mold resin 4 spreads on the upper surface 2C, the mold resin 4 flows vertically downward due to gravity on both of the side surfaces 2E and 2F adjacent to the upper surface 2C, as illustrated by reference numeral M2. At this time, the larger the surface roughness Ra of both of the side surfaces 2E and 2F is, the higher the surface resistance to the mold resin 4 is. This reduces the wettability of the side surfaces 2E and 2F, making it difficult for the mold resin 4 to flow on the side surfaces 2E and 2F. Therefore, the mold resin 4 that flows from the dispenser 7 along the upper surface 2C flows slowly and is likely to accumulate on the side surfaces 2E and 2F. Here, the thickness of the mold resin 4 on the side surfaces 2E and 2F in the Y direction is d1 (μm).
In this example, the surface roughness Ra of both of the side surfaces 2E and 2F is smaller than that of the example in
In this manner, the thicknesses d1 and d2 of the mold resin 4 flowing along the side surfaces 2E and 2F depend on the surface roughness Ra. When the thickness d1 of the mold resin 4 is thick as illustrated in
After the mold resin 4 flows along both of the side surfaces 2E and 2F as illustrated in
In this example, the case where the mold resin 4 illustrated in
As described above, the pressure at which the mold resin 4 flows is small, and the surface roughness Ra of the lower surface 2D is large, so that the mold resin 4 does not easily wet and spread into the gap S. For this reason, voids P are easily generated in the mold resin 4 in the gap S, which may reduce the reliability of the mold.
By forming the multilayer chip 2 so that the surface roughness Ra of the lower surface 2D is smaller than the surface roughness Ra of the side surfaces 2E and 2F, the mold resin 4 can easily flow into the gap S, and the occurrence of the voids P in the mold resin 4 in the gap S is suppressed. This improves the reliability of the mold in the multilayer ceramic capacitor 1.
In this example, the surface roughness Ra of the lower surface 2D is smaller than the surface roughness Ra of both of the side surfaces 2E and 2F, but the surface roughness Ra of the lower surface 2D may be smaller than the surface roughness Ra of at least one of the side surfaces 2E and 2F. In this case, the flow into the gap S from at least one of the side surfaces 2E and 2F is facilitated, and the occurrence of the voids P in the mold resin 4 can be suppressed.
For example, when the circuit board 9 is bent, the shorter type multilayer ceramic capacitor 1 is more likely to generate large stress in the bending direction than the taller type multilayer ceramic capacitor 1, but the stress is alleviated by sufficiently filling the gap S with the mold resin 4 as described above, and therefore, for example, the occurrence of cracks can be suppressed. Furthermore, the taller type multilayer ceramic capacitor 1 has a larger number of layers than the shorter type multilayer ceramic capacitor 1, and generates more heat. However, by sufficiently filling the gaps S with the mold resin 4 as described above, heat dissipation is improved, and temperature rise can be suppressed.
The greater the difference in surface roughness Ra between the lower surface 2D and the side surfaces 2E and 2F is, the more stable the suppression of voids is. For this reason, it is preferable that the difference in surface roughness Ra is, for example, 0.025 (μm) or more.
The smaller the difference in surface roughness Ra between the lower surface 2D and the side surfaces 2E and 2F is, the smaller the difference in appearance between the lower surface 2D and the side surfaces 2E and 2F is, and this makes it easier to identify defects such as chipping of the ridges of the multilayer ceramic capacitor 1 during optical appearance inspection. For this reason, it is preferable that the difference in surface roughness Ra is, for example, 0.151 (μm) or less.
The larger the surface roughness Ra of the lower surface 2D is, the larger the surface area of the lower surface 2D is, and therefore the stronger the adhesion of the mold resin to the lower surface 2D is. For this reason, it is preferable that the surface roughness of the lower surface 2D is, for example, 0.041 (μm) or more.
The smaller the surface roughness Ra of the lower surface 2D is, the more stably it is to suppress voids. For this reason, it is preferable that the surface roughness of the lower surface 2D is, for example, 0.065 (μm) or less.
The larger the surface roughness Ra of the side surfaces 2E and 2F is, the more the thickness d1 of the mold resin 4 can be increased. For this reason, it is preferable that the surface roughness of the side surfaces 2E and 2F is, for example, 0.090 (μm) or more.
The smaller the surface roughness Ra of the side surfaces 2E and 2F is, the more crack defects can be suppressed. For this reason, it is preferable that the surface roughness Ra of the side surfaces 2E and 2F is, for example, 0.192 (μm) or less. The numerical ranges of the surface roughness Ra of each surface described above are merely examples, and are not intended to be limiting.
(Manufacturing method of multilayer ceramic capacitor)
(Green sheet forming process) First, the green sheet forming process St1 is carried out. In this process, a dielectric material obtained by adding various additive compounds (such as sintering aids) to ceramic powder is wet mixed with a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer. The resulting slurry is used to coat a dielectric green sheet on a base material, for example, by a die coater method or a doctor blade method, and then dried. The base material is, for example, a PET (polyethylene terephthalate) film.
Additive compounds for the ceramic powder include oxides of Mg (magnesium), Mn (manganese), V (vanadium), Cr (chromium), rare earth elements (Y (yttrium), Sm (samarium), Eu (europium), Gd (gadolinium), Tb (terbium), Dy (dysprosium), Ho (holmium), Er (erbium), Tm (thulium) or Yb (ytterbium)), as well as oxides or glass of Co (cobalt), Ni, Li (lithium), B (boron), Na (sodium), K (potassium) or Si (silicon).
(Internal electrode printing process) Next, the internal electrode printing process St2 is carried out. In this process, a metal conductive paste for forming an internal electrode containing an organic binder is printed by gravure printing on the dielectric green sheet on the base material, so that a plurality of internal electrode patterns corresponding to the internal electrode layers 23 are formed at a distance from each other. Ceramic particles are added to the metal conductive paste as a co-material. The main component of the ceramic particles is not particularly limited, but is preferably the same as the main component ceramic of the dielectric layer 22.
(Stacking process) Next, the stacking process St3 is carried out. In this process, a multilayer sheet is formed by stacking the dielectric green sheets on which the internal electrode pattern that will become the internal electrode layer 23 is printed. Dielectric green sheets corresponding to the cover layers 20 and 21 are stacked on both end surfaces in the stacking direction of the multilayer sheet.
(Crimping process) Next, the crimping process St4 is carried out. This process is an example of a process in which the plurality of green sheets each having the internal electrode pattern formed on its surface are stacked and pressed in the stacking direction with a pressing member to be compressed. In this process, the multilayer sheet is pressurized to compress the plurality of dielectric green sheets. The crimping means may be, for example, a hydrostatic press, but is not limited thereto.
(Cutting process) Next, cutting process St5 is carried out. This process is an example of a process in which the multilayer sheet after crimping is cut along the stacking direction with a blade so as to divide it into a plurality of the multilayer chips 2. In this process, a plurality of the multilayer chips 2 are obtained by cutting the multilayer sheet along a predetermined cut line in the stacking direction.
(Polishing process) Next, polishing process St6 is carried out. In this process, the multilayer chip 2 is polished by a method such as barrel polishing. As a result, the corners of the multilayer chip 2 are rounded.
(External electrode forming process) Next, external electrode formation process St7 is carried out. This process is an example of a process in which a pair of external electrodes 3a and 3b are formed that cover the pair of end surfaces 2A and 2B of the multilayer chip 2 and are alternately connected to the internal electrode layer 23 along the stacking direction. In this process, a conductive paste containing, for example, metal powder, glass frit, binder, and solvent is applied to each of the end surfaces 2A and 2B, the upper surface 2C, the lower surface 2D, and each of the side surfaces 2E and 2F of the multilayer chip 2. After the conductive paste is applied, it is dried to form the external electrodes 3a and 3b. The binder and the solvent are evaporated by baking. Examples of the method for applying the conductive paste include a sputtering method and a dipping method.
(Firing process) Next, the firing process St8 is carried out. In this process, the multilayer chip 2 on which the external electrodes 3a and 3b are formed is subjected to a binder removal process in an N2 atmosphere at 250 to 500° C., and then fired in a reducing atmosphere at 1300 to 1400° C. for about 1 hour, thereby sintering each particle in the multilayer chip 2. In this way, the manufacturing process of the multilayer ceramic capacitor 1 is carried out. After the firing process, metal coatings such as Cu, Ni, Sn and the like may be applied to the external electrodes 3a and 3b by plating. Furthermore, the external electrode formation process St7 may be performed after the firing process St8.
For example, in the crimping process St4, the surface roughness Ra of the pressing member pressing the multilayer sheet is set so that the surface roughness Ra of the lower surface 2D of the multilayer chip 2 is smaller than the surface roughness Ra of the side surfaces 2E and 2F.
The multilayer sheet 5S is crimped by being sandwiched between a pair of pressing members 6a and 6b from above and below in the stacking direction. The pressing members 6a and 6b are, for example, metal plate-shaped members, and as indicated by the symbol DP, press the multilayer sheet 5S from above and below in the stacking direction, for example, by hydrostatic pressure.
The symbol Ga indicates an enlarged view of a surface 60 of the lower pressing member 6b and a lower surface 50 of the dielectric green sheet 5b, which come into contact with each other in the crimping step St4. The surface 60 of the pressing member 6b has irregularities according to the design value of the surface roughness Ra of the lower surface 2D of the multilayer chip 2. The irregularities of the pressing member 6b are transferred to the lower surface 50 of the dielectric green sheet 5b by the pressing member 6b pressing the dielectric green sheet 5b in the crimping step St4. As a result, the surface roughness Ra of the lower surface 2D of the multilayer chip 2, which corresponds to the lower surface 50, becomes a desired value smaller than the surface roughness Ra of the side surfaces 2E and 2F.
In this way, the surface roughness Ra of the surface of the pressing member 6b that comes into contact with the lower surface 2D is set so that the surface roughness Ra of the lower surface 2D is smaller than the surface roughness Ra of the side surfaces 2E and 2F, so that the surface roughness Ra of the lower surface 2D can be easily adjusted to a desired value. After confirming that the surface roughness Ra of the dielectric green sheet 5b has been adjusted to the desired value, the next cutting step St5 is carried out.
In this example, adjustment of the surface roughness Ra of the lower surface 2D of the multilayer chip 2 has been described, but the surface roughness Ra of the upper surface 2C can also be adjusted by the same means as above. In this case, the surface roughness Ra of the pressing member 6a that contacts the upper dielectric green sheet 5a is set according to the desired value of the upper surface 2C. As a result, in the crimping step St4, the irregularities of the pressing member 6a is transferred to the upper surface of the dielectric green sheet 5a, and the surface roughness Ra of the upper surface 2C becomes smaller than the surface roughness Ra of the side surfaces 2E and 2F.
In addition, the adjustment of the surface roughness Ra of the lower surface 2D is not limited to the above means. For example, in the cutting step St5, irregularities may be formed on the cutting edge of the blade so that the surface roughness Ra of the lower surface 2D of the multilayer chip 2 is smaller than the surface roughness Ra of the side surfaces 2E and 2F.
The symbol Gb indicates an enlarged part of the cutting edge BLa of the blade BL. The cutting edge BLa has saw-like irregularities formed thereon, as an example. The uneven shape of the cutting edge BLa is determined according to the desired value of the surface roughness Ra of the side surfaces 2E and 2F of the multilayer chip 2. For example, the height and pitch of the irregularities of the cutting edge BLa are determined so as to roughen the cut surfaces of the multilayer sheet 5S corresponding to the side surfaces 2E and 2F. As a result, the surface roughness Ra of the lower surface 2D of the multilayer chip 2 becomes smaller than the surface roughness Ra of the side surfaces 2E and 2F.
In this way, the cutting edge BLa of the blade BL is uneven so that the surface roughness Ra of the lower surface 2D is smaller than the surface roughness Ra of the side surfaces 2E and 2F, so that the surface roughness Ra of the side surfaces 2E and 2F can be easily adjusted to a desired value. After confirming that the surface roughness Ra of the cut surface of the multilayer sheet 5S has been adjusted to a desired value, the next polishing step St6 is carried out.
In this example, an example of adjusting the surface roughness Ra of the side surfaces 2E and 2F is given, but it is also possible to adjust only the surface roughness Ra of one of the side surfaces 2E and 2F. Also, in this example, an example of adjusting the surface roughness Ra of the side surfaces 2E and 2F to be larger than the surface roughness Ra of the lower surface 2D is given, but it is also possible to adjust the surface roughness Ra of the side surfaces 2E and 2F to be larger than both the surface roughness Ra of the lower surface 2D and the surface roughness Ra of the upper surface 2C.
The surface roughness of the upper surface 2C, the lower surface 2D, and the side surfaces 2E and 2F of the multilayer chip 2, and the difference in surface roughness Ra between the upper surface 2C and the side surfaces 2E and 2F, are as described above.
Next, the evaluation results of the multilayer ceramic capacitor 1 of the example will be described.
Table 1 shows the evaluation results of the multilayer ceramic capacitors of Examples 1 to 6 and examples 1 and 2 for comparison (hereinafter referred to as Comparative Examples 1 and 2). The multilayer ceramic capacitors of Examples 1 to 6 and Comparative Examples 1 and 2 were fabricated according to the above manufacturing process and were evaluated. Each multilayer ceramic capacitor was a taller type. The size of each multilayer ceramic capacitor was 0.6 (mm) in length, 0.3 (mm) in width, and 0.4 (mm) in height, and the rated voltage of each multilayer ceramic capacitor was 6.3 (V).
The surface roughness Ra of each multilayer ceramic capacitor was adjusted in the above crimping process St4. In the multilayer ceramic capacitor of Example 1, the surface roughness Ra of the lower surface 2D and the side surfaces 2E and 2F was set to 0.065 (μm) and 0.09 (μm), respectively. In the multilayer ceramic capacitor of Example 2, the surface roughness Ra of the lower surface 2D and the side surfaces 2E and 2F was set to 0.073 (μm) and 0.129 (μm), respectively. In the multilayer ceramic capacitor of Example 3, the surface roughness Ra of the lower surface 2D and the side surfaces 2E and 2F was set to 0.041 (μm) and 0.192 (μm), respectively. In the multilayer ceramic capacitor of Example 4, the surface roughness Ra of the lower surface 2D and the side surfaces 2E and 2F was set to 0.054 (μm) and 0.116 (μm), respectively. In the multilayer ceramic capacitor of Example 5, the surface roughness Ra of the lower surface 2D and the side surfaces 2E and 2F was set to 0.062 (μm) and 0.091 (μm), respectively. In the multilayer ceramic capacitor of Example 6, the surface roughness Ra of the lower surface 2D and the side surfaces 2E and 2F was set to 0.048 (μm) and 0.127 (μm), respectively.
As a result, the differences ΔRa between the surface roughness Ra of the lower surface 2D and the surface roughness Ra of the side surfaces 2E and 2F in Examples 1 to 6 were 0.025 (μm), 0.056 (μm), 0.151 (μm), 0.062 (μm), 0.029 (μm), and 0.079 (μm), respectively. In this way, for the multilayer ceramic capacitors of Examples 1 to 3, the surface roughness Ra of the lower surface 2D was set to be smaller than the surface roughness Ra of the side surfaces 2E and 2F.
On the other hand, in the multilayer ceramic capacitor of Comparative Example 1, the surface roughness Ra of the lower surface 2D and the side surfaces 2E and 2F was set to 0.089 (μm) and 0.068 (μm), respectively. In the multilayer ceramic capacitor of Comparative Example 2, the surface roughness Ra of the lower surface 2D and the side surfaces 2E and 2F was set to 0.075 (μm) and 0.061 (μm), respectively. As a result, the difference ΔRa between the surface roughness Ra of the lower surface 2D and the surface roughness Ra of the side surfaces 2E and 2F in Comparative Examples 1 and 2 was −0.021 (μm) and −0.014, respectively. In this way, in the multilayer ceramic capacitor of the comparative example, the surface roughness Ra of the lower surface 2D was set to be greater than the surface roughness Ra of the side surfaces 2E and 2F, in contrast to Examples 1 to 6.
The multilayer ceramic capacitors of Examples 1 to 6 and Comparative Examples 1 and 2 were mounted on the circuit board 9 by a reflow process so that the lower surface 2D faced the board surface 9S. After mounting, mold resin was poured into the multilayer ceramic capacitor from a dispenser above the circuit board 9 to cover its entire outer surface. The viscosity of the mold resin at this time was set to 6700 (Pa·s). The circuit board 9 was then heated for 8 to 10 minutes in a batch furnace at 130 to 150 (° C.) to harden the mold resin. After the mold resin hardened, the presence or absence of voids in the mold resin filled in the gap between the lower surface 2D and the board surface 9S was confirmed by viewing the A-A cross section in
The “Presence or Absence of Voids” in Table 1 indicates the confirmation results. There were no voids in the multilayer ceramic capacitors of Examples 1 to 6. For this reason, the judgment results for Examples 1 to 3 were set to “OK”. This is because in Examples 1 to 6, the surface roughness Ra of the lower surface 2D is smaller than the surface roughness Ra of each of the side surfaces 2E and 2F, so that the mold resin easily flows from the side surfaces 2E and 2F along the lower surface 2D into the gaps, as described above.
In contrast, voids were confirmed in the multilayer ceramic capacitors of Comparative Examples 1 and 2. For this reason, the comparative examples were judged to be “NG”. This is because in Examples 1 to 6, the surface roughness Ra of the lower surface 2D is larger than the surface roughness Ra of each of the side surfaces 2E and 2F, so that the mold resin does not easily flow from the side surfaces 2E and 2F along the lower surface 2D into the gaps, as described above.
In this way, the case where the difference in surface roughness Ra between the lower surface 2D and the side surfaces 2E and 2F is 0.025 (μm) or more, or 0.151 (μm) or less is preferable, because the mold resin 4 flows into the voids favorably. Furthermore, it is preferable that the surface roughness Ra of the lower surface 2D is 0.041 to 0.065 (μm) and the surface roughness Ra of the side surfaces 2E and 2F is 0.090 to 0.192 (μm) because this allows the mold resin to flow into the voids favorably.
Although the embodiments of the present invention have been described in detail, it is to be understood that the various change, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-140865 | Sep 2022 | JP | national |
This application is a continuation application of International Application No. PCT/JP2023/024974 filed on Jul. 5, 2023, which claims the benefit of Japanese Application No. 2022-140865, filed on Sep. 5, 2022, in the Japanese Patent Office, the entire contents of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2023/024974 | Jul 2023 | WO |
| Child | 18806106 | US |
