Patent Grant
10615289
The invention is in the field of semiconductor devices.
For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant.
Non-volatile semiconductor memories typically use stacked floating gate type field-effect-transistors. In such transistors, electrons are injected into a floating gate of a memory cell to be programmed by biasing a control gate and grounding a body region of a substrate on which the memory cell is formed. An oxide-nitride-oxide (ONO) stack is used as either a charge storing layer, as in a semiconductor-oxide-nitride-oxide-semiconductor (SON OS) transistor, or as an isolation layer between the floating gate and control gate, as in a split gate flash transistor.
Referring to
One problem with conventional SONOS transistors is the limited program and erase window achievable with a conventional blocking layer 106C, inhibiting optimization of semiconductor device 100. For example,
Embodiments of the present invention are illustrated by way of example, and not limitation, in the figures of the accompanying drawings in which:
A nonvolatile charge trap memory device and a method to form the same is described herein. In the following description, numerous specific details are set forth, such as specific dimensions, in order to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known processing steps, such as patterning steps or wet chemical cleans, are not described in detail in order to not unnecessarily obscure the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale.
Disclosed herein is a nonvolatile charge trap memory device. The device may include a substrate having a channel region and a pair of source and drain regions. A gate stack may be formed above the substrate over the channel region and between the pair of source and drain regions. In an embodiment, the gate stack includes a high dielectric constant blocking region. In one embodiment, the high dielectric constant blocking region is a bi-layer blocking dielectric region having a first dielectric layer disposed directly above a charge-trapping layer and a second dielectric layer disposed directly above the first dielectric layer and directly below a gate layer. The dielectric constant of the first dielectric layer is lower than the dielectric constant of the second dielectric layer. In another embodiment, the high dielectric constant blocking region is a graded blocking dielectric layer disposed directly above a charge-trapping layer and directly below a gate layer. The dielectric constant of the graded blocking dielectric layer has a low-to-high gradient in the direction from the charge-trapping layer to the gate layer.
A nonvolatile charge trap memory device including a high dielectric constant blocking region may exhibit a relatively large program and erase window, enabling improved performance of such a device. For example, in accordance with an embodiment of the present invention,
The ability to achieve a deep erase in a nonvolatile charge trap memory device including a high dielectric constant blocking region may result from the ability of the high dielectric constant blocking region to mitigate back-streaming of electrons. Such back-streaming otherwise proceeds into a charge-trapping layer that is subject to an erase-mode voltage application. For example, in accordance with an embodiment of the present invention,
A nonvolatile charge trap memory device may include a multi-layer blocking dielectric region.
Referring to
Semiconductor device 500 may be any nonvolatile charge trap memory device. In one embodiment, semiconductor device 500 is a Flash-type device wherein the charge-trapping layer is a conductor layer or a semiconductor layer. In accordance with another embodiment of the present invention, semiconductor device 500 is a SONOS-type device wherein the charge-trapping layer is an insulator layer. By convention, SONOS stands for “Semiconductor-Oxide-Nitride-Oxide-Semiconductor,” where the first “Semiconductor” refers to the channel region material, the first “Oxide” refers to the tunnel dielectric layer, “Nitride” refers to the charge-trapping dielectric layer, the second “Oxide” refers to the blocking dielectric layer and the second “Semiconductor” refers to the gate layer. A SONOS-type device, however, is not limited to these specific materials, as described below.
Substrate 502 and, hence, channel region 512, may be composed of any material suitable for semiconductor device fabrication. In one embodiment, substrate 502 is a bulk substrate composed of a single crystal of a material which may include, but is not limited to, silicon, germanium, silicon-germanium or a III-V compound semiconductor material. In another embodiment, substrate 502 includes a bulk layer with a top epitaxial layer. In a specific embodiment, the bulk layer is composed of a single crystal of a material which may include, but is not limited to, silicon, germanium, silicon-germanium, a III-V compound semiconductor material and quartz, while the top epitaxial layer is composed of a single crystal layer which may include, but is not limited to, silicon, germanium, silicon-germanium and a III-V compound semiconductor material. In another embodiment, substrate 502 includes a top epitaxial layer on a middle insulator layer which is above a lower bulk layer. The top epitaxial layer is composed of a single crystal layer which may include, but is not limited to, silicon (i.e. to form a silicon-on-insulator (SOI) semiconductor substrate), germanium, silicon-germanium and an III-V compound semiconductor material. The insulator layer is composed of a material which may include, but is not limited to, silicon dioxide, silicon nitride and silicon oxy-nitride. The lower bulk layer is composed of a single crystal which may include, but is not limited to, silicon, germanium, silicon-germanium, an III-V compound semiconductor material and quartz. Substrate 502 and, hence, channel region 512, may include dopant impurity atoms. In a specific embodiment, channel region 512 is doped P-type and, in an alternative embodiment, channel region 512 is doped N-type.
Source and drain regions 510 in substrate 502 may be any regions having opposite conductivity to channel region 512. For example, in accordance with an embodiment of the present invention, source and drain regions 510 are N-type doped regions while channel region 512 is a P-type doped region. In one embodiment, substrate 502 and, hence, channel region 512, is composed of boron-doped single-crystal silicon having a boron concentration in the range of 1×1015-1×1019 atoms/cm3. Source and drain regions 510 are composed of phosphorous- or arsenic-doped regions having a concentration of N-type dopants in the range of 5×1016-5×1019 atoms/cm3. In a specific embodiment, source and drain regions 510 have a depth in substrate 502 in the range of 80-200 nanometers. In accordance with an alternative embodiment of the present invention, source and drain regions 510 are P-type doped regions while channel region 512 is an N-type doped region.
Tunnel dielectric layer 504A may be any material and have any thickness suitable to allow charge carriers to tunnel into the charge-trapping layer under an applied gate bias while maintaining a suitable barrier to leakage when the device is unbiased. In one embodiment, tunnel dielectric layer 504A is formed by a thermal oxidation process and is composed of silicon dioxide or silicon oxy-nitride, or a combination thereof. In another embodiment, tunnel dielectric layer 504A is formed by chemical vapor deposition or atomic layer deposition and is composed of a dielectric layer which may include, but is not limited to, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, hafnium silicate, zirconium silicate, hafnium oxy-nitride, hafnium zirconium oxide and lanthanum oxide. In another embodiment, tunnel dielectric layer 504A is a bi-layer dielectric region including a bottom layer of a material such as, but not limited to, silicon dioxide or silicon oxy-nitride and a top layer of a material which may include, but is not limited to, silicon nitride, aluminum oxide, hafnium oxide, zirconium oxide, hafnium silicate, zirconium silicate, hafnium oxy-nitride, hafnium zirconium oxide and lanthanum oxide. Thus, in one embodiment, tunnel dielectric layer 504A includes a high-K dielectric portion. In a specific embodiment, tunnel dielectric layer 504A has a thickness in the range of 1-10 nanometers.
Charge-trapping layer may be any material and have any thickness suitable to store charge and, hence, raise the threshold voltage of gate stack 504. In accordance with an embodiment of the present invention, charge-trapping layer 504B is formed by a chemical vapor deposition process and is composed of a dielectric material which may include, but is not limited to, stoichiometric silicon nitride, silicon-rich silicon nitride and silicon oxy-nitride. In one embodiment, charge-trapping layer 504B is composed of a bi-layer silicon oxy-nitride region. For example, in a specific embodiment, charge-trapping layer 504B includes an oxygen-rich portion and a silicon rich portion and is formed by depositing an oxygen-rich oxy-nitride film by a first composition of gases and, subsequently, depositing a silicon-rich oxy-nitride film by a second composition of gases. In a particular embodiment, charge-trapping layer 504B is formed by modifying the flow rate of ammonia (NH3) gas, and introducing nitrous oxide (N20) and dichlorosilane (SiH2Cb) to provide the desired gas ratios to yield first an oxygen-rich oxy-nitride film and then a silicon-rich oxy-nitride film. In one embodiment, charge-trapping layer 504B has a thickness in the range of 5-10 nanometers. In accordance with an alternative embodiment of the present invention, charge-trapping layer 504B has a graded composition.
Multi-layer blocking dielectric region 504C may be composed of any material and have any thickness suitable to maintain a barrier to charge leakage without significantly decreasing the capacitance of gate stack 504. In accordance with an embodiment of the present invention, multi-layer blocking dielectric region 504C is a bilayer blocking dielectric region having a first dielectric layer 506 disposed directly above charge-trapping layer 504B and having a second dielectric layer 508 disposed directly above first dielectric layer 506 and directly below gate layer 504D. In an embodiment, first dielectric layer 506 has a large barrier height while second dielectric layer 508 has a high dielectric constant. In one embodiment, the barrier height of first dielectric layer 506 is at least approximately 2 electron Volts (eV). In a specific embodiment, the barrier height of first dielectric layer 506 is at least approximately 3 eV. In an embodiment, the dielectric constant of first dielectric layer 506 is lower than the dielectric constant of second dielectric layer 508. In one embodiment, first dielectric layer 506 of bi-layer blocking dielectric region 504C is composed of silicon dioxide and second dielectric layer 508 is composed of silicon nitride. In another embodiment, first dielectric layer 506 of bi-layer blocking dielectric region 504C is composed of silicon dioxide and second dielectric layer 508 is composed of a material such as, but not limited to, aluminum oxide, hafnium oxide, zirconium oxide, hafnium silicate, zirconium silicate, hafnium oxy-nitride, hafnium zirconium oxide or lanthanum oxide. In a specific embodiment, first dielectric layer 506 of bi-layer blocking dielectric region 504C is composed of a material having a dielectric constant approximately in the range of 3.5-4.5 and second dielectric layer 508 is composed of a material having a dielectric constant above approximately 7. In accordance with an embodiment of the present invention, multi-layer blocking dielectric region 504C is formed in part by a chemical vapor deposition process. In one embodiment, multi-layer blocking dielectric region 504C is formed from at least two different materials. In a specific embodiment, forming multi-layer blocking dielectric region 504C from at least two different materials includes oxidizing a top portion of charge-trapping layer 504B and, subsequently, depositing a dielectric layer above the oxidized portion of charge-trapping layer 504B. In another specific embodiment, forming graded blocking dielectric layer 504C from at least two different materials includes depositing a first dielectric layer having a first dielectric constant and, subsequently, depositing a second dielectric layer having a second dielectric constant, wherein the second dielectric constant is greater than the first dielectric constant. In a particular embodiment, the first dielectric layer has a thickness approximately in the range of 0.5-3 nanometers, the second dielectric layer has a thickness approximately in the range of 2-5 nanometers, and the first and second dielectric layers are not inter-mixed. Thus, in accordance with an embodiment of the present invention, multi-layer blocking dielectric region 504C has an abrupt interface between first dielectric layer 506 and second dielectric layer 508, as depicted in
Gate layer 504D may be composed of any conductor or semiconductor material suitable for accommodating a bias during operation of a SON OS-type transistor. In accordance with an embodiment of the present invention, gate layer 504D is formed by a chemical vapor deposition process and is composed of doped poly-crystalline silicon. In another embodiment, gate layer 504D is formed by physical vapor deposition and is composed of a metal-containing material which may include, but is not limited to, metal nitrides, metal carbides, metal silicides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt and nickel. In one embodiment, gate layer 504D is a high work-function gate layer.
In another aspect of the present invention, a nonvolatile charge trap memory device may include a graded blocking dielectric layer.
Referring to
Semiconductor device 600 may be any semiconductor device described in association with semiconductor device 500 from
However, in contrast to semiconductor device 500, semiconductor device 600 includes a graded blocking dielectric layer 604C, as depicted in
A nonvolatile charge trap memory device may be fabricated to include a multi-layer blocking dielectric region.
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
In another embodiment, a nonvolatile charge trap memory device is fabricated to include a graded blocking dielectric layer.
Referring to
Referring to
Referring to
Implementations and Alternatives
In another aspect the present disclosure is directed to multigate or multigate-surface memory devices including charge-trapping regions overlying two or more sides of a channel formed on or above a surface of a substrate, and methods of fabricating the same. Multigate devices include both planar and non-planar devices. A planar multigate device (not shown) generally includes a double-gate planar device in which a number of first layers are deposited to form a first gate below a subsequently formed channel, and a number of second layers are deposited thereover to form a second gate. A non-planar multigate device generally includes a horizontal or vertical channel formed on or above a surface of a substrate and surrounded on three or more sides by a gate.
Referring again to
In some embodiments, such as that shown in
Either or both of the first charge-trapping layer 924 and the second charge-trapping layer 926 can comprise silicon nitride or silicon oxynitride, and can be formed, for example, by a CVD process including N2O/NH3 and DCS/NH3 gas mixtures in ratios and at flow rates tailored to provide a silicon-rich and oxygen-rich oxynitride layer. The second nitride layer of the multi-layer charge storing structure is then formed on the middle oxide layer. The second charge-trapping layer 926 has a stoichiometric composition of oxygen, nitrogen and/or silicon different from that of the first charge-trapping layer 924, and may also be formed or deposited by a CVD process using a process gas including DCS/NH3 and N2O/NH3 gas mixtures in ratios and at flow rates tailored to provide a silicon-rich, oxygen-lean top nitride layer.
In those embodiments including an intermediate or anti-tunneling layer 928 comprising oxide, the anti-tunneling layer can be formed by oxidation of the bottom oxynitride layer, to a chosen depth using radical oxidation. Radical oxidation may be performed, for example, at a temperature of 1100-1100° C. using a single wafer tool, or 800-900° C. using a batch reactor tool. A mixture of H2 and O2 gasses may be employed at a pressure of 300-500 Tor for a batch process, or 11-15 Tor using a single vapor tool, for a time of 1-2 minutes using a single wafer tool, or 30 min-1 hour using a batch process.
A suitable thickness for the first charge-trapping layer 924 may be from about 30 Å to about 80 Å (with some variance permitted, for example ±10 A), of which about 5-20 Å may be consumed by radical oxidation to form the anti-tunneling layer 928. A suitable thickness for the second charge-trapping layer 926 may be at least 30 Å. In certain embodiments, the second charge-trapping layer 926 may be formed up to 90 Å thick, of which 30-70 Å may be consumed by radical oxidation to form the blocking dielectric 918. A ratio of thicknesses between the first charge-trapping layer 924 and second charge-trapping layer 926 is approximately 1:1 in some embodiments, although other ratios are also possible. In other embodiments, the second charge-trapping layer 926 may comprise a high K dielectric. Suitable high K dielectrics include hafnium based materials such as HfSiON, HfSiO or HfO, Zirconium based material such as ZrSiON, ZrSiO or ZrO, and Yttrium based material such as Y2O3.
Referring again to
The multi-layer blocking dielectric 918 can be formed by oxidizing a top portion of the second charge-trapping layer 926 to form a first dielectric layer 918a having a first dielectric constant and, subsequently, depositing a material having a second dielectric constant above the first dielectric layer to form a second dielectric layer 918b, wherein the second dielectric constant is greater than the first dielectric constant. It will be appreciated that the thickness of the second charge-trapping layer 926 may be adjusted or increased as some of the second charge-trapping layer will be effectively consumed or oxidized during the process of thermally growing the first dielectric layer 918a. In one embodiment, forming the first dielectric layer 918a is accomplished using a radical oxidation process, such as In-Situ Steam Generation (ISSG). ISSG can be accomplished by placing the substrate 906 in a deposition or processing chamber, heating the substrate to a temperature from about 700° C. to about 850° C., and exposing it to a wet vapor for a predetermined period of time selected based on a desired thickness of the finished first dielectric layer 918a. Exemplary process times are from about 5 to about 20 minutes. The oxidation can be performed at atmospheric or at low pressure.
In other embodiments, forming the multi-layer blocking dielectric 918 comprises depositing at least two different materials, including depositing a first material having a first dielectric constant to form the first dielectric layer 918a and, subsequently, depositing a material having a second dielectric constant to form the second dielectric layer 918b. In certain embodiments, the first dielectric layer 918a is a high temperature oxide deposited in a high-temperature oxide (HTO) process. Generally, the HTO process involves exposing the substrate 906 with the split charge-trapping region 914 formed thereon to a silicon source, such as silane, chlorosilane, or dichlorosilane, and an oxygen-containing gas, such as O2 or N2O in a chemical vapor deposition (CVD) chamber at a pressure of from about 50 mT to about 1000 mT, for a period of from about 10 minutes to about 120 minutes while maintaining the substrate at a temperature of from about 650° C. to about 850° C.
Alternatively, either or both of the first dielectric layer 918a and the second dielectric layer 918b may comprise a high K dielectric formed by any technique, composed of any materials, and have any thicknesses as described above in association with first dielectric layer 506 and second dielectric layer 508, respectively, from
In other embodiments, such as that shown in
In one embodiment, the graded blocking dielectric layer 930 has a low-to-high gradient in the direction from the second charge-trapping layer 926 to the top surface of the graded blocking dielectric layer. Graded blocking dielectric layer 930 may be formed by any technique, composed of any materials, and have any thicknesses described in association with graded blocking dielectric layers 604C and 804C, respectively, from
In another specific embodiment, forming the graded blocking dielectric layer 930 from at least two different materials includes depositing a first dielectric layer having a first dielectric constant and, subsequently, depositing a second dielectric layer having a second dielectric constant, wherein the second dielectric constant is greater than the first dielectric constant, and annealing the graded blocking dielectric layer 930 to cause materials of the first and second dielectric layers to diffuse at a boundary thereof. Alternatively, the graded blocking dielectric can be formed in a single a CVD processing step by changing process gases, ratios or flow rates to form a graded blocking dielectric having different stoichiometric composition across a thickness of the layer.
As with the multi-layer embodiment described above, either or both of the materials of the first second dielectric layers may comprise a high K dielectric formed by any suitable technique, and having any thicknesses. Suitable high K dielectrics materials include hafnium based materials such as HfSiON, HfSiO or HfO, Zirconium based material such as ZrSiON, ZrSiO or ZrO, and Yttrium based material such as Y2O3.
A split charge-trapping region is formed abutting the tunnel oxide (module 1006). Generally, the split charge-trapping region comprises a first charge-trapping layer including a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The individual layers of the split charge-trapping region can include silicon oxides, silicon oxynitrides and silicon nitrides having various stoichiometric compositions of oxygen, nitrogen and/or silicon, and may deposited or grown by any conventional technique, such as, but not limited to thermally grown oxides, radical oxidation and CVD processes, as described above. In some embodiments, the split charge-trapping region can further include a thin, anti-tunneling oxide layer separating the first charge-trapping layer from the second charge-trapping layer.
Next, a multi-layer or graded blocking dielectric comprising at least a first material having a first dielectric constant and a second material having a second dielectric constant greater than the first dielectric constant is formed abutting the split charge-trapping region. In some embodiments, the blocking dielectric comprises a multi-layer blocking dielectric including at least a first dielectric layer formed abutting the split charge-trapping region, and a second dielectric layer formed above first dielectric layer (module 1008). In other embodiments, the blocking dielectric comprises a graded blocking dielectric with no distinct interface between the first and second materials (module 1010). As described above in association with graded blocking dielectric layer 930, from
Finally, a gate layer is formed overlying the blocking dielectric to form a control gate of the memory device (module 1012). In some embodiments, the gate layer a high work-function gate layer and can include a metal-containing material formed by physical vapor deposition and may include, but is not limited to, metal nitrides, metal carbides, metal silicides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt and nickel. In other embodiments, a doped polysilicon may be deposited instead of metal to provide a polysilicon gate layer. Suitable dopants include, for example a p-type dopant such as Boron, to provide a P+ polysilicon gate.
In another embodiment, shown in
Referring to
In accordance with the present disclosure, the non-planar multigate memory device 1100 of
The split charge-trapping region includes at least one inner charge-trapping layer 1120 comprising nitride closer to the tunnel oxide 1114, and an outer charge-trapping layer 1122 overlying the inner charge-trapping layer. Generally, the outer charge-trapping layer 1122 comprises a silicon-rich, oxygen-lean nitride layer and comprises a majority of a charge traps distributed in multiple charge-trapping layers, while the inner charge-trapping layer 1120 comprises an oxygen-rich nitride or silicon oxynitride, and is oxygen-rich relative to the outer charge-trapping layer to reduce the number of charge traps therein.
In some embodiments, such as that shown, the split charge-trapping region further includes at least one thin, intermediate or anti-tunneling layer 1124 comprising a dielectric, such as an oxide, separating outer charge-trapping layer 1122 from the inner charge-trapping layer 1120. The anti-tunneling layer 1124 substantially reduces the probability of electron charge that accumulates at the boundaries of outer charge-trapping layer 1122 during programming from tunneling into the inner charge-trapping layer 1120, resulting in lower leakage current.
As with the embodiments described above, either or both of the inner charge-trapping layer 1120 and the outer charge-trapping layer 1122 can comprise silicon nitride or silicon oxynitride, and can be formed, for example, by a CVD process including N2O/NH3 and DCS/NH3 gas mixtures in ratios and at flow rates tailored to provide a silicon-rich and oxygen-rich oxynitride layer. The second nitride layer of the multi-layer charge storing structure is then formed on the middle oxide layer. The outer charge-trapping layer 1122 has a stoichiometric composition of oxygen, nitrogen and/or silicon different from that of the inner charge-trapping layer 1120, and may also be formed or deposited by a CVD process using a process gas including DCS/NH3 and N2O/NH3 gas mixtures in ratios and at flow rates tailored to provide a silicon-rich, oxygen-lean top nitride layer.
In those embodiments including an intermediate or anti-tunneling layer 1124 comprising oxide, the anti-tunneling layer can be formed by oxidation of the inner charge-trapping layer 1120, to a chosen depth using radical oxidation. Radical oxidation may be performed, for example, at a temperature of 1000-1100° C. using a single wafer tool, or 800-900° C. using a batch reactor tool. A mixture of H2 and O2 gasses may be employed at a pressure of 300-500 Tor for a batch process, or 11-15 Tor using a single vapor tool, for a time of 1-2 minutes using a single wafer tool, or 30 min-1 hour using a batch process.
A suitable thickness for the inner charge-trapping layer 1120 may be from about 30 Å to about 80 Å (with some variance permitted, for example ±10 A), of which about 5-20 Å may be consumed by radical oxidation to form the anti-tunneling layer 1124. A suitable thickness for the outer charge-trapping layer 1122 may be at least 30 Å. In certain embodiments, the outer charge-trapping layer 1122 may be formed up to 90 Å thick, of which 30-70 Å may be consumed by radical oxidation to form the blocking dielectric. A ratio of thicknesses between the inner charge-trapping layer 1120 and the outer charge-trapping layer 1122 is approximately 1:1 in some embodiments, although other ratios are also possible.
In other embodiments, either or both of the outer charge-trapping layer 1122 and the blocking dielectric 1116a, 1116b, may comprise a high K dielectric. Suitable high K dielectrics include hafnium based materials such as HfSiON, HfSiO or HfO, Zirconium based material such as ZrSiON, ZrSiO or ZrO, and Yttrium based material such as Y2O3.
Referring again to
The multi-layer blocking dielectric 1116a, 1116b, can be formed by oxidizing a top portion of the outer charge-trapping layer 1122 to form a first dielectric layer 1116a having a first dielectric constant and, subsequently, depositing a material having a second dielectric constant above the first dielectric layer to form a second dielectric layer 1116b, wherein the second dielectric constant is greater than the first dielectric constant. It will be appreciated that the thickness of the outer charge-trapping layer 1122 may be adjusted or increased as some of the outer charge-trapping layer will be effectively consumed or oxidized during the process of thermally growing the first dielectric layer 1116a. In one embodiment, forming the first dielectric layer 1116a is accomplished using a radical oxidation process, such as In-Situ Steam Generation (ISSG). ISSG can be accomplished by placing the substrate 1106 in a deposition or processing chamber, heating the substrate to a temperature from about 700° C. to about 850° C., and exposing it to a wet vapor for a predetermined period of time selected based on a desired thickness of the finished first dielectric layer 1116a. Exemplary process times are from about 5 to about 20 minutes. The oxidation can be performed at atmospheric or at low pressure.
In other embodiments, forming the multi-layer blocking dielectric 1116a, 1116b, comprises depositing at least two different materials, including depositing a first material having a first dielectric constant to form the first dielectric layer 1116a and, subsequently, depositing a material having a second dielectric constant to form the second dielectric layer 1116b. In certain embodiments, the first dielectric layer 1116a is a high temperature oxide deposited in a high-temperature oxide (HTO) process. Generally, the HTO process involves exposing the substrate 1106 with the split charge-trapping region formed thereon to a silicon source, such as silane, chlorosilane, or dichlorosilane, and an oxygen-containing gas, such as O2 or N2O in a chemical vapor deposition (CVD) chamber at a pressure of from about 50 mT to about 1000 mT, for a period of from about 10 minutes to about 120 minutes while maintaining the substrate at a temperature of from about 650° C. to about 850° C.
Alternatively, either or both of the first dielectric layer 1116a and the second dielectric layer 1116b may comprise a high K dielectric formed by any technique, composed of any materials, and have any thicknesses as described above in association with first dielectric layer 506 and second dielectric layer 508, respectively, from
In other embodiments (not shown), the blocking dielectric is fabricated to be or include a graded blocking dielectric layer, such as graded blocking dielectric layer 930, shown in
In one embodiment, the graded blocking dielectric layer has a low-to-high gradient in the direction from the outer charge-trapping layer 1122 to a top surface of the blocking dielectric 1116. The graded blocking dielectric layer may be formed by any technique, composed of any materials, and have any thicknesses described in association with graded blocking dielectric layers 604C and 804C, respectively, from
As with the multi-layer embodiment described above, either or both of the materials of the first second dielectric layers may comprise a high K dielectric formed by any suitable technique, and having any thicknesses. Suitable high K dielectrics materials include hafnium based materials such as HfSiON, HfSiO or HfO, Zirconium based material such as ZrSiON, ZrSiO or ZrO, and Yttrium based material such as Y2O3.
In another embodiment, the memory device is or includes a non-planar device comprising a vertical nanowire channel formed in or from a semiconducting material projecting above or from a number of conducting, semiconducting layers on a substrate. In one version of this embodiment, shown in cut-away in
In some embodiments, such as that shown in
Referring to
As with the embodiments described above, either or both of the first charge trapping layer 1216 and the second charge trapping layer 1218 can comprise silicon nitride or silicon oxynitride, and can be formed, for example, by a CVD process including N2O/NH3 and DCS/NH3 gas mixtures in ratios and at flow rates tailored to provide a silicon-rich and oxygen-rich oxynitride layer.
Finally, either or both of the second charge trapping layer 1218 and the blocking dielectric 1212 may comprise a high K dielectric, such as HfSiON, HfSiO, HfO, ZrSiON, ZrSiO, ZrO, or Y2O3.
Referring again to
The multi-layer blocking dielectric 1212 can be formed by oxidizing a top portion of the outer charge-trapping layer 1218 to form a first dielectric layer 1212a having a first dielectric constant and, subsequently, depositing a material having a second dielectric constant above the first dielectric layer to form a second dielectric layer 1212b, wherein the second dielectric constant is greater than the first dielectric constant. It will be appreciated that the thickness of the outer charge-trapping layer 1218 may be adjusted or increased as some of the outer charge-trapping layer will be effectively consumed or oxidized during the process of thermally growing the first dielectric layer 1212a. In one embodiment, forming the first dielectric layer 1212a is accomplished using a radical oxidation process, such as In-Situ Steam Generation (ISSG). ISSG can be accomplished by placing the substrate 1106 in a deposition or processing chamber, heating the substrate to a temperature from about 700° C. to about 850° C., and exposing it to a wet vapor for a predetermined period of time selected based on a desired thickness of the finished first dielectric layer 1212a. Exemplary process times are from about 5 to about 20 minutes. The oxidation can be performed at atmospheric or at low pressure.
In other embodiments, forming the multi-layer blocking dielectric 1212a, 1212b, comprises depositing at least two different materials, including depositing a first material having a first dielectric constant to form the first dielectric layer 1212a and, subsequently, depositing a material having a second dielectric constant to form the second dielectric layer 1212b. In certain embodiments, the first dielectric layer 1212a is a high temperature oxide deposited in a high-temperature oxide (HTO) process. Generally, the HTO process involves exposing the substrate 1106 with the split charge-trapping region formed thereon to a silicon source, such as silane, chlorosilane, or dichlorosilane, and an oxygen-containing gas, such as O2 or N2O in a chemical vapor deposition (CVD) chamber at a pressure of from about 50 mT to about 1000 mT, for a period of from about 10 minutes to about 120 minutes while maintaining the substrate at a temperature of from about 650° C. to about 850° C.
Alternatively, either or both of the first dielectric layer 1212a and the second dielectric layer 1212b may comprise a high K dielectric formed by any technique, composed of any materials, and have any thicknesses as described above in association with first dielectric layer 506 and second dielectric layer 508, respectively, from
In other embodiments (not shown), the blocking dielectric is fabricated to be or include a graded blocking dielectric layer, such as graded blocking dielectric layer 930, shown in
In one embodiment, the graded blocking dielectric layer has a low-to-high gradient in the direction from the outer charge-trapping layer 1218 to a top surface of the blocking dielectric 1212. The graded blocking dielectric layer may be formed by any technique, composed of any materials, and have any thicknesses described in association with graded blocking dielectric layers 604C and 804C, respectively, from
As with the multi-layer embodiment described above, either or both of the materials of the first second dielectric layers may comprise a high K dielectric formed by any suitable technique, and having any thicknesses. Suitable high K dielectrics materials include hafnium based materials such as HfSiON, HfSiO or HfO, Zirconium based material such as ZrSiON, ZrSiO or ZrO, and Yttrium based material such as Y2O3.
The memory device 1200 of
Referring to
Referring to
Referring to
As described above, either or both of the first dielectric layer 1314a and the second dielectric layer 1314b may comprise an oxide, nitride, oxynitride or a high K dielectric formed by any technique, composed of any materials, and have any thicknesses as described above in association with first dielectric layer 506 and second dielectric layer 508, respectively, from
In other embodiments (not shown), the blocking dielectric is fabricated to be or include a graded blocking dielectric layer, such as graded blocking dielectric layer 930, shown in
In some embodiments, such as that shown in
Next, a second or channel opening 1320 is anisotropically etched through tunneling oxide 1318, charge-trapping region 1316, and blocking dielectric 1314,
Referring to
Referring to
Referring to
Referring to
The blocking dielectric can comprise a multi-layer blocking dielectric region abutting the outer charge-trapping layer 1416b. In the embodiment shown the multi-layer blocking dielectric is a bi-layer blocking dielectric and includes a first dielectric layer 1418a formed on the sidewall of opening of 1312 and a second dielectric layer 1418b formed above first dielectric layer. First dielectric layer 1418a and second dielectric layer 1418b may be formed by any technique, composed of any materials, and have any thicknesses described above in association with first dielectric layer 918a and second dielectric layer 918b, respectively. Generally, the multi-layer blocking dielectric is formed from at least two different materials and has an abrupt interface between first dielectric layer 1418a and second dielectric layer 1418b, as depicted in
As described above, either or both of the first dielectric layer 1418a and the second dielectric layer 1418b may comprise an oxide, nitride, oxynitride or a high K dielectric formed by any technique, composed of any materials, and have any thicknesses as described above in association with first dielectric layer 506 and second dielectric layer 508, respectively, from
In other embodiments (not shown), the blocking dielectric is fabricated to be or include a graded blocking dielectric layer, such as graded blocking dielectric layer 930, shown in
Next, a gate layer 1422 is deposited into the second opening 1412 and the surface of the upper dielectric layer 1402 planarized to yield the intermediate structure illustrated in
Thus, nonvolatile charge trap memory devices have been disclosed. The devices each include a substrate having a channel region and a pair of source and drain regions. A gate stack is above the substrate over the channel region and between the pair of source and drain regions. In accordance with an embodiment of the present invention, the gate stack includes a high dielectric constant blocking region. In one embodiment, the high dielectric constant blocking region is a bi-layer blocking dielectric region. In another embodiment, the high dielectric constant blocking region is a graded blocking dielectric layer.
This application is a continuation of application Ser. No. 13/436,875, filed Mar. 31, 2012, Now U.S. Pat. No. 9,431,549, Issued Aug. 30, 2016, which is a continuation-in-part of U.S. application Ser. No. 13/114,889, filed May 24, 2011, Now U.S. Pat. No. 8,860,122, Issued Oct. 14, 2014, which is a divisional application of U.S. patent application Ser. No. 12/030,644, filed Feb. 13, 2008, Now abandoned, which claims the benefit of U.S. Provisional Application No. 61/007,566, filed Dec. 12, 2007, the entire contents of which are hereby incorporated by reference herein
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| Number | Date | Country | |
|---|---|---|---|
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| Number | Date | Country | |
|---|---|---|---|
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| Number | Date | Country | |
|---|---|---|---|
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| Child | 13114889 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 13436875 | Mar 2012 | US |
| Child | 15252059 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 13114889 | May 2011 | US |
| Child | 13436875 | US |
