The present disclosure relates generally to an optical package structure.
Liquid crystal polymer (LCP) lid may be used for optical shielding between an emitter and a receiver of an optical package structure, and the emitter is usually electrically connected to a substrate of the optical package structure through a bond wire. However, the LCP lid usually has a relatively large thickness, and the loop height of the bond wire may increase the overall thickness of the optical package structure.
In one or more arrangements, an optical package structure includes a first substrate, a second substrate, a first optical component, a second optical component, and an electrical shielding element. The second substrate is over the first substrate. The first substrate and the second substrate collectively define a first cavity. The first optical component is disposed in the first cavity. The second optical component is disposed over the first substrate. The electrical shielding element is disposed adjacent to a sidewall of the first cavity and between the first optical component and the second optical component.
In one or more arrangements, an optical package structure includes a first substrate, a second substrate, an adhesive layer, and a shielding structure. The first substrate includes a first circuit structure. The second substrate includes a second circuit structure. The adhesive layer is between the first substrate and the second substrate. The shielding structure is at least partially encapsulated by the adhesive layer and configured to reduce an electromagnetic interference between the first circuit structure and the second circuit structure.
In one or more arrangements, an optical package structure includes a substrate structure, an optical receiver, and a limitation structure. The optical receiver is over the substrate structure. The limitation structure is over the substrate structure and configured to reduce a first light reflected from the limitation structure to the optical receiver.
Aspects of the present disclosure are better understood from the following detailed description when read with the accompanying drawings. It is noted that various features may not be drawn to scale, and the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Common reference numerals are used throughout the drawings and the detailed description to indicate the same or similar elements.
The substrates 10 and 20 may independently include, for example, a printed circuit board, such as a paper-based copper foil laminate, a composite copper foil laminate, or a polymer-impregnated glass-fiber-based copper foil laminate. The substrates 10 and 20 may independently include an interconnection structure, which may include such as a plurality of conductive traces and/or a plurality of conductive vias. The interconnection structure may include a redistribution layer (RDL) and/or a grounding element. In some arrangements, the substrates 10 and 20 may independently include an organic substrate or a leadframe. In some arrangements, the substrates 10 and 20 may independently include a ceramic material or a metal plate. In some arrangements, the substrates 10 and 20 may independently include a two-layer substrate which includes a core layer and a conductive material and/or structure disposed on an upper surface (or a top surface) and a lower surface (or a bottom surface) of the substrate. The substrates 10 and 20 may independently include a semiconductor wafer or an electronic component. The electronic component may be a chip or a die including a semiconductor substrate, one or more integrated circuit devices and one or more overlying interconnection structures therein. The integrated circuit devices may include active devices such as transistors and/or passive devices such resistors, capacitors, inductors, or a combination thereof. The substrates 10 and 20 may independently include one or more conductive elements, surfaces, contacts, or pads.
In some arrangements, the substrate 10 includes a base layer 10A and a circuit structure 10R. The base layer 10A may be or include a semiconductor layer or a dielectric layer. In some arrangements, the circuit structure 10R includes a plurality of conductive layers (e.g., conductive layers 110, 101, 102, 103, 101A, 102A, 103A, and 10g) and a plurality of conductive vias (e.g., conductive vias 10V1, 10V2, 10V3, and 10V4) electrically connected to corresponding conductive layers. In some arrangements, the conductive vias 10V1, 10V2, 10V3, and 10V4 penetrate the base layer 10A. In some arrangements, the conductive vias 10V1, 10V2, 10V3, and 10V4 taper toward the substrate 20. In some arrangements, the conductive layer 10g may serve as or connect to a ground element.
In some arrangements, the substrate 20 is disposed over the substrate 10. In some arrangements, the substrate 20 is electrically connected to the substrate 10. In some arrangements, the substrates 10 and 20 collectively define a cavity C1 (also referred to as “a recess” or “a space”). The cavity C1 may accommodate one or more optical components. In some arrangements, the conductive layer 110 (or a top surface 111 of the substrate 10) is exposed to the cavity C1. In some arrangements, the substrate 20 includes the cavity C1. In some arrangements, the substrate 20 further includes or defines a cavity C2 (also referred to as “a recess” or “a space”). The cavity C2 may accommodate one or more optical components. In some arrangements, the substrate 20 includes a base layer 20A and a circuit structure 20R. The base layer 20A may be or include a semiconductor layer or a dielectric layer. In some arrangements, the circuit structure 20R includes a plurality of conductive layers (e.g., conductive layers 210, 220, 230, 210A, 220A, and 230A) and a plurality of conductive vias (e.g., conductive vias 20V1, 20V2, and 20V3) electrically connected to corresponding conductive layers. In some arrangements, the conductive vias 20V1, 20V2, and 20V3 penetrate the base layer 20A. In some arrangements, the conductive layers 210 and 220 are exposed to the cavity C2. In some arrangements, the circuit structure 20R is disposed over the circuit structure 10R. The substrate 20 may have a surface 201 (also referred to as “a top surface”), a surface 202 opposite to the surface 201, surfaces 203 and 204 (also referred to as “lateral surface”) extending between the surface 201 and the surface 202.
In some arrangements, the conductive layer, pads, or contacts may independently include a conductive material such as a metal or metal alloy. Examples include gold (Au), silver (Ag), aluminum (Al), copper (Cu), or an alloy thereof. The dielectric layers may independently include an organic material, a solder mask, PI, an ABF, one or more molding compounds, one or more pre-impregnated composite fibers (e.g., a pre-preg material), borophosphosilicate glass (BPSG), silicon oxide, silicon nitride, silicon oxynitride, undoped silicate glass (USG), any combination thereof, or the like. In some arrangements, the substrate 10 is referred to as a substrate structure of the optical package structure 1A. In some arrangements, the substrates 10 and 20 construct a substrate structure of the optical package structure 1A.
The optical emitter 30 (also referred to as “optical emitting device” or “light emitting device”) may be embedded in the substrate structure. In some arrangements, the optical emitter 30 is disposed in the cavity C1. In some arrangements, the optical emitter 30 is electrically connected to the substrate 10. In some arrangements, the optical emitter 30 is disposed on the circuit structure 10R. In some arrangements, the optical emitter 30 is electrically connected to the circuit structure 10R. In some arrangements, the optical emitter 30 is electrically connected to the substrate 20. In some arrangements, the optical emitter 30 is wire-bonded to the substrate 20. In some arrangements, the conductor (e.g., the conductive wire 90) is directly connected to the optical emitter 30 and the substrate 20. In some arrangements, the optical emitter 30 has a surface 301 (also referred to as “a top surface”) and a surface 302 opposite to the surface 301. In some arrangements, the surface 301 is electrically connected to the conductive layer 230 through the conductive wire 90 (or the conductor), and the surface 302 is electrically connected to the conductive layer 110. In some arrangements, the optical emitter 30 includes two electrodes 310 and 320 on opposite surfaces (e.g., the surfaces 301 and 302) electrically connected to the conductive layer 110 and the conductive layer 230, respectively. In some arrangements, the electrode 310 is electrically connected to the conductive layer 110A through the conductive layer 110 and the conductive via 10V1. In some arrangements, the electrode 320 is electrically connected to the substrate 10 through the conductive wire 90, the conductive layer 230, the conductive via 20V3, and the conductive layer 230A. In some arrangements, the electrode 320 is electrically connected to the conductive layer 103A through the conductive wire 90, the substrate 20, a conductive via 230V, the conductive layer 103, and the conductive via 10V2.
The optical receiver 40 (also referred to as “optical receiving device” or “light receiving device”) may be disposed over the substrate structure. In some arrangements, the optical receiver 40 is disposed over the substrate 10. In some arrangements, the optical receiver 40 is disposed in the cavity C2. In some arrangements, the optical receiver 40 is electrically connected to the substrate 20. In some arrangements, the optical receiver 40 is disposed on the circuit structure 20R. In some arrangements, the optical receiver 40 is electrically connected to the circuit structure 20R. In some arrangements, the optical receiver 40 is flip-chip bonded to the substrate 20. In some arrangements, the optical receiver 40 has a surface 401 (also referred to as “a top surface”) and a surface 402 opposite to the surface 401. In some arrangements, the surface 302 is electrically connected to the conductive layers 210 and 220. In some arrangements, the optical receiver 40 includes two electrodes 410 and 420 on the surface 402 electrically connected to the conductive layers 210 and 220, respectively. In some arrangements, the electrode 410 is electrically connected to the conductive layer 101A through the conductive layer 210, the conductive via 20V1, the conductive layer 210A, a conductive via 210V, the conductive layer 101, and the conductive via 10V3. In some arrangements, the electrode 420 is electrically connected to the conductive layer 102A through the conductive layer 220, the conductive via 20V2, the conductive layer 220A, a conductive via 220V, the conductive layer 102, and the conductive via 10V4. In some arrangements, an elevation of the optical receiver 40 is higher than an elevation of the optical emitter 30 with respect to the substrate 10. In some arrangements, the surface 401 (or the top surface) of the optical receiver 40 is higher than an elevation of a top portion of the cavity C1 with respect to the substrate 10.
In some arrangements, the shielding structure may be configured to reduce an electromagnetic interference between the circuit structure 10R and the circuit structure 20R. In some arrangements, the shielding structure may include a portion between the optical emitter 30 and the optical receiver 40 and configured to reduce a light interference therebetween. In some arrangements, the shielding structure may further include a connection portion extending into the substrate 10 and electrically connected to a ground element of the substrate 10. In some arrangements, the shielding structure may include an electrical shielding element 50, a connection portion 50R (also referred to as “a connection element”), and a via portion 50V (also referred to as “a conductive via”). In some arrangements, the shielding structure is at least partially encapsulated by the adhesive layer 60. In some arrangements, the shielding structure may include a conductive material, for example, a metal material. The examples may include aluminum (Al), copper (Cu), chromium (Cr), tin (Sn), gold (Au), silver (Ag), nickel (Ni) or stainless steel, or a mixture, an alloy, or other combination thereof.
In some arrangements, the electrical shielding element 50 includes a portion 510 (also referred to as “a vertical portion”) and a portion 520 (also referred to as “a horizontal portion”). In some arrangements, the electrical shielding element 50 (or the portion 510) is disposed between the optical emitter 30 and the optical receiver 40. In some arrangements, the portion 510 is configured to reduce a light interference between the optical emitter 30 and the optical receiver 40. In some arrangements, the portion 510 is referred to as a block structure disposed adjacent to the cavity C1 and configured to reflect a light from the optical emitter 30. In some arrangements, the electrical shielding element 50 (or the portion 510) is disposed adjacent to a sidewall 205 of the cavity C1. In some arrangements, the electrical shielding element 50 (or the portion 510) covers the sidewall 205 of the cavity C1. In some arrangements, the electrical shielding element 50 (or the portion 510) extends along the sidewall 205 of the cavity C1. In some arrangements, the electrical shielding element 50 (or the portion 510) extends along the sidewall 205 to an end portion (e.g., the surface 202) of the substrate 20 facing the substrate 10. In some arrangements, the portion 510 further includes a vertical part 512 and an extension 511. In some arrangements, the extension 511 partially covers the surface 201 of the substrate 20. In some arrangements, the vertical part 512 covers the sidewall 205 of the cavity C1. In some arrangements, referring to
In some arrangements, the electrical shielding element 50 (or the portion 520) is between the circuit structure 10R and the circuit structure 20R. In some arrangements, the circuit structure 20R at least partially vertically overlaps the portion 520 of the shielding structure. In some arrangements, the portion 520 is disposed on the surface 202 of the substrate 20. In some arrangements, the portion 520 includes a plurality of horizontal parts between the conductive layers 210A, 220A, and 230A.
In some arrangements, the connection portion 50R (or the connection element) electrically connects the electrical shielding element 50 to a ground element (e.g., the conductive layer 10g). In some arrangements, the portion 510 is electrically connected to the ground element (e.g., the conductive layer 10g) through the connection portion 50R. In some arrangements, the connection portion 50R includes a conductive via 510V and a conductive layer 105. The portion 510 is electrically connected to the ground element (e.g., the conductive layer 10g) through the conductive via 510V and the conductive layer 105.
In some arrangements, the via portion 50V (or the conductive via) is disposed or formed in the substrate 10 and electrically connects the connection portion 50R to the ground element (e.g., the conductive layer 10g). In some arrangements, the via portion 50V extends into the substrate 10 and electrically connects to the ground element (e.g., the conductive layer 10g). In some arrangements, the via portion 50V penetrates the base layer 10A of the substrate 10. In some arrangements, the via portion 50V tapers toward the substrate 20.
The adhesive layer 60 may between the substrate 10 and the substrate 20. In some arrangements, the adhesive layer 60 is configured to adhere the substrate 10 and the substrate 20. In some arrangements, the adhesive layer 60 encapsulates the portion 520 and the connection portion 50R. In some arrangements, the adhesive layer 60 encapsulates the portion 520, the conductive via 510V, and the conductive layer 105. In some arrangements, the adhesive layer 60 directly contacts the electrical shielding element 50 (or the portion 520). In some arrangements, the adhesive layer 60 directly contacts the portion 520, the conductive via 510V, and the conductive layer 105. In some arrangements, the adhesive layer 60 at least partially encapsulates the conductive layers 110, 102, 103, and 104 of the circuit structure 10R. In some arrangements, the adhesive layer 60 directly contacts the conductive layers 110, 102, 103, and 104 of the circuit structure 10R. In some arrangements, the adhesive layer 60 at least partially encapsulates the conductive layers 210A, 220A, and 230A of the circuit structure 20R. In some arrangements, the adhesive layer 60 directly contacts the conductive layers 210A, 220A, and 230A of the circuit structure 20R. In some arrangements, the adhesive layer 60 is spaced apart from the cavity C1. In some arrangements, the conductive layer 110 is exposed to the cavity C1 and spaced apart from the electrical shielding element 50 by the adhesive layer 60.
The barrier 70 may be disposed over the substrate structure. The barrier 70 may be or include a limitation structure configured to define a receiving range of an optical signal received by the optical receiver 40. In some arrangements, the limitation structure (or the barrier 70) is over the substrate structure (e.g., the substrate 10 or the combination of the substrates 10 and 20) and configured to reduce a light reflected from the limitation structure to the optical receiver 40. In some arrangements, the portion 510 (or the block structure) is disposed adjacent to the cavity C1 and configured to reflect a light from the optical emitter 30. In some arrangements, the portion 510 (or the block structure) and the barrier 70 (or the limitation structure) are disposed between the optical emitter 30 and the optical receiver 40. In some arrangements, the barrier 70 is formed of or includes an optical blocking material or a light absorbing material. In some arrangements, the barrier 70 has an optical transmittance (or a light transmittance) of no greater than about 10%, 5%, 3%, or 1%, with respect to a peak wavelength or a range of wavelengths of an optical signal (a light) emitted by the optical emitter 30. In some arrangements, the barrier 70 has an optical transmittance (or a light transmittance) of no greater than about 10%, 5%, 3%, or 1%, with respect to a peak wavelength or a range of wavelengths of an optical signal (a light) received by the optical receiver 40. The barrier 70 may be referred to as a light block structure. In some arrangements, at least a portion of the barrier 70 (or the light block structure) is over the substrate 20 and between the optical emitter 30 and the optical receiver 40. In some arrangements, the barrier 70 includes through holes C3 and C4. In some arrangements, the through hole C3 is over the optical emitter 30 and wider than the cavity C1. In some arrangements, the through hole C4 is over the optical receiver 40. In some arrangements, a roughness (e.g., a surface roughness) of a sidewall 705 of the through hole C3 is greater than a roughness (e.g., a surface roughness) of a top surface 701 of the barrier 70. In some arrangements, a roughness (e.g., a surface roughness) of a sidewall 707 of the through hole C4 is greater than a roughness (e.g., a surface roughness) of a top surface 701 of the barrier 70. In some arrangements, the barrier 70 is or includes a core substrate layer (e.g., a black core layer). In some arrangements, the barrier 70 includes a resin layer. In some arrangements, the barrier 70 is substantially free of glass fibers. In some arrangements, the barrier 70 may be omitted depending on the thickness (or the height) of the optical receiver 40. In some arrangements, the barrier 70 may be omitted when the optical receiver 40 is substantially entirely received within the cavity C2.
The protective layer 80 may be between the substrate 10 and the substrate 20. In some arrangements, the protective layer 80 is partially exposed to the cavity C1. In some arrangements, the conductive layer 110 is spaced apart from the electrical shielding element 50 by the protective layer 80. In some arrangements, the protective layer 80 directly contacts the conductive layer 110 and the electrical shielding element 50. In some arrangements, the protective layer 80 directly contacts the adhesive layer 60. The protective layer 80 may be or include a solder mask. In some arrangements, the conductive layer 110 is exposed to the cavity C1 and spaced apart from the electrical shielding element 50 by the protective layer 80.
The protective layer 81 may be between the barrier 70 and the substrate 20. The protective layer 82 may partially cover the conductive layers 10g, 110A, 101A, 102A, and 103A. The protective layers 81 and 82 may be or include solder masks.
According to some arrangements of the present disclosure, the optical emitter is disposed in a cavity defined by stacked substrates, and an electrical shielding element is adjacent to a sidewall of the cavity and between the optical emitter and the optical receiver. Therefore, crosstalk between the optical emitter and the optical receiver can be effectively prevented by the electrical shielding element. In addition, the loop height of the conductive wire for bonding the optical emitter to the substrates can be reduced by lowering the elevation of the optical emitter lowered with respect to the substrate or to the optical receiver without thinning the optical emitter. Therefore, the overall thickness of the optical package structure can be reduced, and the processing risk for thinning the optical emitter can be omitted, which is advantageous to increasing the yield.
In addition, according to some arrangements of the present disclosure, the electrical shielding element surrounds the optical emitter. Therefore, an improved optical shielding effect between the optical emitter and the optical receiver can be provided.
Moreover, according to some arrangements of the present disclosure, the horizontal portion of the electrical shielding element is disposed between the circuit structure connected to the optical emitter and the circuit structure connected to the optical receiver. Therefore, interference between the circuit structures connected can be effectively reduced.
In addition, according to some arrangements of the present disclosure, cavities are formed in the substrate without damaging, partially removing, or cutting through the conductive features (e.g., the conductive layers, the conductive vias, and the like) of the circuit structure of the substrate. As a result, even with the optical emitter and the optical receiver disposed in the cavities of the substrate, the electrical shielding element is not damaged, the coverage of the electrical shielding element is not reduced, and the original design of the circuit structure is not damages or altered. Therefore, the interference between the circuit structures connected can be effectively reduced by the electrical shielding element while the size of the optical package structure is significantly reduced.
Furthermore, in some cases the barrier for an optical package structure is formed by injecting a liquid crystal polymer (LCP) material into a mold having a predetermined shape, curing the LCP material, and removing the mold from the cured LCP material to form the barrier with the predetermined shape. Due to the processing limit of the above method and the property of the LCP material, the size of the as-formed barrier is relatively large, resulting in an increased thickness of the optical package structure. In contrast, according to some arrangements of the present disclosure, the barrier is or includes a black core layer with the through holes formed by drilling. Therefore, the black core layer may be formed with a relatively small thickness, e.g., less than about 200 μm or lower, and thus the overall thickness of the optical package structure can be further reduced, which is advantageous to the reduction of the size of the optical package structure. Moreover, the barrier (or the limitation structure) may be formed of or include a black core layer which absorbs lights instead of reflecting lights, and thus the light reflected by the barrier to the optical receiver may be reduced. Furthermore, due to the relatively large roughness of the sidewalls of the barrier (or the limitation structure) resulted from the drilling operation for forming the through holes, the light reflected by the barrier may be scattered toward outside of the cavities, and thus the light reflected by the barrier to the optical receiver may be further reduced. In addition, the barrier may be free of glass fibers. Therefore, leakage of lights resulted from the glass fibers can be further prevented.
Moreover, according to some arrangements of the present disclosure, the optical receiver is disposed over the stacked substrates, and at least partially within a cavity, and the optical receiver is further flip-chip bonded to the substrate instead of wire-bonded to the substrate. Therefore, the optical receiver at an elevation higher than that of the optical emitter with respect to the substrate can receive a relatively large amount of the optical signal, and the overall thickness of the optical package structure can be further reduced as well.
In some arrangements, the connection portion 50R and the via portion 50V of the shielding structure is between the optical emitter 30 and the optical receiver 40. In some arrangements, portions of the circuit structure 20R connected to the optical emitter 30 and portions of the circuit structure 20R connected to the optical receiver 40 are disposed on opposite sides of the electrical shielding element 50 (or the portion 510). In some arrangements, portions of the circuit structure 10R connected to the optical emitter 30 and portions of the circuit structure 10R connected to the optical receiver 40 are disposed on opposite sides of the connection portion 50R and the via portion 50V.
According to some arrangements of the present disclosure, with the arrangements of the electrical shielding element 50, the connection portion 50R, and the via portion 50V, crosstalk between the optical emitter and the optical receiver can be effectively prevented, and the interference between the circuits connected to the optical emitter and the circuits connected to the optical receiver can be effectively reduced as well.
In some arrangements, the optical receiver 40 includes two electrodes 410 and 420 on opposite surfaces (e.g., the surfaces 401 and 402) electrically connected to the conductive layers 210 and 220, respectively. In some arrangements, the electrode 420 is electrically connected to the conductive layer 220 through a conductive wire 92.
In some arrangements, the circuit structure 20R of the substrate 20 includes conductive layers 210, 220, 230, 211, 221, 210A, 220A, and 230A and conductive vias 20V1, 20V2, 20V1a, 20V2a, and 20V3. In some arrangements, the conductive layers 210 and 220 are disposed on the surface 201. In some arrangements, the electrode 410 is electrically connected to the conductive layer 101A through the conductive layer 210, the conductive via 20V1, the conductive layer 211, the conductive via 20V1a, the conductive layer 210A, the conductive via 210V, the conductive layer 101, and the conductive via 10V3. In some arrangements, the electrode 420 is electrically connected to the conductive layer 102A through the conductive layer 220, the conductive via 20V2, the conductive layer 221, the conductive via 20V2a, the conductive layer 220A, the conductive via 220V, the conductive layer 102, and the conductive via 10V4. In some arrangements, the substrate 20 does not include a cavity C2 as shown in
In some arrangements, the electrode 420 of the optical receiver 40 is electrically connected to the conductive layer 220 through the conductive wire 92.
In some arrangements, conductive layers and conductive vias of the substrate 20 that connect the conductive layers 210 and 220 to the substrate 10 are similar to those illustrate in
In some arrangements, the connection portion 50R and the via portion 50V of the shielding structure is between the optical emitter 30 and the optical receiver 40.
In some arrangements, the optical package structure 3A includes optical emitters 30 and 30′ and conductive wires 90 and 90′. In some arrangements, the circuit structure 10R of the substrate 10 further includes conductive layers 110′, 110A′, 103′, and 103A′ and conductive vias 10V1′ and 10V2′. In some arrangements, the circuit structure 20R of the substrate 20 further includes conductive layers 230′ and 230A′ and a conductive via 20V3′.
In some arrangements, the optical emitter 30′ includes two electrodes 310′ and 320′ on opposite surfaces (e.g., the surfaces 301′ and 302′) electrically connected to the conductive layer 110′ and the conductive layer 230′, respectively. In some arrangements, the electrode 310 is electrically connected to the conductive layer 110A′ through the conductive layer 110′ and the conductive via 10V1′. In some arrangements, the electrode 320′ is electrically connected to the substrate 10 through the conductive wire 90′, the conductive layer 230′, the conductive via 20V3′, and the conductive layer 230A′. In some arrangements, the electrode 320′ is electrically connected to the conductive layer 103A′ through the conductive wire 90′, the substrate 20, a conductive via 230V′, the conductive layer 103′, and the conductive via 10V2′.
In some arrangements, the optical package structure 3B includes optical receivers 40 and 40′ and conductive wires 92 and 92′. In some arrangements, the circuit structure 10R of the substrate 10 further includes conductive layers 101′, 101A′, 102′, and 102A′ and conductive vias 10V3′ and 10V4′. In some arrangements, the circuit structure 20R of the substrate 20 further includes conductive layers 210′, 220′, 211′, 221′, 210A′, and 220A′ and conductive vias 20V1′, 20V2′, 20V1a′, and 20V2a′.
In some arrangements, the optical receiver 40′ includes electrodes 410′ and 420′. In some arrangements, the electrode 410′ is electrically connected to the conductive layer 101A′ through the conductive layer 210′, the conductive via 20V1′, the conductive layer 211′, the conductive via 20V1a′, the conductive layer 210A′, the conductive via 210V′, the conductive layer 101′, and the conductive via 10V3′. In some arrangements, the electrode 420′ is electrically connected to the conductive layer 102A′ through the conductive layer 220′, the conductive via 20V2′, the conductive layer 221′, the conductive via 20V2a′, the conductive layer 220A′, the conductive via 220V′, the conductive layer 102′, and the conductive via 10V4′.
In some arrangements, the substrate 20 includes cavities C2 and C2′ for accommodating the optical receivers 40 and 40′, respectively. In some arrangements, the barrier 70 includes through holes C4 and C4′ each over and connected to the cavities C2 and C2′, respectively.
In some arrangements, the optical receivers 40 and 40′ are flip-chip bonded to the substrate 20. In some arrangements, the electrode 410′ of the optical receiver 40′ is electrically connected to the conductive layer 101A′ through the conductive layer 210′, the conductive via 20V1′, the conductive layer 210A′, the conductive via 210V′, the conductive layer 101′, and the conductive via 10V3′. In some arrangements, the electrode 420′ of the optical receiver 40′ is electrically connected to the conductive layer 102A′ through the conductive layer 220′, the conductive via 20V2′, the conductive layer 220A′, the conductive via 220V′, the conductive layer 102′, and the conductive via 10V4′.
It should be noted that the number of optical emitters and the number of the optical receivers in an optical package structure may vary according to actual applications and are not limited to the above examples illustrated in
In some arrangements, a portion of a top surface (e.g., a surface 1011) of the substrate 10 is exposed to the cavity C2. In some arrangements, a portion of the surface 1011 of the conductive layer 101 of the substrate 10 is exposed to the cavity C2. In some arrangements, the adhesive layer 60 is partially exposed to the cavity C2. In some arrangements, the protective layer 80 is partially exposed to the cavity C2.
In some arrangements, the optical receiver 40 is entirely in the cavity C2. In some arrangements, the electrode 410 of the optical receiver 40 is electrically connected to the conductive layer 101A through the conductive layer 101 and the conductive via 10V3.
In some arrangements, the base layer 20A may be or include a black core layer. The substrate 10 may be referred to as a substrate structure, and the combination of the base layer 20A and the barrier 70 may be referred to as a limitation structure over the substrate structure and configured to reduce lights reflected from the limitation structure to the optical receiver 40. In some arrangements, the base layer 20A is formed of or includes a black core layer which absorbs lights instead of reflecting lights, and thus the light reflected by the barrier 70 to the optical receiver 40 may be reduced. The substrate structure (e.g., the substrate 10) and the limitation structure may collectively define a cavity C1 for accommodating the optical emitter 30, and the portion 510 (or the block structure) is disposed adjacent to the cavity C1 and configured to reflect a light from the optical emitter 30. In some arrangements, the portion 510 (or the block structure) and the combination of the base layer 20A and the barrier 70 (or the limitation structure) are disposed between the optical emitter 30 and the optical receiver 40. According to some arrangements of the present disclosure, with the base layer 20A and the barrier 70 both formed of black core layers, the overall thickness can be reduced, and the crosstalk of optical signals between the optical emitter and the optical receiver can be further effectively prevented.
In some arrangements, the electrode 420 of the optical receiver 40 is electrically connected to the conductive layer 102A through the conductive wire 92, the conductive layer 102, and the conductive via 10V4. In some arrangements, the optical package structure 4B does not include a barrier 70 illustrated in
The substrate 10 may be referred to as a substrate structure, and the base layer 20A may be referred to as a limitation structure over the substrate structure and configured to reduce lights reflected from the limitation structure to the optical receiver 40. The substrate structure (e.g., the substrate 10) and the limitation structure may collectively define a cavity C1 for accommodating the optical emitter 30, and the portion 510 (or the block structure) is disposed adjacent to the cavity C1 and configured to reflect a light from the optical emitter 30. In some arrangements, the portion 510 (or the block structure) and the base layer 20A (or the limitation structure) are disposed between the optical emitter 30 and the optical receiver 40. According to some arrangements of the present disclosure, with the base layer 20A formed of a black core layer and the barrier 70 is removed, the overall thickness of the optical package structure can be further reduced, and the crosstalk between optical signals of the optical emitter and the optical receiver can be effectively prevented.
In some arrangements, the connection portion 50R and the via portion 50V of the shielding structure is between the optical emitter 30 and the optical receiver 40. In some arrangements, the substrate 10 includes a circuit structure 10R1 electrically connected to the optical emitter 30 and a circuit structure 10R2 electrically connected to the optical receiver 40. In some arrangements, the circuit structure 10R1 includes the conductive layers 110, 110A, 103, and 103A and the conductive vias 10V1 and 10V2. In some arrangements, the circuit structure 10R2 includes the conductive layers 101, 101A, 102, and 102A and conductive vias 10V3 and 10V4. In some arrangements, the via portion 50V is between the circuit structure 10R1 and the circuit structure 10R2.
According to some arrangements of the present disclosure, with the arrangements of the electrical shielding element 50, the connection portion 50R, and the via portion 50V, crosstalk between the optical emitter and the optical receiver can be effectively prevented, and the interference between the circuit structure connected to the optical emitter and the circuit structure connected to the optical receiver can be effectively reduced as well.
In some arrangements, the electrode 420 of the optical receiver 40 is electrically connected to the conductive layer 102A through the conductive wire 92, the conductive layer 102, and the conductive via 10V4. In some arrangements, the cavity C2 (or the recess) is connected to and substantially aligned with the through hole C4 of the barrier 70. In some arrangements, the cavity C2 and the through hole C4 are formed by a single operation.
In some arrangements, the electrical shielding element 50 includes a vertical part 512 without an extension covering the surface 201 of the substrate 20. In some arrangements, a top surface of the vertical part 512 is substantially aligned with or coplanar with the surface 201 of the substrate 20.
In some arrangements, the electrical shielding element 50 includes a vertical part 512 without an extension covering the surface 201 of the substrate 20. In some arrangements, a top surface of the vertical part 512 is lower than the surface 201 of the substrate 20.
In some arrangements, the electrical shielding element 50 (or the portion 510) is embedded in the substrate 20 and spaced apart from the sidewall 205 of the cavity C1. In some arrangements, the electrical shielding element 50 (or the portion 510) is embedded in the substrate 20 and spaced apart from the sidewall 205 of the cavity C1 by a portion of the substrate 20 (or a portion of the base layer 20A). In some arrangements, referring to
According to some arrangements of the present disclosure, the electrical shielding element 50 (or the portion 510) is embedded in the substrate 20 and spaced apart from the sidewall 205 of the cavity C1, and thus it can prevent the electrical shielding element 50 (e.g., the metal material of the electrical shielding element 50) from affecting the light-emitting angle of the optical emitter 30.
In some arrangements, the electrical shielding element 50 (or the portion 510) is embedded in the substrate 20 and spaced apart from the sidewall 205 of the cavity C1. In some arrangements, the electrical shielding element 50 (or the portion 510) is embedded in the substrate 20 and spaced apart from the sidewall 205 of the cavity C1 by a portion of the substrate 20 (or a portion of the base layer 20A). In some arrangements, referring to
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In some cases, the two through holes of the barrier may be designed to be relatively close to each other; that is, the adjacent through holes are designed to be separated from each other by a relatively small distance. As a result, the small distance between the through holes may be too narrow, such that the two through holes cannot be formed within the relatively thin barrier before the barrier is laminated to the substrates. In contrast, according to some arrangements of the present disclosure, the barrier with one through hole C3 is laminated to the substrates, such that the substrates can serve as a support for the relatively thin barrier, and then the second through hole C4 can be formed in the barrier while the barrier together with the substrates have a relatively high structural strength. In addition, the cavity C2 and the through hole C4 can be formed by a single operation, and thus the cavity C2 and the through hole C4 are aligned with each other. Therefore, even with a predetermined distance or width between the through holes C3 and C4 is relatively small, the structure as well as the process for forming the structure can provide a relatively good workability and a relatively satisfactory structural strength. Accordingly, the yield can be improved.
Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,” “down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,” “lower,” “upper,” “over,” “under,” and so forth, are indicated with respect to the orientation shown in the figures unless otherwise specified. It should be understood that the spatial descriptions used herein are for purposes of illustration only, and that practical implementations of the structures described herein can be spatially arranged in any orientation or manner, provided that the merits of embodiments of this disclosure are not deviated from by such an arrangement.
As used herein, the terms “approximately,” “substantially,” “substantial” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can refer to a range of variation less than or equal to +10% of that numerical value, such as less than or equal to +5%, less than or equal to +4%, less than or equal to +3%, less than or equal to +2%, less than or equal to +1%, less than or equal to +0.5%, less than or equal to +0.1%, or less than or equal to +0.05%. For example, a first numerical value can be deemed to be “substantially” the same or equal to a second numerical value if the first numerical value is within a range of variation of less than or equal to +10% of the second numerical value, such as less than or equal to +5%, less than or equal to +4%, less than or equal to +3%, less than or equal to +2%, less than or equal to +1%, less than or equal to +0.5%, less than or equal to +0.1%, or less than or equal to +0.05%. For example, “substantially” perpendicular can refer to a range of angular variation relative to 90° that is less than or equal to +10°, such as less than or equal to +5°, less than or equal to +4°, less than or equal to +3°, less than or equal to +2°, less than or equal to +1°, less than or equal to +0.5°, less than or equal to +0.1°, or less than or equal to +0.05°.
Two surfaces can be deemed to be coplanar or substantially coplanar if a displacement between the two surfaces is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm. A surface can be deemed to be substantially flat if a displacement between a highest point and a lowest point of the surface is no greater than 5 μm, no greater than 2 μm, no greater than 1 μm, or no greater than 0.5 μm.
As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise.
As used herein, the terms “conductive,” “electrically conductive” and “electrical conductivity” refer to an ability to transport an electric current. Electrically conductive materials typically indicate those materials that exhibit little or no opposition to the flow of an electric current. One measure of electrical conductivity is Siemens per meter (S/m). Typically, an electrically conductive material is one having a conductivity greater than approximately 104 S/m, such as at least 105 S/m or at least 106 S/m. The electrical conductivity of a material can sometimes vary with temperature. Unless otherwise specified, the electrical conductivity of a material is measured at room temperature.
Additionally, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be understood flexibly to include numerical values explicitly specified as limits of a range, but also to include all individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly specified.
While the present disclosure has been described and illustrated with reference to specific embodiments thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be necessarily drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other embodiments of the present disclosure which are not specifically illustrated. The specification and drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, sub-divided, or re-ordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations of the present disclosure.