Patent Application
20190318991
This disclosure relates to an integrated circuit device used to support different applications by configuring via connections of a via layer.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Integrated circuit devices are used in numerous electronic systems. Computers, handheld devices, portable phones, televisions, industrial control systems, robotics, and telecommunication networking-to name just a few-all use integrated circuit devices. Integrated circuit devices may be developed using lithography techniques that pattern circuitry onto a substrate wafer that is diced to form a number of (generally identical) individual integrated circuit die. Each integrated circuit die for a particular application may include many different components, such as programmable logic fabric, digital or analog signal transmission circuitry, digital signal processing circuitry, application-specific data processing circuitry, memory, and so forth. The lithography techniques to form circuits on an integrated circuit die may involve using a variety of different steps, possibly including one or more photomasks (e.g., a photomask set) corresponding to that specific circuitry on the integrated circuit die. In other words, manufacturing an integrated circuit die that has a first functionality may involve a completely different process and/or photomask set as compared to an integrated circuit die that has a second functionality.
Various aspects of this disclosure may be better understood upon reading the following detailed description and upon reference to the drawings in which:
One or more specific embodiments will be described below. In an effort to provide a concise description of these embodiments, not all features of an actual implementation are described in the specification. It may be appreciated that in the development of any such actual implementation, as in any engineering or design project, numerous implementation-specific decisions must be made to achieve the developers' specific goals, such as compliance with system-related and business-related constraints, which may vary from one implementation to another. Moreover, it may be appreciated that such a development effort might be complex and time consuming, but would nevertheless be a routine undertaking of design, fabrication, and manufacture for those of ordinary skill having the benefit of this disclosure.
When introducing elements of various embodiments of the present disclosure, the articles “a,” “an,” and “the” are intended to mean that there are one or more of the elements. The terms “comprising,” “including,” and “having” are intended to be inclusive and mean that there may be additional elements other than the listed elements. Additionally, it should be understood that references to “one embodiment” or “an embodiment” of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features. Furthermore, the phrase A “based on” B is intended to mean that A is at least partially based on B. Moreover, unless expressly stated otherwise, the term “or” is intended to be inclusive (e.g., logical OR) and not exclusive (e.g., logical XOR). In other words, the phrase A “or” B is intended to mean A, B, or both A and B.
Circuitry of an integrated circuit device may be unique to the specific application for which the integrated circuit device is used. As such, the production of each integrated circuit device for a particular application may include additional and/or different fabrication steps, rendering a particular integrated circuit device designed for one application to be become inoperable or ineffective for to perform a different application function. These additional or different fabrication steps may relate to photomasks that are used to pattern circuitry for the specific application functions onto a substrate. Since the circuitry for one application function may be different than the circuitry of a different application function, the photomasks used for each of these circuitry patterns may not be used for both application functions. As will be discussed in more detail herein, producing the unique circuitry onto a substrate (e.g., wafer) during device fabrication includes the use of lithographic photomasks. Photomasks are silica plates with a pattern (e.g., circuit pattern) of opaque and transparent areas that are projected onto the substrate to define the layout of the integrated circuit. In some implementations, a set of photomasks may be used to define one or more pattern layers of a multilayered structure of the integrated circuit. In general, a photomask is placed over the substrate and short wavelength radiation (e.g., short wavelength light) is passed through to project the pattern onto the substrate surface. The patterns may guide the deposit or removal of material from the substrate.
In some implementations, integrated circuit devices include multiple layers, and often, these layers are fabricated in a sequential process. Accordingly, each of the multiple layers may be fabricated using a unique photomask or set of photomasks. As such, at least some of the photomask patterns used for a specific circuit design may be not be used for a different circuit design. Thus, producing multiple photomasks for the various integrated circuit devices and/or their multiple layers may have their own respective costs.
The integrated circuit device for a particular application may include one circuit to perform one function and another circuit to perform another function of the application. By way of example, an electronic signals transmitted on-chip between circuits or off-chip between other integrated circuits, may use different formats or standards. Each of these standards may be supported by a particular circuit and be associated with separate respective photomasks. However, the circuits for each of these different standards may include common components.
It may be desirable to maintain a single integrated circuit architecture with a driver circuit that is configurable to support each of these standards. Moreover, since a single circuit with common circuitry may be used to provide support the various standards, the overall costs of producing multiple photomasks for each circuit and/or multiple integrated circuit layers may be mitigated. To implement a configurable driver circuit in an integrated circuit device that may be configurable for various applications, a via layer may be used to connect components and circuitry between the layers of the integrated circuit device. Thus, via openings may be selectively located and formed (e.g., filled or coated with metal) on the via layer to create interconnections between the various components to implement a particular input/output (I/O) driver standard in the integrated circuit device. For example, a single circuit with a via layer may be used to configure the circuitry to implement a single-ended voltage-mode driver, a current-mode driver, and/or a true differential driver. Moreover, the circuitry may be configured to tolerate high voltage overstress, such as by using protection biasing. While this disclosure will primarily use the example of an ASIC, the systems and methods of this disclosure may apply to any suitable integrated circuit devices. For example, the methods and devices may be incorporated into numerous types of devices such as microprocessors, system on chip (SoC), or other integrated circuits. Exemplary integrated circuits include programmable array logic (PAL), programmable logic arrays (PLAs), field programmable logic arrays (FPLAs), electrically programmable logic devices (EPLDs), electrically erasable programmable logic devices (EEPLDs), logic cell arrays (LCAs), field programmable gate arrays (FPGAs), application specific standard products (ASSPs), and microprocessors, just to name a few.
With the foregoing in mind,
The circuit layers 12 and 14 may be designed to have a variety of possible connections at a variety of possible via sites. Vias are integrated circuit structures that allow circuitry on one layer to form a connection with circuitry on another layer. Depending on the via configuration of one or more via layers 16, the circuit layers 12 and 14 may have different functionalities. Thus, many different integrated circuit devices 10 may be manufactured using the same circuit layers 12 and 14, but the different integrated circuit devices 10 may be manufactured to have different functionalities by selecting a different via configuration for the one or more via layers 16. The one or more via layers 16 may be manufactured to have a variety of different possible via configurations, where each via configuration provides different connections that determine the functionality of the layers 12 and 14, even while the layers 12 and 14 may not be changed. Thus, by manufacturing the one or more via layers 16 using a particular selected photomask or photomask set that results in a particular via configuration, a functionality of the circuit layers 12 and 14 may be controlled. It should be appreciated that, while two circuit layers 12 and 14 and one or more via layers 16 have been shown by way of example, any suitable number of circuit layers and via layers may be used. Moreover, one or more via layers may also be disposed to connect to an outer surface for selectively connecting to circuitry in a 2.5D or 3D configuration (e.g., another integrated circuit device 10, an interposer, or Embedded Multi-Die Interconnect Bridge (EMIB) by Intel Corporation®).
To illustrate,
Next, the patterning step may include fabricating pattern from a photomask onto the wafer by exposing the wafer to light using the photomask. As previously discussed, photomasks are often formed from silica plates with a pattern, such as a circuit pattern, of opaque and transparent areas that are projected onto the wafer to define the layout of the integrated circuit. In some implementations, a set of photomasks may be used to define one or more pattern layers of the multilayered structure of the integrated circuit device 10. In general, the photomask is placed over the substrate and a short wavelength light is passed through to project the pattern onto the substrate surface.
While the common lithography steps of block 22 are common to all versions of the integrated circuit device 10 that are manufactured using the process 20A, different versions of the integrated circuit device 10 may have different functionalities associated with different applications (e.g., shown here as Application A, Application B, and Application C) depending on the particular via configuration of a via layer of the integrated circuit device 10. Thus, the process 20 may also include performing (block 24) lithography with mask(s) for Application A (e.g., a voltage-mode driver circuit) that produces one or more via layers that will form connections that cause the circuitry formed at block 22 to operate with a first functionality (e.g., voltage-mode driver). On the other hand, the process 20 may include performing (block 26) lithography with mask(s) for Application B (e.g., a current-mode driver circuit) that produces one or more via layers that will form connections that cause the circuitry formed at block 22 to operate with a second functionality (e.g., as a current-mode driver). Further, the process 20 may include performing (block 28) lithography with mask(s) for Application C (e.g., a true differential driver circuit) that produces one or more via layers that will form connections that cause the circuitry formed at block 22 operate with a third functionality (e.g., true differential driver) associated with Application C. Specifically, performing lithography for each of these applications may include selecting via sites of the via layer to configure for either the integrated circuit device 10 for Application A, Application B, or Application C. Thus, the one or more via layer photomasks or photomasks sets are used to pattern and selectively connect components for each of the different integrated circuit devices 10 (e.g., integrated circuits for each application A, B, and C) that may be manufactured by the process 20A.
The process 20 may include performing (block 30) the certain final common lithography steps, which may include steps related to the removal of coating and modification of electrical properties.
The location of the multiple via sites or openings may be based on the various possible application functions to be performed and the components used to perform such functions. The selectable via sites may be filled (e.g., configured or selected) or remain unfilled (e.g., not selected) depending on the specific application to be performed. Thus, when the via layer is configured for Application A by selecting particular via sites that connect the components corresponding to perform Application A, there may be via sites that remain unselected since the components connected to those via sites may not be used to perform the functions of Application A. Similarly, some of the via sites used to perform Application A may not be selected when the via layer is configured for Application B. As such, using a lithography process for each particular application (e.g., Applications A, B, and C) may be mitigated or avoided by using the configurable via layer. Thus, fewer photomasks and/or application specific integrated circuit devices 10 may be manufactured, resulting in lower manufacturing costs and more efficient integrated circuit devices 10. Upon configuring the via layer for the particular application, such as by selecting particular vias (e.g., filing via openings with metal) to interconnect components used for the particular application, the integrated circuit, or at least those vias selected, may have a static configuration.
To facilitate the reuse of circuitry or components between the layers of the single integrated circuit device 10 to implement different applications, vias may be used. For example, and referring back to Applications A and B, some of the circuitry components that are used for Application A may also be used for the circuitry for Application B. Thus, these circuitry components may be reused when the via layer is configured for either Application A or Application B. To illustrate,
As shown, the via layer 50 may include a vertical segment layer 52 (as indicated by the vertical bold lines) of metal segments and a horizontal segment layer 54 (as indicated by the horizontal and relatively thinner lines) of metal segments. The vertical segment layer 52 and the horizontal segment layer 54 may each include selectable via sites 56, which may be used to interconnect segments of the vertical and horizontal segment layers 52 and 54. In some implementations, jumpers 58 may be selectively placed vertically or horizontally along the segments of the vertical segment layer 52 and the horizontal segment layer 54 to facilitate vias connections that may otherwise be disconnected. For example, the jumpers 58 may facilitate in connecting or disconnecting via sites 56 to connect or disconnect segments. As such, the via layer 50 may be reconfigured using the jumpers 58. The circuitry components on the first circuit layer 12 and the second circuit layer 14 that are connected to a respective segment of the via layer 50 (e.g., vertical segment layer 52 and the horizontal segment layer 54) may be connected or disconnected using the via sites 56 to form a circuit for a particular application.
To illustrate, selected vias (e.g., via sites filled with metal to create interconnection) are indicated by darkened selectable via sites 56 in the depicted embodiments. As shown, jumpers 58A, B, C, D, and E create a link between selectable via sites 56 that are on the same segment layer. For example, selectable via sites 56A and 56B may reside on separate segments of the vertical segment layer 52. Accordingly, jumper 58A may connect these two segments, such that when the selectable via sites 56A and 56B are selected, components and/or circuitry on their respective segments may be connected. Similarly, jumpers 58B, 58C, 58D, and 58E may connect selectable via sites 56, such that the jumpers 58 allow a connection to be made between segments of the vertical segment layer 52 or the horizontal segment layer 54, and between the vertical segment layer 52 and the horizontal segment layer 54 when their respective selectable via sites 56 are selected.
Although jumpers 58 may be placed between segments of the vertical segment layer 52 and the horizontal segment layer 54, some of the selectable via sites 56 may not be selected, as indicated by the white selectable via sites 56. In such instances, segments of vertical segment layer 52 and the horizontal segment layer 54 may not be connected. For example, jumper 58E may connect two segments of the horizontal segment layer 54 when the selectable via sites 56 are selected. Since these selectable via sites 56 are not selected, the segments may not be connected and thus, the components or circuitry on those segments may not be interconnected. Moreover, in some implementations, non-selectable via sites 62 may exist on the vertical segment layer 52 and/or the horizontal segment layer 54. The non-selectable via sites 62 may include areas that may not be suitable for a selectable via site 56. These areas may not be adjacent or parallel to components on the other layers, may include jumper connections, or that may include base circuitry or application specific circuitry that is not compatible for use for a different application.
To further illustrate the connections between the layers 52 and 54 using jumpers 58 and/or selectable via sites 56,
Specifically, the selectable via sites 56 that are selected may be active sites used to short the path between the vertical segment layer 52 and the horizontal segment layer 54. In this manner, the components on the portion of the layer connected to the via site 56 may be used or unused depending on the selection of the selectable via site 56. Thus, using vias may reduce the number of application specific circuits and layers, and correspondingly, reduce the number of photomasks used to produce each of the layers. Moreover, since circuit components between layers of the integrated circuit device 10 may be reused, vias may reduce the amount of circuitry and silicon area that may otherwise be used for each application.
As previously discussed, the integrated circuit device 10 may include an input output driver circuit. A driver circuit for multiple standards (e.g., voltage-mode driver, current-mode driver, etc.) may each be formed using separate photomasks. However, both these driver circuits may include common components. As will be described herein, rather than forming separate driver circuits, the single via layer 50 may be used to connect the redundant components of circuitry between layers of the integrated circuit device 10 to configure circuitry and implement the various driver circuit standards in the integrated circuit device 10. As used herein, redundant components may refer to one or more common components to the circuit resulting from a first configuration, such as a voltage-mode driver configuration, and the circuit resulting from a different configuration, such as a current-mode driver configuration. Additionally or alternatively to selectable via sites 56, multiplexers may be used to dynamically configure and select specific circuitry to implement any of the driver circuit standards.
To illustrate,
In other embodiments, vias may be used in conjunction with or in place of multiplexer 70 of
Thus, by selecting or activating particular via sites 56A or 56B, the circuitry of the selected inputs (e.g., input A 72 or input B 74) may be included in the integrated circuit device 10 to be used for a particular driver circuit. Via sites 56 may be selected or unselected (e.g., remain unfilled) based on the application to be executed and the circuitry used for the particular application. As previously mentioned, via sites 56 of the via layer 50 may be selected to configure the integrated circuit device 10 by connecting redundant circuitry between the various layers of the integrated circuit device 10. In this manner, producing additional mask layers associated with each application specific integrated circuit device 10 and/or circuitry for a particular application of the integrated circuit device 10 may be mitigated.
To illustrate,
The configurable I/O driver circuit 100 may be configured to support various power supply values, drive strengths, and/or drive current based on the driver standard. These different configurations may be provided by selectively enabling one or more via sites 56 on one or more via layers 50 to connect or disconnect components connected to segments of the respective via site 56. As previously mentioned, via sites 56 may be selected or enabled by filling the via opening of the via site 56 with metal to interconnect the components connected to the respective via site 56. As shown, multiple vias sites 56 are connected to the various components of the driver circuit 100, and thus, may be enabled to implement a particular driver circuit, as will be discussed in
As shown, via sites 56A-56J, 56AA, and 56AC are selected, connecting circuitry components to implement a pair of current-mode differential drivers. Specifically, via sites 561 and 56J may connect two drivers together to create two differential drivers. Selected via sites 56A-56J may switch transistors 108A-108H (e.g., M1-M8) to “ON.” The gate of transistors 108C-108F corresponding to M3-M6 may be connected to the pre-driver circuit 102 when via sites 56E-56H are enabled. Enabling transistors 108A-108D (e.g., M1-M4), by selecting via site 56A-56D, may allow creating a current mirror on the top half and bottom half of the circuit 100 respectively. Selected via sites 56A-D may connect transistors 108A, 108B, 108G, and 108H (e.g., M1, M2, M7, and M8) to the biasing circuit 104. The biasing circuit 104 may include a common mode feedback, such as for a LVDS standard. The common mode feedback may ensure that the common mode of the output signal is biased within a specified range.
To support voltage-mode drivers,
Transistors 108C-108F (e.g., M3-M6) may be used to create the main voltage-mode driver, and as such, may be connected to supply and ground using selected via sites 56K-56N. The gate of transistor 108C and 108E (e.g., M3 and M5) may be connected to input signal (I_AP) 110A of the pre-driver circuit 102, such as by via site 56AA. This may allow transistor 108C and 108E to form a voltage-mode driver that is driving the signal from I_AP. On the other hand, the gates of transistor 108D and 108F (e.g., M4 and M6) may be connected to input (I_AN) 110B of the pre-driver circuit 102, such as by via site 56AB. This may allow transistor 108D and 108F to form a voltage-mode driver that is driving the signal from source I_AP. These input signals 110A and 110B may be transmitted from two independent sources. However, some technologies may supply a greater voltage to the single-ended drivers than may be tolerated by the single-ended drivers.
As shown, transistors 108A, 108B, 108G, and 108H (e.g., M1, M2, M7, and M8), may be connected to the pre-driver circuit 102 using via sites 56S, 56T, 56U, and 56V respectively. Transistors 108A and 108G may be connected to a source of the pre-driver circuit 102 that receives signals from input signal (I_AP) 110B, while 108B and 108H may be connected to another source that receives signals from input signal (I_AN) 110A. Thus, transistors 108A and 108G may receive input signals independently from transistors 108B and 108H.
To protect the transistors 108A, 108B, 108G, and 108H from receiving a high voltage, transistors 108C-108F (e.g., M3-M6) may be connected to the biasing circuit 104. The biasing circuit 104 may be used to allow a lower level of voltage (e.g., voltage within tolerance) to the gates to bias transistors 108C-108F. Transistors 108C-108F may serve as protection transistors for transistors 108A, 108B, 108G, and 108H.
Moreover, while the method operations have been described in a specific order, it should be understood that other operations may be performed in between described operations, described operations may be adjusted so that they occur at slightly different times or described operations may be distributed in a system which allows the occurrence of the processing operations at various intervals associated with the processing, as long as the processing of overlying operations is performed as desired.
While the embodiments set forth in the present disclosure may be susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and have been described in detail herein. However, it may be understood that the disclosure is not intended to be limited to the particular forms disclosed. The disclosure is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the disclosure as defined by the following appended claims. In addition, the techniques presented and claimed herein are referenced and applied to material objects and concrete examples of a practical nature that demonstrably improve the present technical field and, as such, are not abstract, intangible or purely theoretical. Further, if any claims appended to the end of this specification contain one or more elements designated as “means for [perform]ing [a function]. . . ” or “step for [perform]ing [a function]. . . ”, it is intended that such elements are to be interpreted under 35 U.S.C. 112(f). However, for any claims containing elements designated in any other manner, it is intended that such elements are not to be interpreted under 35 U.S.C. 112(f).
