Claims
- 1. A gate dielectric situated in a semiconductor device comprising:a silicon substrate, a spacer layer overlying said silicon substrate, said spacer layer being formed of substantially SiO2, an oxynitride layer formed by NO reoxidation method having a thickness between 1 Å and 40 Å and a standard deviation of the thickness from 0.001 Å to 0.035 Å overlying said spacer layer, and a SiO2 layer overlying said oxynitride layer.
- 2. A gate dielectric situated in a semiconductor device according to claim 1, wherein each of said spacer layer and said oxynitride layer has a thickness between 1 Å and 40 Å.
- 3. A gate dielectric situated in a semiconductor device according to claim 1, wherein said spacer layer is formed of a material containing at least 90% SiO2.
- 4. A gate stack situated in a semiconductor device comprising:a silicon substrate, a spacer layer overlying said silicon substrate, said spacer layer being formed of substantially SiO2, an oxynitride layer formed by NO reoxidation method having a thickness between 1 Å to 40 Å and a standard deviation of the thickness from 0.001 Å to 0.035 Å overlying the spacer layer, a SiO2 layer overlying said oxynitride layer, and a conductive gate overlying said SIO2layer.
- 5. A gate stack situated in a semiconductor device according to claim 4, wherein said conductive gate is a polysilicon gate.
- 6. A gate stack situated in a semiconductor device according to claim 4, wherein said oxynitride layer is a nitrogen-rich oxynitride having a nitrogen concentration in the range between about 1 and about 50 atomic percent.
- 7. A gate stack situated in a semiconductor device according to claim 4, wherein each of said spacer layer, said oxynitride layer and said SiO2 has a thickness between 1 Å and 40 Å.
- 8. A gate stack situated in a semiconductor device according to claim 4, wherein said spacer layer being formed of a material containing at least 90% SiO2.
- 9. A gate dielectric situated in a semiconductor device comprising:a silicon substrate having a top surface, a spacer layer overlying said top surface of the silicon substrate, said spacer layer being formed of at least 90% SiO2, and said oxynitride layer formed by NO reoxidation method having a thickness between 1 Å and 40 Å and a standard deviation of the thickness from 0.001 Å to 0.035 Å.
CROSS-REFERENCE TO RELATED APPLICATION
This is a divisional application of U.S. application Ser. No. 09/226,369, filed Jan. 6, 1999, now U.S. Pat. No. 6,245,616.
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