PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING SAME, SEMICONDUCTOR DEVICE

Abstract

A package structure includes N first pads, N redistribution layers, second pads and third pads. Each first pad is formed by a interconnect layer exposed by one via hole. Each redistribution layer covers the isolation layer and is electrically connected with a corresponding first pad. Some first pads are arranged side by side along a first direction near a first edge of the semiconductor functional structure, and other first pads are arranged side by side along the first direction near a second edge of the semiconductor functional structure. The exposed parts of each redistribution layer form a second and a third pad. Both an offset direction and an offset distance between a center point of the second pad and that of a corresponding first pad are same. A relative position between the second pad and the third pad for some redistribution layers is different from that for others.

Description

BACKGROUND

With the rapid increase of the popularity of electronic equipment and the vigorous development of the electronic equipment market, it is increasingly required that electronic products should be miniaturized and thinned while having high performance, multifunction, high reliability and convenience. The demands require better, lighter, thinner, higher packaging density, better electrical and thermal properties, higher reliability and higher cost performance of semiconductor devices.

In order to ensure the performance of semiconductor devices to meet the corresponding requirements, it is necessary to prepare ports on the package structure for testing and performing functional interaction.

SUMMARY

In view of this, in order to solve one or more of the related technical problems, embodiments of the disclosure provides a package structure, a method for manufacturing the same, and a semiconductor device.

According to an aspect of the embodiments of the disclosure, a package structure is provided. The package structure include an isolation layer, N first pads, N redistribution layers, a first insulating layer, second pads and third pads.

The isolation layer has a plurality of via holes. The isolation layer covers a surface of an interconnect layer, the via holes expose parts of the interconnect layer, and the interconnect layer is disposed on a surface of a semiconductor functional structure.

Each of the N first pads is formed by the interconnect layer exposed by one of the via holes. The N is a positive integer greater than 1.

Each of the redistribution layers covers the isolation layer and is electrically connected with a corresponding one of the N first pads, some first pads are arranged side by side along a first direction near a first edge of the semiconductor functional structure, other first pads are arranged side by side along the first direction near a second edge of the semiconductor functional structure, the first edge and the second edge are two opposite edges of the semiconductor functional structure.

The first insulating layer covers the redistribution layers and exposes parts of each of the redistribution layers.

The exposed parts of each of the redistribution layers form a second pad and a third pad. Both an offset direction and an offset distance between a center point of the second pad and a center point of a corresponding first pad are same for all the second pad. A relative position between the second pad and the third pad for some redistribution layers is different from a relative position between the second pad and the third pad for other redistribution layers. The first pads and the second pads are used for testing the semiconductor functional structure at different operating speeds. The third pads are used for achieving functional interaction corresponding to contents tested by the second pads.

According to another aspect of the embodiments of the disclosure, a semiconductor device is provided. The semiconductor device includes the package structure as described in the forgoing embodiments of the disclosure and a semiconductor functional structure.

According to yet another aspect of the embodiments of the disclosure, a method for manufacturing a package structure is provided. The method includes the following operations.

A semiconductor functional structure is provided. An interconnect layer is disposed on a surface of the semiconductor functional structure.

An isolation layer having a plurality of via holes is formed. The isolation layer covers a surface of the interconnect layer. The via holes expose parts of the interconnect layer, and each of the exposed parts of the interconnect layer forms a first pad. N first pads are formed. The first pads are used for a first type test. The N is a positive integer greater than 1.

After the first type test, N redistribution layers are formed on the N first pads and the isolation layer. Each of the redistribution layers covers the isolation layer and is electrically connected with a corresponding one of the N first pads. Some first pads are arranged side by side along a first direction near a first edge of the semiconductor functional structure. Other first pads are arranged side by side along the first direction near a second edge of the semiconductor functional structure. The first edge and the second edge are two opposite edges of the semiconductor functional structure.

A first insulating layer is formed. The first insulating layer covers the redistribution layers and exposes parts of each of the redistribution layers. The exposed parts of each of the redistribution layer form a second pad and a third pad. Both an offset direction and an offset distance between a center point of the second pad and a center point of a corresponding first pad are same for all second pads. A relative position between the second pad and the third pad for some redistribution layers is different from a relative position between the second pad and the third pad for other redistribution layers. The second pads are used for a second type test. The third pads are used for performing functional interaction corresponding to contents of the second type test. An operating speed of the semiconductor functional structure for the first type test is lower than an operating speed for the second type test.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional schematic diagram of a package structure provided in embodiments of the disclosure.

FIG. 2A is a cross-sectional schematic diagram of another package structure provided in embodiments of the disclosure.

FIG. 2B is a top view schematic diagram of FIG. 2A.

FIG. 2C is a cross-sectional schematic diagram of a package structure with a conductive pillar provided in embodiments of the disclosure.

FIG. 3 is a schematic diagram of a relative position of first pads and second pads provided in embodiments of the disclosure.

FIG. 4 is a schematic diagram of a relative position of the second pads and third pads provided in embodiments of the disclosure.

FIG. 5 is a flowchart of a method for manufacturing a package structure provided in embodiments of the disclosure.

FIG. 6A is a first schematic diagram of a process for manufacturing a package structure provided in embodiments of the disclosure.

FIG. 6B is a second schematic diagram of a process for manufacturing a package structure provided in embodiments of the disclosure.

FIG. 6C is a third schematic diagram of a process for manufacturing a package structure provided in embodiments of the disclosure.

FIG. 6D is a fourth schematic diagram of a process for manufacturing a package structure provided in embodiments of the disclosure.

In the above figures (which are not necessarily drawn to scale), similar reference numerals may describe similar components in different views. Similar reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate the various embodiments discussed herein by way of example and not limitation.

DETAILED DESCRIPTION

The invention relates to the technical field of semiconductors, in particular to a package structure, a method for manufacturing the same and a semiconductor device.

The technical solution of the disclosure will be further explained in detail below with reference to the drawings and embodiments. Although exemplary embodiments of the disclosure are shown in the drawings, it is to be understood that the disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the disclosure and to fully convey the scope of the disclosure to those skilled in the art.

The embodiments of the disclosure are described in more detail by way of example in the following paragraphs with reference to the drawings. The advantages and features of the disclosure will become more apparent from the following description and the claims. It is to be noted that the drawings are provided in a very simplified form with inaccurate proportions to illustrate the purposes of the embodiments of the disclosure in a convenient and clear way.

It is understood that the meanings of “on”, “up” and “above” of the disclosure should be interpreted in the widest manner, so that “on” not only means its meaning of “on” something “without intervening features or layers (that is, directly on something), but also includes” on “something with intervening features or layers.

In the embodiments of the disclosure, a term “A is connected to B” includes a case where A and B are in direct contact, or a case where A and B are in indirect contact through an intermediate conductive structure. Terms “first”, “second”, and so on are used to distinguish similar objects and need not be used to describe a particular order or priority.

In the embodiments of this disclosure, a term “layer” refers to a portion of an object that includes a region having a thickness. The layer may extend on a lower surface or an upper surface of the structure, and its area may be less than or equal to an area of the extended surface on which the layer lies. It is to be noted that the technical solution described in the embodiments of this disclosure can be arbitrarily combined without conflict.

A semiconductor functional structure involved in the embodiments of the disclosure is a part that will be used in a subsequent manufacturing process to form a final semiconductor device, and is a core part to realize main functions of the semiconductor device. The final semiconductor device may include, but is not limited to, a memory.

In a design of a package structure of a semiconductor device, such as a DRAM (Dynamic Random Access Memory), there are two modes to set pads: one is to window on a top metal; the other is to window on redistribution layers (RDL, Redistribution Layer).

Windowing on a top metal means that a passivation layer or an insulating layer is formed on a top metal layer of a semiconductor functional structure to protect the semiconductor functional structure from being broken. Then window regions are formed on the passivation layer or the insulating layer to expose parts of the top metal layer to form pads. A probe card test may be carried out on the pads, to test electrical performances of the semiconductor functional structure. A bonding wire may also be leaded out from the pad to realize electrical leading out of the semiconductor functional structure.

Windowing on redistribution layers means that a redistribution layers are formed on the top metal layer of the semiconductor functional structure. A passivation layer or an insulating layer is formed on the redistribution layers, and then windowing regions are formed on the passivation layer or the insulating layer, so as to expose parts of each of the redistribution layers and form two pads arranged side by side. One of the two pads is used for carrying out the punch needles test of probe card, and the other is used for leading out the bonding wires on the pads. The redistribution layers may play a role in adjusting positions of the pads in the semiconductor device, and may also play a role in strengthening power supply network of power ground.

It is to be understood that, the top metal layer is relatively thin, and there is a gasket structure below. As such, it is possible to run a probe card test and then bonding wire package is conducted in a packaging factory at the same windowing metal region, without affecting a yield of a wire bond package. Generally, a material of the redistribution layer is a metal. The redistribution layer is thicker than the top metal layer, and deep and rough marks will be resulted by a probe card test. The marks will affect the yield of the wire bond package. Therefore, in the redistribution layer, the pad for testing and is required to be distinguished from the pad for leading out bonding wires. No matter which of the above windowing modes is adopted in the package structure, there is no great influence on the function of the semiconductor device. Redistribution layer windowing is beneficial to improve performance, but the production cycle and production cost are increased.

In some implementations, generally, one of the above two windowing modes is selected to design a package structure according to an actual need of semiconductor device. However, in practical applications, there may be various needs, rather than a single one in a production process of the semiconductor devices. Examples of needs are given below:

For example, before a mass production of semiconductor devices (or “products”), there is a long process of functional debugging. During the debugging process, a test is conducted in a state where the operating speed of the semiconductor functional structures is low. At this stage, the top metal layer windowing mode is enough to achieve the packaging and testing of the semiconductor functional structures. However, when the debugging process is ended, the semiconductor functional structures need to be tested at a high operating speed state, it is necessary to adopt the redistribution layer windowing mode for the packaging test.

Based on the above, embodiments of the disclosure provide a package structure. Referring to FIG. 1, the package structure includes the mode of widowing on a top metal and the mode of windowing on redistribution layers. In the mode of opening windows on the top metal, a first type pad 102 is arranged in a top metal layer 101. The first type pad 102 may be used to perform a test at a low speed and lead out a bonding wire. In the mode of opening windows on the redistribution layers, there are two types of pads (a second type pad 104 and a third type pad 105) in a redistribution layer 103, the second type pad 104 is used to perform a test at a high speed, and the third type pad 105 is used to lead out a bonding wire.

On one hand, when performing the test at low speed with the first type pad 102, a probe card for the test needs to hit center points of all the first type pads 102. When performing the test at high speed with the second type pad 104, the probe card for the test needs to hit center points of all the second type pads 104. However, it can be seen from FIG. 1 that the first type pad 102 and the second pad 104 are in different layers of the package structure and that relative positions of the first type pad 102 and the second pad 104 in the different layers are different. For these reasons, in order to meet the requirements of the test at the low speed and the test at the high speed, two sets of test probe cards have to be made, which greatly increases test cost and test time.

On another hand, when there are a large number of test points, not all the first type pads 102 may be placed near one edge of the semiconductor functional structure. In this case, it is necessary to provide the first type pads at two opposite edges of the semiconductor functional structure. Accordingly, the redistribution layers 103 are also required to be provided at the opposite two edges of the semiconductor functional structure. However, since an area occupied by the second type pad 104 and the third type pad 105 together is larger than an area occupied by the first type pad 102, a redistribution layer 103 at a position of at least one of the edges is prone to extend beyond the edge.

Based on this, in order to further solve the above problems, the embodiments of the disclosure provide a package structure, a method for manufacturing the same and a semiconductor device. The package structure includes: an isolation layer having a plurality of via holes, N first pads, N redistribution layers, a first insulating layer, second pads and third pads. The isolation layer covers a surface of an interconnect layer. The via holes expose parts of the interconnect layer, and the interconnect layer is disposed on a surface of a semiconductor functional structure. Each of the N first pads is formed by the interconnect layer exposed by a corresponding via hole. The N is a positive integer greater than 1. Each of the N redistribution layers covers the isolation layer and is electrically connected with a corresponding one of the N first pads. Some first pads are arranged side by side along a first direction near a first edge of the semiconductor functional structure. Some other first pads are arranged side by side along the first direction near a second edge of the semiconductor functional structure. The first edge and the second edge are two opposite edges of the semiconductor functional structure. The first insulating layer covers and exposes parts of each of the redistribution layers. The exposed parts of each of the redistribution layers form a second pad and a third pad. Both an offset direction and an offset distance between a center point of a second pad and a center point of a corresponding first pad are same for all the second pads. A relative position between a second pad and a third pad for some the redistribution layers is different from a relative position between a second pad and a third pad in other redistribution layers. The first pads and the second pads are used for testing the semiconductor functional structure at different operating speeds. The third pads are used for performing functional interaction corresponding to a content tested by the second pads.

It is to be noted that, the first direction referred to in the embodiments of the disclosure is parallel to the surface of the semiconductor functional structure, the second direction referred to in the embodiments of the disclosure is parallel to the semiconductor functional structure and perpendicular to the first direction, and a third direction referred to in the embodiments of the disclosure is perpendicular to both the first direction and the second direction. In some embodiments, the first direction may be parallel to the X-axis direction, the second direction may be parallel to the Y-axis direction, and the third direction may be parallel to the Z-axis direction.

Referring to FIG. 2A, the package structure includes a substrate (not shown in FIG. 2A). A material for forming the substrate may include silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon on insulator (SOI), or germanium on insulator (GOI).

A semiconductor functional structure 200 is located on the substrate. Specifically, the semiconductor functional structure 200 includes a semiconductor functional layer 201 and a interconnect layer 202 located on a surface of the semiconductor functional layer 201. In the semiconductor functional layer 201, a plurality of functional structures may be provided according to actual needs. Accordingly, the interconnect layer 202 is used to lead out electrical signals of the functional structures in the semiconductor functional layer 201 to make the functional structures work. In some embodiments, the interconnect layer 202 includes a top metal layer, not only for leading out the electrical signals from the functional structure but also for supporting the semiconductor functional structure 200.

It is to be noted that, all signals connected to the redistribution layers formed in a subsequent process are connected to the interconnect layer 202, which ensures the function of the semiconductor functional structure 200 even without the redistribution layers. FIG. 2A is a cross-sectional view where part of the interconnect layer 202 has been removed. In practice, parts in the interconnect layer are not truncated, but interconnected, that is, the parts in the interconnect layer may be continuous on other sections.

An isolation layer 203 covers a surface of the interconnect layer 202, and is configured for isolating the interconnect layer 202 and the subsequently formed redistribution layer 206 in part of a region. A via hole 204 is provided in the isolation layer 203, and the via hole 204 exposes part of the interconnect layer 202. A shape of the via hole 204 may be cylindrical or inverted trapezoidal or any suitable shape. A material for forming the isolation layer 203 includes, but is not limited to, tetraethyl orthosilicate (TEOS).

A first pad 205 is formed by the interconnect layer 202 exposed by one of the via holes 204. A plurality of via holes 204 may be included within the isolation layer 203, such that a plurality of first pads 205 are formed by the exposure of the plurality of via holes 204. On one hand, the first pads 205 can be used for a first type test. On another hand, the first pads 205 can also be used to achieve functional interaction corresponding to a content of the first type test.

Illustratively, the first type test may be understood as some tests performed on the semiconductor functional structure at a lower operating speed. It is to be noted that, in a memory, an operating speed refers to a read-write speed of the memory. The achievement of the functional interaction corresponding to the content of the first type test may be understood as leading out bonding wires on the first pads. That is, when performing the first type test, the first pads 205 can be used to contact a probe card, and a plurality of probes in the probe card correspond to the N first pads one by one, so as to realize electrical connections between the interconnect layer and other test systems.

In practical application, when there are a large number of test points, not all the first pads 205 may be placed near one edge of the semiconductor functional structure. In this case, the first pads 205 may be arranged at two opposite edges of the semiconductor functional structure. Referring to FIG. 2B, there are the N first pads 205. The N first pads are divided into two parts, namely first part of the first pads 2051 and second part of the first pads 2052. The first part of the first pads 2051 includes M1 first pads, and the M1 first pads are arranged side by side along the first direction near a first edge 20a of the semiconductor functional structure. The second part of the first pads 2052 includes M2 first pads, and the M2 first pads are arranged side by side along the first direction near a second edge 20b of the semiconductor functional structure. The first edge 20a and the second edge 20b are two opposite edges of the semiconductor functional structure. Here, M1+M2=N.

It is to be noted that, FIG. 2A is a partial cross-sectional schematic diagram of a package structure where the first pad 205 is in direct contact with a redistribution layer 206. FIG. 2B is a top view of an example of a package structure, in which other layers are omitted in order to show a position arrangement of the first pads more clearly in FIG. 2B. FIG. 2C is a partial cross-sectional schematic diagram of a package structure where a first pad 205 is in indirect contact with a redistribution layer 206 through a conductive pillar 207.

In some embodiments, the number of first pads in the first part of the first pads 2051 and that in the second part of the first pads 2052 may be the same or different.

Specifically, the six first pads in FIG. 2B are divided into the first part of the first pads 2051 and the second part of the first pads 2052. The first part of the first pads 2051 includes three first pads arranged side by side along the first direction near the first edge of the semiconductor functional structure. The second part of the first pads 2052 includes three first pads arranged side by side along the first direction near the second edge of the semiconductor functional structure.

Referring to FIG. 2A, there are N redistribution layers 206 located on the surface of the isolation layer 203 and at the via holes 204. Each of the redistribution layers 206 covers the isolation layer 203. A redistribution layer 206 is in direct contact with the corresponding one of the N first pads 205.

The redistribution layer 206 can contact the first pad 205 in both a direct manner (FIG. 2A) and an indirect manner (i.e., a conductive material layer such as a conductive pillar 207 is provided between the redistribution layer 206 and the first pad 205, FIG. 2B and FIG. 2C). A material for forming the conductive pillar 207 may be the same as or different from that of the redistribution layer 206. It is to be noted that a height of the conductive pillar 207 may be less than or equal to a depth of the via hole 204. The height of the conductive pillar 207 shown in FIG. 2C is equal to the depth of the via hole 204.

In some embodiments, the package structure includes conductive pillars 207. There are a plurality of conductive pillars, and the plurality of conductive pillars are arranged side by side along the first direction.

In the embodiments described above, there may be one or more conductive pillars 207 within a same via hole 204. Adjacent ones of the conductive pillars 207 are isolated by an insulating material. Accordingly, conductive pillars 207 correspond to the first pads 205 one by one, that is, where there are a plurality of conductive pillars 207 in a same via hole 204, there are a plurality of first pads 205 at a bottom of the same via hole 204.

It is to be understood that, when there are a plurality of conductive pillars 207, all the plurality of conductive pillars 207 are connected to a corresponding redistribution layer 206 and the interconnect layer 202, so that the reliability of the electrical connection between the redistribution layer 206 and the interconnect layer 202 can be increased.

It is to be understood that, by providing the plurality of first pads 205 without changing bottom area of the via hole, it is beneficial to reduce total area of all the first pads 205 at the bottom of the same via hole 204, thereby reducing a parasitic capacitance between the first pads 205 and a surrounding conductive material, and further optimizing a signal transmission performance.

Referring to FIG. 2A, a first insulating layer 208 is located on the redistribution layer 206.

The first insulating layer 208 covers a surface of the redistribution layer 206. A redistribution layer 206 on an exposed part of the interconnect layer 202 may have a same thickness as the redistribution layer 206 on the surface of the isolation layer 203. In some embodiments, where a diameter of the via hole 204 is two times greater than a thickness of the redistribution layer 206. The redistribution layer 206 covers a sidewall and the bottom of the via hole 204, and surrounds a groove 209.

In some embodiments, referring to FIG. 2A, the redistribution layer 206 is in direct contact with the corresponding first pad 205. The package structure further includes a second insulating layer 210 located within the groove 209 surrounded by each of the redistribution layers. Hardness of a material of the second insulating layer 210 is less than hardness of the material of the redistribution layer 206. By doing so, on one hand, a stress of the package structure can be reduced and the reliability of the package structure can be increased. On another hand, compared with filling the groove 209 with the redistribution layer 206, filling the groove 209 with the material of the second insulating layer 210 can avoid generating more parasitic capacitance.

In some embodiments, the second insulating layer 210 and the first insulating layer 208 may be an integral structure or separate structures. When the two are of separate structures, the materials of the two may be different. FIG. 2A shows a case where the second insulating layer 210 and the first insulating layer 208 are of an integral structure. The material for forming the second insulating layer 210 includes, but is not limited to, polyimide (PI).

Referring to FIG. 2A, at least some of the N redistribution layers 206 include second pads 211 and third pads 212 at the exposed parts.

Here, a second pad 211 and a third pad 212 are provided in each of the N redistribution layers 206. In other words, N second pads 211 correspond to N third pads 212 one by one. The second pads 211 are used for a second type test, and the third pads 212 are used for achieving functional interaction corresponding to a content of the second type test. The second type test may be understood as some tests performed on the semiconductor functional structure at a higher operating speed. The achievement of the functional interaction corresponding to the content of the second type test may be understood as leading out bonding wires on the third pads and performing the signal interaction.

It is to be noted that, the second pads 211 and its corresponding third pad 212 may be provided continuously, that is, there is no partition wall between the second pad 211 and the third pad 212. The second pad 211 and the third pad 212 may also be spaced apart, that is, there is a partition wall between the second pad 211 and the third pad 212.

Here, where the second pad 211 and the third pad 212 are provided continuously, damage to the probe card caused by the partition wall can be avoided when a probe is not aimed during the test, thereby prolonging a service life of the probe card. Meanwhile, generation of impurities may be reduced, thus improving test efficiency. In addition, damage to the partition wall by the probe card is reduced, thus improving the reliability of the package structure as a whole.

When the partition wall is provided between the second pad 211 and the third pad 212, recognition accuracy for each pad by a machine can be improved during the test.

In the following embodiments, the description is given by taking an example that a partition wall is provided between the second pad 211 and the third pad 212, but it is to be understood that, the following description regarding to the partition wall is only used to illustrate the disclosure, but is not used to limit the scope of the disclosure.

In order to reach a situation that each probe in the probe card can correspond to a corresponding one of the second pads during the second type test, in the embodiments of the disclosure, an offset direction and an offset distance between a center point of a second pad 211 and a center point of a corresponding first pad 205 are same for all the second pads, such that the N first pads and the N second pads keep a same relative position. By doing so, after the first type test, a same set of probe cards can be aligned with center points of all the second pads 211 after moving from center points of the first pads 205 in a certain distance and a certain direction. That is, the second type test can be directly performed with the probe card on all the second pads to be tested without replacing a new probe card.

Meanwhile, the position relationships between the second pad 211 and the third pad 212 at different edges are different; by doing so, the second pads and the third pads can be located near the edges but not beyond the edges. A position setting mode of the first pads and the second pads is specified below through an example.

In some embodiments, the second pad and the third pad included in each of the N redistribution layers are arranged side by side along the second direction, the second direction is perpendicular to the first direction.

The first pads 205 are arranged at two opposite edges of the semiconductor functional structure. Illustratively, referring to FIG. 3, a left side of the arrow in FIG. 3 shows an example of an arrangement of the first pads 205, which is the same as FIG. 2B and is not repeated here.

Similarly, the N second pads are divided into two parts, namely a third part and a fourth part. The third part includes M1 second pads. The fourth part includes M2 second pads. The M1 second pads in the third part are arranged side by side along the first direction near the first edge of the semiconductor functional structure. The M2 second pads in the fourth part are arranged side by side along the second direction near the second edge of the semiconductor functional structure. Similarly, the N third pads are divided into two parts, namely a fifth part and a sixth part. The fifth part includes M1 third pads. The sixth part includes M2 third pads. The M1 third pads in the fifth part and the M1 second pads are arranged side by side along the second direction near the first edge of the semiconductor functional structure. The M2 third pads in the sixth part and the M2 second pads are arranged side by side along the second direction near the second edge of the semiconductor functional structure.

Illustratively, a right side of the arrow in FIG. 3 shows an example of an arrangement of the redistribution layers 206. Specifically, the six redistribution layers 206 are divided into two parts. Each of the parts includes three redistribution layers, the three redistribution layers 206 in each part are arranged side by side along the X-axis direction, and each of the redistribution layers 206 includes a second pad 211 and a corresponding one of the third pads 212. The second pad 211 and the third pad 212 are arranged side by side along the Y-axis direction. Dotted lines in FIG. 3 show straight lines where the center points of the first pads 205 are located.

In some embodiments, all the first pads 205, the second pads 211 and the third pads 212 are of strip shapes. A shape of an orthographic projection of each of the redistribution layers on a plane where the interconnect layer is located is of a strip shape. A width of each of the first pads 205 along the first direction may be the same as a width of each of the second pads 211 and each of the third pads 212 along the first direction. A length of each of the first pads 205 along the second direction may be different from a length of each of the second pads 211 and each of the third pads 212 along the second direction.

In some embodiments, an orthographic projection of a center point of each of the second pads on the plane where the interconnect layer is located is offset by a first distance along the second direction with respect to a center point of a corresponding first pad.

Illustratively, referring to FIG. 3, at the first edge 20a, the center point O₂ of each of the second pads is offset by the first distance H1 along the Y-axis direction relative to the center point O₁ of the corresponding first pad. Meanwhile, at the second edge 20b, the center point O₂ of each of the second pads is offset by the first distance H1 along the Y-axis direction relative to the center point O₁ of the corresponding first pad.

In some embodiments, first ends of the some first pads near the first edge and second ends of the some redistribution layers near the first edge are substantially flush along a third direction perpendicular to both the first direction and the second direction.

Third ends of the other first pads near the second edge and fourth ends of the other redistribution layers near the second edge are substantially flush along the third direction.

In some embodiments, in the some redistribution layers, second pads are located near the second ends and third pads are located away from the second ends.

In the other redistribution layers, second pads are located near the fourth ends and third pads are located away from the fourth ends.

In some other embodiments, in the some redistribution layers, the third pads are located near the second ends and the second pads are located away from the second ends. In the other redistribution layers, the third pads are located near the fourth ends and the second pads are located away from the fourth ends.

That is to say, on the premise that both an offset direction and an offset distance between a center point of a second pad and a center point of a corresponding first pad are same for all the second pads, the second pad may also be provided at a farther distance from the first pad.

It is to be understood that, where the second pads in the some redistribution layers are located near the second ends, and the second pads in the other redistribution layers are located near the fourth ends, probes move a shorter distance, as compared with the situation where the second pads in the some redistribution layers located away from the second ends and the second pads in the other redistribution layers located near the fourth ends. This can improve test efficiency and reduce a probability of error occurrence. In some embodiments, each of the redistribution layers further includes a first region for conductively connecting with the first pad.

In the some redistribution layers, both the second pad and the third pad located on one same side of the first region. In the other redistribution layers, the second pad and the third pad are respectively located on two sides of the first region.

It is to be understood that when the conductive pillar 207 is provided in the package structure, referring to FIG. 3 and FIG. 4, the first region 213 is in contact with the conductive pillar 207 and is located around the conductive pillar, so as to realize electrical connection between each of the first pad and the redistribution layer. When the conductive pillar 207 is not provided in the package structure, the first region 213 is located within the via hole 204. A material of the first region 213 may be the same as or different from the material of the redistribution layer 206 and may be any suitable conductive material.

In the embodiments of the disclosure, the relative position relationships between the second pads and the third pads are different. As shown in FIG. 4, in part of the package structure, the second pad is located between the conductive pillar and the third pad; in another part of the package structure, the conductive pillar 207 is located between the second pad 211 and the third pad 212. Based on this, the first region 213 may be disposed between a corresponding second pad 211 and third pad 212, or may be disposed on a same side of the corresponding second pad 211 and third pad 212.

In addition, it should be understood that when the conductive pillar 207 and/or the first region 213 is disposed between the corresponding second pad 211 and the third pad 212, the partition wall may be provided between the corresponding second pad 211 and third pad 212.

It is to be noted that, in order to more clearly show the relative position relationships among the first pad, the second pad and the third pad, FIG. 4 only shows one redistribution layer near the first edge 20a and one redistribution layer near the second edge 20b. In addition, FIG. 3 and FIG. 4 only schematically show the redistribution layer(s) near the first edge 20a and the corresponding redistribution layer(s) near the second edge 20b, the distance between them does not represent a distance in actual application. The actual distance may be set according to actual needs.

In the embodiments of the disclosure, the positions of the second pad and the third pad are different at different edges. With such a configuration, tests at two different operating speeds can be performed with one same set of probe cards. Compared with a situation that the test are performed with two sets of probe cards, test cost and test time are saved, and production cycle and manufacturing cost are reduced.

According to another aspect of the embodiments of the disclosure, a semiconductor device is provided. The semiconductor device includes a package structure as described in the forgoing embodiments of the disclosure and a semiconductor functional structure.

In some embodiments, the semiconductor device further includes a base plate and a plurality of dies that are stacked. Each of the dies includes a semiconductor functional structure and a package structure located on the semiconductor functional structure. Each of the dies is electrically connected to the base plate through wires on third pads in the package structure.

According to yet another aspect of the embodiments of the disclosure, a method for manufacturing a package structure is provided. As shown in FIG. 5, the method includes the following operations.

In S501, a semiconductor functional structure is provided. An interconnect layer is provided at a surface of the semiconductor functional structure.

In S502, an isolation layer having a plurality of via holes is formed. The isolation layer covers a surface of the interconnect layer. The via holes expose parts of the interconnect layer, and each of the parts of the interconnect layer exposed by the via holes corresponds to one first pad. N first pads are formed. The first pads are used for performing a first type test. The N is a positive integer greater than 1.

In S503, after the first type test is completed, N redistribution layers are formed on the N first pads and the isolation layer. Each of the redistribution layers covers the isolation layer and is electrically connected with a corresponding one of the N first pads. Some first pads are arranged side by side along a first direction near a first edge of the semiconductor functional structure. Other first pads are arranged side by side along the first direction at positions near a second edge of the semiconductor functional structure. The first edge and the second edge are two opposite edges of the semiconductor functional structure.

In S504, a first insulating layer is formed. The first insulating layer covers the redistribution layers and exposes parts of each of the redistribution layers. The exposed parts of the redistribution layer form a second pad and a third pad. Both an offset direction and an offset distance between a center point of the second pad and a center point of a corresponding first pad are same for all second pads A relative position between the second pads and the third pads in parts of the redistribution layers is different from a relative position between the second pads and the third pads in other parts of the redistribution layers. The second pads are used for performing a second type test. The third pads are used for achieving functional interaction corresponding to a content of the second type test. An operating speed of the semiconductor functional structure for the first type test is lower than an operating speed of the semiconductor functional structure for the second type test.

It is to be understood that the operations shown in FIG. 5 are not exclusive and that other operations may be performed before, after, or between any of the operations shown in FIG. 5. The order of the operations shown in FIG. 2 can be adjusted according to actual needs. FIG. 6A to FIG. 6D are cross-sectional schematic diagrams of a process for manufacturing a package structure provided by embodiments of the disclosure. The method for manufacturing the package structure provided by the embodiments of the disclosure will be described in detail with reference to FIG. 5 and FIG. 6A to FIG. 6D.

In S501, referring to FIG. 6A, a semiconductor functional structure 600 is provided, which includes a semiconductor functional layer 601 and a interconnect layer 602. The operation of providing a semiconductor functional structure 600 includes the following operations. A substrate (not shown in FIG. 6A) is provided. A semiconductor functional layer 601 is formed on the substrate. A interconnect layer 602 is formed on the semiconductor functional layer.

Specifically, the semiconductor functional layer 601 includes a single layer thin film or multiple layer thin films. The semiconductor functional layer has a conductive layer and/or a dielectric layer. In the semiconductor functional layer 601, functional structures may be provided according to actual needs. Accordingly, the interconnect layer 602 is used to lead out electrical signals of the functional structures in the semiconductor functional layer 601 to operate the functional structures. In some embodiments, the interconnect layer 602 includes a top metal layer, not only for leading out the electrical signals from the functional structure but also for supporting the semiconductor functional structure 600.

In some embodiments, the method further includes removing part of the interconnect layer 602 to reduce an area of the interconnect layer and reduce a parasitic capacitance generated by the interconnect layer. FIG. 6A is a cross-sectional view of a certain section after the part of the interconnect layer 602 are removed. In practice, the interconnect layer are not truncated, but are interconnected, that is, the interconnect layer may be continuous on other sections.

In S502, referring to FIG. 6B, an isolation layer 603 is formed on the interconnect layer 602. A material of the isolation layer includes, but is not limited to, tetraethyl orthosilicate.

Then, parts of the isolation layer are removed to form a plurality of via holes 604. The via holes expose parts of the interconnect layer, and each of the parts exposed by the via holes forms a first pad 605. N first pads 605 are formed. A shape of the via hole 604 may be cylindrical, inverted trapezoidal, or any suitable shape. A cross-sectional area of the via hole includes an area of an orthographic projection of the via hole on the plane where the interconnect layer is located. For example, when the via hole is of an inverted trapezoidal shape, the cross-sectional area of the first pad is the minimum cross-sectional area of the via hole.

The first pads 605 can be used to perform a first type test. Also, the first pads 205 can be used to achieve functional interaction corresponding to a content of the first type test, for example, signal interaction and lead out of bonding wires. The first type test may be understood as some tests performed on the semiconductor functional structure at a lower operating speed. It is to be noted that, in a memory, an operating speed refers to a read-write speed of the memory.

In S503, referring to FIG. 6C, redistribution layers 606 are formed on the isolation layer 603 and in the via holes 604.

A specific manner of forming the redistribution layers 606 on the isolation layer 603 includes the following operations. A new wire pattern is formed on the isolation layer by exposure and development, and then the redistribution layers are formed according to the new wire pattern by using an electroplating technique. The redistribution layers include new wire paths which are electrically connected with the interconnect layer.

Each of the redistribution layers 606 covers the isolation layer 603 and is electrically connected to a corresponding one of the N first pads 605. It is to be noted that, the first pads 605 include first part of the first pads and second part of the first pads. The first pads in the first part of the first pads are arranged side by side along a first direction near a first edge of the semiconductor functional structure. The first pads in the second part of the first pads are arranged side by side along the first direction at positions near a second edge of the semiconductor functional structure. The first edge and the second edge are two opposite edges of the semiconductor functional structure.

In S504, referring to FIG. 6D, a first insulating layer 608 is formed on the redistribution layers 606.

Then, parts of the first insulating layer 608 are removed to expose parts of the redistribution layer 606. The exposed parts of the redistribution layer form a second pad 611 and a third pad 612. The second pad 611 is used for performing a second type test, and the third pad 612 is used for achieving functional interactions corresponding to a content of the second type test. The second type test may be understood as some tests performed on the semiconductor functional structure at a higher operating speed. The positions of the second pad 611 and the third pad 612 may be selected and set according to actual needs.

It is to be noted that, in the embodiment, referring to FIG. 6D, the first insulating layer not only exposes parts of the redistribution layer to form the second pad and the third redistribution layer, but also exposes another part of the redistribution layer located above the first pad, so as to subsequently fill a second insulating layer 610 in a groove 609 formed by the redistribution layer. A density of the second insulating layer may be less than or equal to that of the first insulating layer. In other embodiments, the first insulating layer also covers a bottom and a sidewall of the groove 609 formed by the redistribution layer, and the second insulating layer 610 is subsequently formed in the groove 609 formed by the first insulating layer.

In other embodiments, the package structure also includes a conductive pillar. Accordingly, the method further includes the following operation. The conductive pillar is formed on the first pads after the first type test. The operation that the redistribution layers are formed on the first pads and the isolation layer includes that the redistribution layers are formed on the isolation layer and the conductive pillars. The redistribution layers are electrically connected with the interconnect layer through the conductive pillars.

In the embodiments of the disclosure, the relative position relationship between the second pad and the third pad may be set according to actual needs. For example, the second pad in the package structure is located between the conductive pillar and the third pad, and/or, the conductive pillar in the package structure is located between the second pad 611 and the third pad 612. Based on this, a relative position between the second pad 611 and the third pad 612 in parts of the redistribution layers 606 and a relative position between the second pad 611 and the third pad 612 in other parts of the redistribution layers 606 may be the same or different, which have been described before and are not repeated here.

Both an offset direction and an offset distance between a center point of a second pad and a center point of a corresponding first pad are same for all the second pads. By doing so, after the first type test, a same set of probe cards can be aligned with the center points of all the second pads 211 after moving a certain distance from the center points of the first pads 205 to a certain direction. That is, the second type test can be directly performed by the probe cards on all the second pads without replacing new probe cards.

In addition, in the foregoing embodiments of the disclosure, it is to be noted that a package structure compatible with the two types of tests is adopted, such that a semiconductor functional structure can be subjected to different types of tests at different process stages. However, it should be noted that when designing a layout of the package structure, it is necessary to reserve positions of the via holes of the redistribution layers on the top metal layer, so as to ensure that the top metal layer or any other photomask and process need not be changed when a redistribution layer needs to be added.

In the embodiments provided by the disclosure, it is to be understood that the disclosed apparatus and methods may be implemented in a non-target manner. The embodiments of the device described above are only schematic. For example, the division of the unit is only a logical function division, and there may be another division mode in actual implementation, such as: multiple units or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled with each other, or directly coupled.

The units described above as separate elements may or may not be physically separated, and the elements displayed as elements may or may not be physical elements, i.e. may be located in one place or may be distributed over multiple network elements. According to the actual needs, some or all of the units can be selected to achieve the purpose of the solutions of the embodiments.

The features disclosed in the several embodiments of methods or devices provided by the disclosure can be arbitrarily combined without conflict, in order to obtain a new embodiment of a method or of a device.

The above-mentioned are only the specific embodiments of the disclosure, and the scope of protection of the disclosure is not limited thereto. Within the technical scope of the disclosure, any skilled person familiar with the technical field may easily conceive of changes or substitutions, which should be covered within the scope of protection of the disclosure. Therefore, the scope of protection of the disclosure should be subject to the scope of protection of the claims.

Claims

1. A package structure, comprising: an isolation layer having a plurality of via holes, wherein the isolation layer covers a surface of an interconnect layer, the via holes expose parts of the interconnect layer, and the interconnect layer is disposed on a surface of a semiconductor functional structure;N first pads, wherein each of the first pads is formed by the interconnect layer exposed by one of the via holes, the N is a positive integer greater than 1;N redistribution layers, wherein a redistribution layer covers the isolation layer and is electrically connected with a corresponding one of the N first pads, some first pads are arranged side by side along a first direction near a first edge of the semiconductor functional structure, other first pads are arranged side by side along the first direction near a second edge of the semiconductor functional structure, the first edge and the second edge are two opposite edges of the semiconductor functional structure;a first insulating layer covering the redistribution layers and exposing parts of each of the redistribution layers; andsecond pads and third pads, wherein the exposed parts of each of the redistribution layers form a second pad and a third pad, both an offset direction and an offset distance between a center point of the second pad and a center point of a corresponding first pad are same for all the second pads, a relative position between the second pad and the third pad for some of the redistribution layers is different from a relative position between the second pad and the third pad for other redistribution layers; the first pads and the second pads are used for testing the semiconductor functional structure at different operating speeds, and the third pads are used for achieving functional interaction corresponding to contents tested by the second pads.

2. The package structure of claim 1, wherein the second pad and the third pad comprised in each of the N redistribution layers are arranged side by side along a second direction, the second direction is perpendicular to the first direction.

3. The package structure of claim 2, wherein an orthographic projection of the center point of the second pad on a plane where the interconnect layer is located is offset by a first distance along the second direction with respect to the center point of the corresponding first pad.

4. The package structure of claim 3, wherein an orthographic projection of each of the redistribution layers on the plane where the interconnect layer is located is of a strip shape.

5. The package structure of claim 4, wherein first ends of the some of the first pads near the first edge and second ends of the some of the redistribution layers near the first edge are substantially flush along a third direction perpendicular to both the first direction and the second direction; andwherein third ends of the other first pads near the second edge and fourth ends of the other redistribution layers near the second edge are substantially flush along the third direction.

6. The package structure of claim 5, wherein in the some of the redistribution layers, the second pads are located near the second ends and the third pads are located away from the second ends; andwherein in the other redistribution layers, the second pads are located near the fourth ends and the third pads are located away from the fourth ends.

7. The package structure of claim 6, wherein the redistribution layer further comprises a first region for conductively connecting with the corresponding first pad; andwherein in the some of redistribution layers, the second pads and the third pads are located at one side of first regions; and in the other redistribution layers, the second pads and the third pads respectively located at two sides of the first regions.

8. The package structure of claim 1, wherein the redistribution layer contacts with the corresponding first pad directly; orwherein the package structure further comprises a conductive pillar, wherein the conductive pillar is located between the redistribution layer and the corresponding first pad, and the redistribution layer is electrically connected with the interconnect layer through the conductive pillar.

9. The package structure of claim 8, wherein the package structure comprises the conductive pillar, wherein there are a plurality of conductive pillars, and the plurality of conductive pillars are arranged side by side along the first direction.

10. The package structure of claim 8, wherein the redistribution layer contacts with the corresponding first pad directly, and the package structure further comprises: second insulating layers located within grooves, wherein each of the grooves is surrounded by the redistribution layer, a hardness of a material of the second insulating layers is less than a hardness of a material of the redistribution layers.

11. A semiconductor device, comprising the package structure according to claim 1 and a semiconductor functional structure.

12. The semiconductor device of claim 11, further comprising: a base plate; anda plurality of dies that are stacked, wherein each of the dies comprises the semiconductor functional structure and the package structure located on the semiconductor functional structure,wherein each of the dies is electrically connected to the base plate through wires on the third pads in the package structure.

13. A method for manufacturing a package structure, comprising: providing a semiconductor functional structure, wherein an interconnect layer is disposed on a surface of the semiconductor functional structure;forming an isolation layer having a plurality of via holes, wherein the isolation layer covers a surface of the interconnect layer, the via holes expose parts of the interconnect layer, and each of the exposed parts of the interconnect layer forms a first pad, N first pads are formed; the first pads are used for a first type test, and the N is a positive integer greater than 1;forming N redistribution layers on the N first pads and the isolation layer after the first type test, wherein each of the redistribution layers covers the isolation layer and is electrically connected with a corresponding one of the N first pads, some of the first pads are arranged side by side along a first direction near a first edge of the semiconductor functional structure, other first pads are arranged side by side along the first direction near a second edge of the semiconductor functional structure, and the first edge and the second edge are two opposite edges of the semiconductor functional structure; andforming a first insulating layer covering the redistribution layers and exposing parts of each of the redistribution layers, wherein the exposed parts of each of the redistribution layers form a second pad and a third pad; both an offset direction and an offset distance between a center point of the second pad and a center point of a corresponding first pad are same for all second pads; a relative position between the second pad and the third pads for some of the redistribution layers is different from a relative position between the second pad and the third pad for other redistribution layers; the second pads are used for a second type test, third pads are used for performing functional interaction corresponding to contents of the second type test; and an operating speed of the semiconductor functional structure for the first type test is lower than an operating speed for the second type test.