Patent Application
20120024449
With each successive semiconductor technology generation, wafer diameters tend to increase and transistor sizes decrease, resulting in the need for an ever higher degree of accuracy and repeatability in substrate processing. Semiconductor substrate materials, such as silicon wafers, are routinely processed using plasma in vacuum chambers. Plasma processing techniques include sputter deposition, plasma-enhanced chemical vapor deposition (PECVD), resist strip, and plasma etch.
In a plasma processing chamber, process gas is excited into a plasma in a proximity of a substrate being processed. However, gas at other locations (such as gas holes, conduits, lift pin holes, plenums, and the like) in the plasma processing chamber can also be excited into an unwanted plasma under certain conditions. Such an unwanted plasma is called parasitic plasma. Parasitic plasma can occur in a plasma processing chamber due to many reasons, such as geometry of chamber components, gas pressure and gas chemistry used in plasma processing recipes, supply of radio frequency (RF) power, etc. Parasitic plasma can cause a variety of issues in plasma processing, such as particle contamination, spatial and temporal nonuniformity during processing, and/or premature failure of chamber components. It is therefore desirable to eliminate parasitic plasma in a plasma processing chamber.
Described herein is a component of a plasma processing chamber, comprising: a first layer of a non-metal material, the first layer having first and second opposing surfaces, the first surface exposed to plasma in the plasma processing chamber and the second surface not exposed plasma in the plasma processing chamber; a second layer of an electrically conductive material, the second layer bonded to the second surface of the first layer; a void space extending through the entire first and second layers; a tubular sleeve lining an interior surface of the void space in the second layer such that the second layer is not exposed in the void space and parasitic plasma can be prevented in the void space; wherein one end of the tubular sleeve is coplanar with facing surfaces of the first layer and the second layer and the other end of the tubular sleeve is coplanar with a lower surface of the second layer.
Described herein is a method and components of a plasma processing chamber for eliminating parasitic plasma. The method and components are not limited to a particular type of plasma processing chamber or a particular plasma processing technique. A plasma processing chamber can rely on a variety of mechanisms to generate plasma, such as inductive coupling (transformer coupling), helicon, electron cyclotron resonance, capacitive coupling (parallel plate). For instance, high density plasma can be produced in a transformer coupled plasma (TCP™) processing chamber, or in an electron cyclotron resonance (ECR) processing chamber. Transformer coupled plasma processing chambers, wherein RF energy is inductively coupled into the chambers, are available from Lam Research Corporation, Fremont, Calif. An example of a high-flow plasma processing chamber that can provide high density plasma is disclosed in commonly-owned U.S. Pat. No. 5,948,704, the disclosure of which is hereby incorporated by reference. Parallel plate plasma processing chambers, electron-cyclotron resonance (ECR) plasma processing chambers, and transformer coupled plasma (TCP™) processing chambers are disclosed in commonly-owned U.S. Pat. Nos. 4,340,462; 4,948,458; 5,200,232 and 5,820,723, the disclosures of which are hereby incorporated by reference.
By way of example, plasma can be produced in a parallel plate processing chamber such as the dual frequency plasma etching chamber described in commonly-owned U.S. Pat. No. 6,090,304, the disclosure of which is hereby incorporated by reference. A preferred parallel plate plasma processing chamber is a dual frequency capacitively coupled plasma processing chamber including an upper showerhead electrode and a substrate support. For purposes of illustration, embodiments herein are described with reference to a parallel plate type plasma processing chamber.
A parallel plate plasma processing chamber for plasma etching is illustrated in
The load locks 112 and 114 (if provided) include transfer devices to transfer substrates such as wafers from a wafer supply 162, through the chamber 110, and out to a wafer receptacle 164. A load lock pump 176 can provide a desired vacuum pressure in the load locks 112 and 114.
A vacuum pump 172 such as a turbo pump is adapted to maintain a desired pressure in the chamber 110. During plasma etching, the chamber pressure is controlled, and preferably maintained at a level sufficient to sustain a plasma. Too high a chamber pressure can disadvantageously contribute to etch stop while too low a chamber pressure can lead to plasma extinguishment. In a medium density plasma processing chamber, such as a parallel plate plasma processing chamber, preferably the chamber pressure is maintained at a pressure below about 200 mTorr (e.g., less than 100 mTorr such as 20 to 50 mTorr) (“about” as used herein means±10%).
The vacuum pump 172 can be connected to an outlet in a wall of the chamber 110 and can be throttled by a valve 173 in order to control the pressure in the chamber. Preferably, the vacuum pump is capable of maintaining a pressure within the chamber 110 of less than 200 mTorr while etching gases are flowed into the chamber 110.
The chamber 110 includes an upper electrode assembly 120 including an upper electrode 125 (e.g., showerhead electrode), and a substrate support 150. The upper electrode assembly 120 is mounted in an upper housing 130. The upper housing 130 can be moved vertically by a mechanism 132 to adjust the gap between the upper electrode 125 and the substrate support 150.
A process gas source 170 can be connected to the housing 130 to deliver process gas comprising one or more gases to the upper electrode assembly 120. In a preferred plasma processing chamber, the upper electrode assembly comprises a gas distribution system, which can be used to deliver process gas to a region proximate to the surface of a substrate. Gas distribution systems, which can comprise one or more gas rings, injectors and/or showerheads (e.g., showerhead electrodes), are disclosed in commonly-owned U.S. Pat. Nos. 6,333,272; 6,230,651; 6,013,155 and 5,824,605, the disclosures of which are hereby incorporated by reference.
The upper electrode 125 preferably comprises a showerhead electrode, which includes gas holes (not shown) to distribute process gas therethrough. The gas holes can have a diameter of 0.02 to 0.2 inch. The showerhead electrode can comprise one or more vertically spaced-apart baffle plates that can promote the desired distribution of process gas. The upper electrode and the substrate support may be formed of any suitable material such as graphite, silicon, silicon carbide, aluminum (e.g., anodized aluminum), or combinations thereof. A heat transfer liquid source 174 can be connected to the upper electrode assembly 120 and another heat transfer liquid source can be connected to the substrate support 150.
The substrate support 150 can have one or more embedded clamping electrodes for electrostatically clamping a substrate on an upper surface 155 (support surface) of the substrate support 150. The substrate support 150 can be powered by an RF source and attendant circuitry (not shown) such as RF matching circuitry. The substrate support 150 is preferably temperature controlled and may optionally include a heating arrangement (not shown). Examples of heating arrangements are disclosed in commonly assigned U.S. Pat. Nos. 6,847,014 and 7,161,121, which are hereby incorporated by reference. The substrate support 150 can support a semiconductor substrate such as a flat panel or 200 mm or 300 mm wafer on the support surface 155.
The substrate support 150 preferably includes passages therein for supplying a heat transfer gas such as helium under the substrate supported on the support surface 155 to control the substrate temperature during plasma processing thereof. For example, helium back cooling can maintain wafer temperature low enough to prevent burning of photoresist on the substrate. A method of controlling a temperature of a substrate by introducing a pressurized gas into a space between the substrate and the substrate support surface is disclosed in commonly-owned U.S. Pat. No. 6,140,612, the disclosure of which is hereby incorporated by reference.
The substrate support 150 can include lift pin holes (not shown), through which lift pins can be actuated vertically by suitable mechanisms and raise the substrate off the support surface 155 for transport into and out from the chamber 110. The lift pin holes can have a diameter of about 0.08 inch. Details of lift pin holes are disclosed in commonly owned U.S. Pat. Nos. 5,885,423 and 5,796,066, the disclosure of which is hereby incorporated by reference.
Void spaces such as the gas holes, helium passages, lift pin holes in the upper electrode 125 and the substrate support 150 can be prone to parasitic plasma. For example, if a void space extends across layers of materials with different relative permittivity at RF frequencies, excessive RF voltage can occur between the layers, under certain conditions (e.g. gas pressure, RF load, RF frequency, etc.). Such excessive RF voltage (e.g. 20 V or more) can be sufficient to cause parasitic plasma in the void space. Electrically conductive materials commonly used in the upper electrode 125 and the substrate support 150 can include aluminum, steel, graphite, and doped silicon. Exposed conductive interior surfaces of the void space (e.g. of gas holes) can concentrate electric fields and intensify parasitic plasma in their proximity, when RF power is supplied to the processing chamber 100 to generate plasma therein. DC breakdown voltage VB of a gas in parallel plates as a function of pressure p and gap distance d is given by the Paschen
where A and B are constants determined by the properties of the gas (e.g., temperature, gas composition and ionization potential) and y is a parameter related to materials of the parallel plates. AC breakdown voltage can be as little as one tenth of VB, especially in the vicinity of conductive surfaces that are exposed to the gas and concentrated electric fields.
In one embodiment, as shown in
The sleeve 300 can be a self-supporting sleeve affixed to the component 200 by any suitable means, such as adhesive, press fitting or the like. However, the sleeve 300 can have threads on its exterior surface that mate with threads in the laminate 200. The sleeve 300 can also be in a form of a coating applied on the interior surface of the void space 210 by any suitable coating means. For example, CVD, plasma spraying.
In another embodiment, as shown in
The sleeve described herein can also be used in cavities, holes, conduits, voids, plenums and/or other spaces prone to parasitic plasma in a plasma processing chamber. The sleeve can be made into a shape that fits interior conductive surfaces of these spaces. For example, the substrate support 150 can have sleeves in lift pin holes and/or helium passages.
While the sleeve for eliminating parasitic plasma, and the plasma exposed laminate having the sleeve therein have been described in detail with reference to specific embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made, and equivalents employed, without departing from the scope of the appended claims.
