Patent Application
20070262429
The present invention relates to aggregating integrated circuits and, in particular, to stacking integrated circuits in chip-scale packages and methods for creating stacked modules of chip-scale packages.
A variety of techniques are used to stack packed integrated circuits. Some methods require special packages, while other techniques stack packages configured for stand-alone deployment in an operating environment.
“Chip scale packaging” or CSP refers generally to packages that provide connection to an integrated circuit through a set of contacts (often embodied as “bumps” or “balls”) arrayed across a major surface of the package. Instead of leads emergent from a peripheral side of the package as in “leaded” packages, in a CSP, contacts are placed on a major surface and typically emerge from the planar bottom surface of the package. The absence of “leads” on package sides renders most stacking techniques devised for leaded packages inapplicable for CSP stacking.
CSP has enabled reductions in size and weight parameters for many applications. CSP is a broad category including a variety of packages from near chip scale to die-sized packages such as the die sized ball grid array (DSBGA). To meet the continuing demands for cost and form factor reductions concurrent with increasing capabilities and capacities, technologies that aggregate plural integrated circuit dies in a package been developed. The techniques and technology for stacking plural integrated circuit dies within a single package, however, are not generally applicable for stacking packages that are configured to allow stand-alone deployment in an operating environment.
There are several known techniques for stacking integrated circuit packages articulated in chip scale technology. A variety of previous techniques for stacking CSPs typically present complex structural arrangements and thermal or high frequency performance issues. For example, thermal performance is a characteristic of importance in CSP stacks. With increasing operating frequencies of most systems, high frequency performance issues are also increasingly important. Further, many stacking techniques result in modules that exhibit profiles taller than may be preferred for particular applications.
The industry has developed a variety of stacked module designs. Some of those designs employ flexible circuitry to connect stacked chip scale IC devices. Typically, such flex-based stack designs place a part of the flex circuitry beneath the stack and part of the flex circuitry between constituent ICs of the stack disposed in like orientations. This can result in unequal trace length. Further, typical CSP stack designs use solder balls to mount the assembly to the host platform. Thus, in some cases where such proven designs are present, a height penalty is paid. Consequently, alternatives are welcome.
Stacked module design and assembly techniques and systems that provide a thermally efficient, reliable structure that perform well at higher frequencies but do not add excessive height to the stack that can be manufactured at reasonable cost with readily understood and managed materials and methods are provided.
A stacked module employs flexible circuitry to connect CSP integrated circuits. A flexible circuit with obverse and reverse sides is disposed between two CSPs oriented face-to-face with the flex circuit between to form a precursor assembly. One or more flaps or extension parts of the flex circuitry extend from the perimeter of the facing CSPs. Contacts to connect the CSPs to an operating environment are disposed along the one or more flex circuitry flaps or extensions.
In a preferred embodiment, the CSP and flex circuit precursor assembly is disposed in a frame and the one or more flex circuitry flaps or extensions that extend out from beyond the perimeter of the CSP devices are disposed on the form or frame. The contacts disposed on the flex circuitry extension(s) are positioned along the bottom edge of the form or frame for deployment of the stacked module in an operating environment.
The present invention may be employed to advantage in numerous configurations and combinations of CSPs in modules provided for high-density memories, high capacity computing, and other applications. The present invention also provides methods for constructing stacked circuit modules and precursor assemblies with flexible circuitry.
The present invention can be used to advantage with CSP packages of a variety of sizes and configurations ranging from typical BGAs with footprints somewhat larger than the contained die to smaller packages such as, for example, die-sized packages such as DSBGA. Although the present invention is applied most frequently to chip scale packages that contain one die, it may be employed with chip scale packages that include more than one integrated circuit die.
CSP packages of a variety of types and configurations may be employed in preferred embodiments of the invention. CSPs such as, for example, those that are die-sized, as well those that are near chip-scale as well as the variety of ball grid array packages known in the art may be employed. Collectively, these will be known herein as chip scale packaged integrated circuits (CSPs) and preferred embodiments will be described in terms of CSPs, but the particular configurations used in the explanatory figures are not, however, to be construed as limiting. For example, the views of certain FIGS. herein are depicted with CSPs of a particular profile, but it should be understood that the figures are exemplary only. The invention may be employed to advantage in the wide range of CSP configurations available in the art where an array of connective elements is available from at least one major surface. The invention is advantageously employed with CSPs that contain memory circuits but may be employed to advantage with logic, computing, and other types of circuits where added capacity without commensurate PWB or other board surface area consumption is desired.
Typical CSPs, such as, for example, ball-grid-array (“BGA”), micro-ball-grid array (“μBGA”), and fine-pitch ball grid array (“FBGA”) packages have an array of connective contacts embodied, for example, as leads, bumps, solder balls, pads or balls along lower surface 18 of a plastic casing in any of several patterns and pitches (“contacts”). An external portion of the connective contacts is often finished with a ball of solder. Shown in
Frame 40 may be comprised of any of a large variety of materials with some preferred materials being thermally conductive. Plastic may also be used to create frame 40 in those embodiments where light weight and ease of fabrication are of concern. Further, frame 40 need not be contiguous and need not circumvent the entirety of the perimeter of the respective CSPs.
Flex circuitry 30 has two major sides “A” and “B”, along each of which there are disposed contact sites for connection of integrated circuits such as CSPs 12 and 14 as those of skill will understand often appreciation of this specification. One or more conductive layers may be employed in flex circuitry 30. The entire flex circuit may be flexible or, as those of skill in the art will recognize, a PCB structure made flexible in, for example, extension areas E to allow conformability around frame 40 as shown and rigid in other areas, such as the area between respective bodies 17 of CSPs 12 and 14 may be employed as an alternative flex circuit in the present invention. For example, structures known as rigid-flex may be employed.
Flex circuitry 30 is preferably a multi-layer flexible circuit structure that has at least two conductive layers. Preferably, the conductive layers are metal such as alloy 110. The use of plural conductive layers provides advantages such as, for example, the creation of a distributed capacitance intended to reduce noise or bounce effects that can, particularly at higher frequencies, degrade signal integrity, as those of skill in the art will recognize. However, a flex circuitry having a single conductive layer may also be employed in module 10.
Steps in a preferred method for fabricating modules such as the module 10 depicted in
Flex 30 is shown in
Although the present invention has been described in detail, it will be apparent to those skilled in the art that the invention may be embodied in a variety of specific forms and that various changes, substitutions and alterations can be made without departing from the spirit and scope of the invention. The described embodiments are only illustrative and not restrictive, and therefore the scope of the invention is indicated by the following claims.
