TREA

PHASE CHANGE MEMORY WITH MULTI-LEVEL PROGRAMMING

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Information

  • Patent Application
  • 20230301207
  • Publication Number
    20230301207
  • Date Filed
    March 16, 2022
    2 years ago
  • Date Published
    September 21, 2023
    8 months ago
Information
Abstract
A phase change memory (PCM) semiconductor device is provided. The PCM semiconductor device includes: a phase change material stack on a substrate, the phase change material stack including at least two phase change material layers each separated by an insulating layer; a first electrode on a first side of the phase change material stack; and a second electrode on a second side of the phase change material stack, wherein a first one of the phase change material layers has a length that is different from a length of a second one of the phase change material layers.
Description
Claims
  • 1. A phase change memory (PCM) device comprising: a phase change material stack on a substrate, the phase change material stack including at least two phase change material layers each separated by an insulating layer;a first electrode on a first side of the phase change material stack; anda second electrode on a second side of the phase change material stack,wherein a first one of the phase change material layers has a length that is different from a length of a second one of the phase change material layers.
  • 2. The PCM memory device according to claim 1, wherein the first and second phase change material layers are configured as nanowires.
  • 3. The PCM memory device according to claim 1, wherein a difference in the lengths of the first and second phase change material layers is sufficient to enable performance on a RESET operation on the first phase change material layer without the performance of a RESET operation on the second phase change material layer.
  • 4. The PCM memory device according to claim 3, wherein the first phase change material layer has a smaller length than that of the second phase change material layer.
  • 5. The PCM memory device according to claim 1, wherein a difference in the lengths of the first and second phase change material layers is sufficient to enable performance on a RESET operation on the second phase change material layer without the performance of a SET operation on the first phase change material layer.
  • 6. The PCM memory device according to claim 1, wherein a thickness of the first phase change material layer is different from a thickness of the second phase change material layer.
  • 7. The PCM memory device according to claim 1, wherein the first and second phase change material layers each include at least one selected from the group consisting of GeSe, As—S, Sb—Te and In2Se3GeAsTe, or GeSbTe (GST).
  • 8. The PCM memory device according to claim 1, wherein the phase change material stack has a symmetrical profile with a truncated conical shape.
  • 9. The PCM memory device according to claim 1, wherein at least one of the first and second phase change material layers is doped with at least one selected from the group consisting of aluminum oxide (Al2O3), silicon oxide (SiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), cerium oxide (CeO2), silicon nitride (SiN), and silicon oxynitride (SiON).
  • 10. The PCM memory device according to claim 1, wherein a side profile of the phase change material stack in slanted.
  • 11. A method of manufacturing a phase change memory (PCM) device, the method comprising: forming a phase change material stack on a substrate, the phase change material stack including at least two phase change material layers each separated by an insulating layer;forming a first electrode on a first side of the phase change material stack; andforming a second electrode on a second side of the phase change material stack,wherein a first one of the phase change material layers has a length that is different from a length of a second one of the phase change material layers.
  • 12. The method according to claim 11, wherein the first and second phase change material layers are configured as nanowires.
  • 13. The method according to claim 11, wherein a difference in the lengths of the first and second phase change material layers is sufficient to enable performance on a RESET operation on the first phase change material layer without the performance of a RESET operation on the second phase change material layer.
  • 14. The method according to claim 13, wherein the first phase change material layer has a smaller length than that of the second phase change material layer.
  • 15. The method according to claim 11, wherein a difference in the lengths of the first and second phase change material layers is sufficient to enable performance on a RESET operation on the second phase change material layer without the performance of a SET operation on the first phase change material layer.
  • 16. The method according to claim 11, wherein a thickness of the first phase change material layer is different from a thickness of the second phase change material layer.
  • 17. The method according to claim 11, wherein a material composition of the first phase change material layer is different from a material composition of the second phase change material layer.
  • 18. The method according to claim 11, wherein the first and second phase change material layers each include at least one selected from the group consisting of GeSe, As—S, Sb-Te and In2Se3GeAsTe, or GeSbTe (GST).
  • 19. The method according to claim 11, wherein at least one of the first and second phase change material layers is doped with at least one selected from the group consisting of aluminum oxide (Al2O3), silicon oxide (SiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), cerium oxide (CeO2), silicon nitride (SiN), and silicon oxynitride (SiON).
  • 20. The method according to claim 11, wherein a side profile of the phase change material stack in slanted.