Patent Application
20050287787
The invention relates to the field of dielectric films for semiconductor devices such as integrated circuits.
Several layers of dielectric material are typically used in an integrated circuit. For instance, interconnects are formed between transistors formed in a substrate, with overlying conductors inlaid in an interlayer dielectric (ILD). Often, several such layers are used, each of which includes the conductive lines as well as vias for making contact with conductors in underlying layers. In many cases, the conductors and vias are inlaid in an ILD with a damascene process.
The dielectric constant (k) of the dielectric material to a large degree, determines the capacitance between the various conductors and vias in the integrated circuit. It is desirable to have a low-k dielectric to reduce RC delays and cross-talk between the conductors.
Several dielectrics are used and proposed to be used to reduce this capacitance. One problem with the low-k dielectrics, is that they tend to be mechanically weak. This is particularly a problem since often, chemical mechanical polishing is needed to provide sufficient planarization for the multilayer interconnect structures. This and other stresses can cause a failure in a mechanically weak layer.
In the following description, the use and formation of porous ceramic materials in semiconductor devices such as integrated circuits is described. Numerous specific details are set forth, such as specific compounds, in order to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art that these specific details need not be used to practice the present invention. In other instances, well-known processing steps, such as deposition steps, are not described in detail in order not to unnecessarily obscure the present invention.
The mechanical strength of the dielectric layer in a semiconductor device, as mentioned earlier, is important particularly where the layer is subjected to chemical mechanical polishing (CMP) as is often done in a damascene process. Packaging stresses can be even higher than the CMP stresses, and is another particularly important point where the ILD must be resistant to cracking or deforming.
Typically, openings are formed in an ILD for both the vias and conductors in a damascene process. Metal is then deposited or plated into the openings. The metal covers the entire exposed surface of the ILD. A planarization step is used to remove the metal from the surface of the dielectric, most effectively with polishing. Unless the ILD is strong enough to withstand this polishing and other stresses, defects in the device can result. The other stresses include those associated with packaging and thermal cycling during ordinary use.
Generally, the mechanical strength of a dielectric material includes, but is not limited to, its elastic modulus, hardness and cohesive strength. For the most part, the mechanical strength tracks well with the elastic modulus, and consequently, for purposes of this patent, the elastic modulus, also referred to as Young's modulus, is used to evaluate mechanical strength. Young's modulus is defined as the stress-over-strain for a given material and is generally measured in giga-Pascals (GPa). This modulus varies from less than 0.1 for rubber, 3-5 for polyimides, 100 or less for soft metals, the mid-hundreds for many ceramics, to 1,000 for diamond.
As mentioned, a dielectric layer including the ILD should have a low-k when used in an integrated circuit, particularly when operating at a high frequency as do most modern circuits. A k of approximately 2.2 or lower is considered to be an acceptable dielectric constant for such circuits fabricated at a minimum pitch of around 32 nm. (The dielectric constant may be as high as 2.4 and still considered acceptable, consequently as used in this patent, “approximately 2.2” is intended to cover the upper range of k=2.4.) An acceptable mechanical strength, as measured by Young's modulus, for integrated circuit processing is considered to be 6 GPa or higher, preferably about 10 GPa or higher.
As described below in more detail, ceramic materials having in their dense matrix state (non-porous) a k greater than 2.2 are used as an ILD in a porous matrix. The k is lowered by reducing the density of the ceramic material. This is done by making the ceramic material porous while still maintaining sufficient mechanical strength. These materials have E values in excess of 6 GPa in the porous matrix, as will be discussed.
In general, ceramics are considered to be non-metallic materials that are strong and brittle. They are typically electric insulators, resistant to heat and often not easily attacked by chemicals. The ceramic films including those with nitrides, may be formed by several processes including using commercially available precursors, as will be described later.
As the density of a dielectric material decreases (increased porosity), its k decreases proportionally. The strength of the material as its density decreases is predicted by the formula: E=E0(ρm), where E=predicted Young's modulus, E0=Young's modulus of a dense matrix (original material before the material is made porous), ρ=density (proportional to porosity and k), and m=experimentally determined exponent.
By way of example, the calculated Young's modulus for CDO with k=2.2 (15% carbon, 30% porosity) is 4.1 GPa. By contrast, the calculated Young's modulus for porous SiO2 with k=2.2 (47% porosity) is 8.2 GPa.
Assume that a k of 2.2 is needed for a dielectric film. The table below identifies several ceramic materials, their initial k and E0 (dense film) and their porosity and E for a k of 2.2. Silicon dioxide is also shown in the table for purposes of comparison.
Consequently, porous BeO, MgO, Al2O3, Yb2O3, SiC, Si3N4, and AlN provide a better performing film than SiO2 since they are all stronger than SiO2 for a porosity that provides a k of 2.2.
To provide a ceramic film for use in a semiconductor device, a selection is first made of a ceramic material with an E0 greater than or equal to 100 GPa. The k of the film should be 15 or less. This is shown as 30 in
Plasma enhanced chemical vapor deposition (PECVD) of ceramic films is well-known. For example, zirconium tert-butoxide is used to deposit zirconium dioxide films with k=16 (see Byeong-Ok Cho, B.-O., et al., Appl. Phys. Lett., 80(16), 2002, 1052-1054). A precursor may be used for the deposition of the film such as Al(OC(CH3)4)4 for Al2O3, by PECVD, spin-on, or other conventional deposition techniques. Other precursors to deposit ceramic materials which are commercially available can be chosen from metal alkoxides (OR), acetates (OAc), acetonyl acetates, and hexafluoroacetonylacetates. Metal alkyl or olefin species also can be used if an oxidant such as O2 or N2O are added to the plasma. Nitrides are generally formed by adding ammonia or amines to the plasma.
Pore generating can be added by incorporating a carbon-based polymer in the film, by adding ethylene to the plasma, for example. The carbon based porogen can be removed at a later down-stream process step. For instance, the porogen can be thermally decomposed immediately after deposition, or even later after CMP processing to avoid etching porous materials in a damascene process, as will be described in conjunction with
Porogen may be incorporated in the film by adding a second polymerizable component to the deposition plasma. Alternatively, side chains attached to the precursor can be used that survive plasma deposition and that can be decomposed after deposition.
The porosity of the deposited film may also be obtained by increasing the deposition rate to produce a low-film density, for instance, by adding more oxidant to the plasma. This however, results in the immediate formation of the low-density porous film.
Several processes for forming low-density films are described in U.S. Patent publication number 20040026783 Al, published Feb. 12, 2004, entitled “Low-k Dielectric Film with Good Mechanical Strength”; U.S. Pat. No. application Ser. No. 10/377,061, filed Feb. 28, 2003, entitled “Forming a Dielectric Layer Using A Hydrocarbon-Containing Precursor”; U.S. patent application Ser. No. 10/394,104, filed Mar. 21, 2003, entitled “Forming a Dielectric Layer Using Porogens”; and U.S. patent application Ser. No. 10/746,485, filed Dec. 23, 2003, entitled “Method and Materials for Self-Aligned Dual Damascene Interconnect Structure.”
Referring now to
Now, as shown in
Following the formation of the openings, a barrier metal 48 is formed to line the openings as is typically done in a damascene process. As shown in
Then, a conductor such as copper or a copper alloy is plated onto the barrier layer 48, in an ordinary plating process. The plated metal also covers the upper surface of the layer 40 and is removed from that surface using CMP. The resultant structure is shown in
Now as shown in
Thus, the use of a ceramic material for a low-k, relatively high E layer has been described.
